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mmc: sdhci-esdhc-imx: name esdhc specific definitions with ESDHC_ prefix
Rename esdhc local definitions with ESDHC_ rather than SDHCI_ prefix, so that we can distinguish them from SDHCI core definitions from name. A couple of bit fields are also changed use shift for consistency and better readability. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Tested-by: Dirk Behme <dirk.behme@de.bosch.com> Signed-off-by: Chris Ball <cjb@laptop.org>
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@ -30,12 +30,12 @@
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#include "sdhci-pltfm.h"
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#include "sdhci-esdhc.h"
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#define SDHCI_CTRL_D3CD 0x08
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#define ESDHC_CTRL_D3CD 0x08
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/* VENDOR SPEC register */
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#define SDHCI_VENDOR_SPEC 0xC0
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#define SDHCI_VENDOR_SPEC_SDIO_QUIRK 0x00000002
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#define SDHCI_WTMK_LVL 0x44
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#define SDHCI_MIX_CTRL 0x48
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#define ESDHC_VENDOR_SPEC 0xc0
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#define ESDHC_VENDOR_SPEC_SDIO_QUIRK (1 << 1)
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#define ESDHC_WTMK_LVL 0x44
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#define ESDHC_MIX_CTRL 0x48
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/*
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* There is an INT DMA ERR mis-match between eSDHC and STD SDHC SPEC:
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@ -43,7 +43,7 @@
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* but bit28 is used as the INT DMA ERR in fsl eSDHC design.
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* Define this macro DMA error INT for fsl eSDHC
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*/
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#define SDHCI_INT_VENDOR_SPEC_DMA_ERR 0x10000000
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#define ESDHC_INT_VENDOR_SPEC_DMA_ERR (1 << 28)
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/*
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* The CMDTYPE of the CMD register (offset 0xE) should be set to
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@ -165,8 +165,8 @@ static u32 esdhc_readl_le(struct sdhci_host *host, int reg)
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}
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if (unlikely(reg == SDHCI_INT_STATUS)) {
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if (val & SDHCI_INT_VENDOR_SPEC_DMA_ERR) {
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val &= ~SDHCI_INT_VENDOR_SPEC_DMA_ERR;
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if (val & ESDHC_INT_VENDOR_SPEC_DMA_ERR) {
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val &= ~ESDHC_INT_VENDOR_SPEC_DMA_ERR;
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val |= SDHCI_INT_ADMA_ERROR;
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}
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}
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@ -192,9 +192,9 @@ static void esdhc_writel_le(struct sdhci_host *host, u32 val, int reg)
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* re-sample it by the following steps.
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*/
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data = readl(host->ioaddr + SDHCI_HOST_CONTROL);
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data &= ~SDHCI_CTRL_D3CD;
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data &= ~ESDHC_CTRL_D3CD;
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writel(data, host->ioaddr + SDHCI_HOST_CONTROL);
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data |= SDHCI_CTRL_D3CD;
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data |= ESDHC_CTRL_D3CD;
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writel(data, host->ioaddr + SDHCI_HOST_CONTROL);
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}
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}
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@ -203,15 +203,15 @@ static void esdhc_writel_le(struct sdhci_host *host, u32 val, int reg)
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&& (reg == SDHCI_INT_STATUS)
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&& (val & SDHCI_INT_DATA_END))) {
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u32 v;
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v = readl(host->ioaddr + SDHCI_VENDOR_SPEC);
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v &= ~SDHCI_VENDOR_SPEC_SDIO_QUIRK;
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writel(v, host->ioaddr + SDHCI_VENDOR_SPEC);
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v = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
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v &= ~ESDHC_VENDOR_SPEC_SDIO_QUIRK;
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writel(v, host->ioaddr + ESDHC_VENDOR_SPEC);
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}
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if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE)) {
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if (val & SDHCI_INT_ADMA_ERROR) {
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val &= ~SDHCI_INT_ADMA_ERROR;
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val |= SDHCI_INT_VENDOR_SPEC_DMA_ERR;
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val |= ESDHC_INT_VENDOR_SPEC_DMA_ERR;
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}
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}
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@ -253,9 +253,9 @@ static void esdhc_writew_le(struct sdhci_host *host, u16 val, int reg)
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&& (host->cmd->data->blocks > 1)
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&& (host->cmd->data->flags & MMC_DATA_READ)) {
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u32 v;
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v = readl(host->ioaddr + SDHCI_VENDOR_SPEC);
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v |= SDHCI_VENDOR_SPEC_SDIO_QUIRK;
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writel(v, host->ioaddr + SDHCI_VENDOR_SPEC);
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v = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
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v |= ESDHC_VENDOR_SPEC_SDIO_QUIRK;
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writel(v, host->ioaddr + ESDHC_VENDOR_SPEC);
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}
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imx_data->scratchpad = val;
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return;
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@ -266,9 +266,9 @@ static void esdhc_writew_le(struct sdhci_host *host, u16 val, int reg)
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val |= SDHCI_CMD_ABORTCMD;
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if (is_imx6q_usdhc(imx_data)) {
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u32 m = readl(host->ioaddr + SDHCI_MIX_CTRL);
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u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
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m = imx_data->scratchpad | (m & 0xffff0000);
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writel(m, host->ioaddr + SDHCI_MIX_CTRL);
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writel(m, host->ioaddr + ESDHC_MIX_CTRL);
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writel(val << 16,
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host->ioaddr + SDHCI_TRANSFER_MODE);
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} else {
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@ -487,7 +487,7 @@ static int sdhci_esdhc_imx_probe(struct platform_device *pdev)
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* to something insane. Change it back here.
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*/
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if (is_imx6q_usdhc(imx_data))
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writel(0x08100810, host->ioaddr + SDHCI_WTMK_LVL);
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writel(0x08100810, host->ioaddr + ESDHC_WTMK_LVL);
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boarddata = &imx_data->boarddata;
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if (sdhci_esdhc_imx_probe_dt(pdev, boarddata) < 0) {
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