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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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drm/amd: Add BIOS smu_info v3_3 required struct def.
Signed-off-by: Jerry (Fangzhi) Zuo <Jerry.Zuo@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Jerry (Fangzhi) Zuo
Alex Deucher
parent
c519113340
commit
60a5205fb5
@ -501,6 +501,32 @@ enum atom_cooling_solution_id{
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LIQUID_COOLING = 0x01
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};
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struct atom_firmware_info_v3_2 {
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struct atom_common_table_header table_header;
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uint32_t firmware_revision;
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uint32_t bootup_sclk_in10khz;
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uint32_t bootup_mclk_in10khz;
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uint32_t firmware_capability; // enum atombios_firmware_capability
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uint32_t main_call_parser_entry; /* direct address of main parser call in VBIOS binary. */
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uint32_t bios_scratch_reg_startaddr; // 1st bios scratch register dword address
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uint16_t bootup_vddc_mv;
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uint16_t bootup_vddci_mv;
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uint16_t bootup_mvddc_mv;
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uint16_t bootup_vddgfx_mv;
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uint8_t mem_module_id;
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uint8_t coolingsolution_id; /*0: Air cooling; 1: Liquid cooling ... */
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uint8_t reserved1[2];
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uint32_t mc_baseaddr_high;
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uint32_t mc_baseaddr_low;
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uint8_t board_i2c_feature_id; // enum of atom_board_i2c_feature_id_def
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uint8_t board_i2c_feature_gpio_id; // i2c id find in gpio_lut data table gpio_id
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uint8_t board_i2c_feature_slave_addr;
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uint8_t reserved3;
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uint16_t bootup_mvddq_mv;
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uint16_t bootup_mvpp_mv;
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uint32_t zfbstartaddrin16mb;
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uint32_t reserved2[3];
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};
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/*
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***************************************************************************
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@ -1169,7 +1195,29 @@ struct atom_gfx_info_v2_2
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uint32_t rlc_gpu_timer_refclk;
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};
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struct atom_gfx_info_v2_3 {
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struct atom_common_table_header table_header;
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uint8_t gfxip_min_ver;
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uint8_t gfxip_max_ver;
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uint8_t max_shader_engines;
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uint8_t max_tile_pipes;
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uint8_t max_cu_per_sh;
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uint8_t max_sh_per_se;
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uint8_t max_backends_per_se;
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uint8_t max_texture_channel_caches;
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uint32_t regaddr_cp_dma_src_addr;
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uint32_t regaddr_cp_dma_src_addr_hi;
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uint32_t regaddr_cp_dma_dst_addr;
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uint32_t regaddr_cp_dma_dst_addr_hi;
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uint32_t regaddr_cp_dma_command;
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uint32_t regaddr_cp_status;
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uint32_t regaddr_rlc_gpu_clock_32;
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uint32_t rlc_gpu_timer_refclk;
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uint8_t active_cu_per_sh;
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uint8_t active_rb_per_se;
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uint16_t gcgoldenoffset;
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uint32_t rm21_sram_vmin_value;
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};
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/*
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***************************************************************************
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@ -1198,6 +1246,76 @@ struct atom_smu_info_v3_1
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uint8_t fw_ctf_polarity; // GPIO polarity for CTF
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};
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struct atom_smu_info_v3_2 {
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struct atom_common_table_header table_header;
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uint8_t smuip_min_ver;
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uint8_t smuip_max_ver;
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uint8_t smu_rsd1;
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uint8_t gpuclk_ss_mode;
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uint16_t sclk_ss_percentage;
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uint16_t sclk_ss_rate_10hz;
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uint16_t gpuclk_ss_percentage; // in unit of 0.001%
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uint16_t gpuclk_ss_rate_10hz;
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uint32_t core_refclk_10khz;
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uint8_t ac_dc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for AC/DC switching, =0xff means invalid
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uint8_t ac_dc_polarity; // GPIO polarity for AC/DC switching
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uint8_t vr0hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR0 HOT event, =0xff means invalid
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uint8_t vr0hot_polarity; // GPIO polarity for VR0 HOT event
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uint8_t vr1hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR1 HOT event , =0xff means invalid
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uint8_t vr1hot_polarity; // GPIO polarity for VR1 HOT event
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uint8_t fw_ctf_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for CTF, =0xff means invalid
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uint8_t fw_ctf_polarity; // GPIO polarity for CTF
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uint8_t pcc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for PCC, =0xff means invalid
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uint8_t pcc_gpio_polarity; // GPIO polarity for CTF
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uint16_t smugoldenoffset;
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uint32_t gpupll_vco_freq_10khz;
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uint32_t bootup_smnclk_10khz;
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uint32_t bootup_socclk_10khz;
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uint32_t bootup_mp0clk_10khz;
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uint32_t bootup_mp1clk_10khz;
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uint32_t bootup_lclk_10khz;
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uint32_t bootup_dcefclk_10khz;
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uint32_t ctf_threshold_override_value;
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uint32_t reserved[5];
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};
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struct atom_smu_info_v3_3 {
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struct atom_common_table_header table_header;
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uint8_t smuip_min_ver;
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uint8_t smuip_max_ver;
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uint8_t smu_rsd1;
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uint8_t gpuclk_ss_mode;
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uint16_t sclk_ss_percentage;
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uint16_t sclk_ss_rate_10hz;
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uint16_t gpuclk_ss_percentage; // in unit of 0.001%
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uint16_t gpuclk_ss_rate_10hz;
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uint32_t core_refclk_10khz;
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uint8_t ac_dc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for AC/DC switching, =0xff means invalid
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uint8_t ac_dc_polarity; // GPIO polarity for AC/DC switching
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uint8_t vr0hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR0 HOT event, =0xff means invalid
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uint8_t vr0hot_polarity; // GPIO polarity for VR0 HOT event
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uint8_t vr1hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR1 HOT event , =0xff means invalid
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uint8_t vr1hot_polarity; // GPIO polarity for VR1 HOT event
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uint8_t fw_ctf_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for CTF, =0xff means invalid
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uint8_t fw_ctf_polarity; // GPIO polarity for CTF
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uint8_t pcc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for PCC, =0xff means invalid
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uint8_t pcc_gpio_polarity; // GPIO polarity for CTF
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uint16_t smugoldenoffset;
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uint32_t gpupll_vco_freq_10khz;
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uint32_t bootup_smnclk_10khz;
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uint32_t bootup_socclk_10khz;
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uint32_t bootup_mp0clk_10khz;
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uint32_t bootup_mp1clk_10khz;
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uint32_t bootup_lclk_10khz;
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uint32_t bootup_dcefclk_10khz;
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uint32_t ctf_threshold_override_value;
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uint32_t syspll3_0_vco_freq_10khz;
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uint32_t syspll3_1_vco_freq_10khz;
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uint32_t bootup_fclk_10khz;
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uint32_t bootup_waflclk_10khz;
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uint32_t reserved[3];
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};
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/*
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***************************************************************************
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Data Table smc_dpm_info structure
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@ -1283,7 +1401,6 @@ struct atom_smc_dpm_info_v4_1
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uint32_t boardreserved[10];
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};
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/*
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***************************************************************************
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Data Table asic_profiling_info structure
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@ -1864,6 +1981,55 @@ enum atom_smu9_syspll0_clock_id
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SMU9_SYSPLL0_DISPCLK_ID = 11, // DISPCLK
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};
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enum atom_smu11_syspll_id {
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SMU11_SYSPLL0_ID = 0,
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SMU11_SYSPLL1_0_ID = 1,
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SMU11_SYSPLL1_1_ID = 2,
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SMU11_SYSPLL1_2_ID = 3,
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SMU11_SYSPLL2_ID = 4,
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SMU11_SYSPLL3_0_ID = 5,
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SMU11_SYSPLL3_1_ID = 6,
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};
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enum atom_smu11_syspll0_clock_id {
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SMU11_SYSPLL0_SOCCLK_ID = 0, // SOCCLK
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SMU11_SYSPLL0_MP0CLK_ID = 1, // MP0CLK
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SMU11_SYSPLL0_DCLK_ID = 2, // DCLK
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SMU11_SYSPLL0_VCLK_ID = 3, // VCLK
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SMU11_SYSPLL0_ECLK_ID = 4, // ECLK
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SMU11_SYSPLL0_DCEFCLK_ID = 5, // DCEFCLK
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};
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enum atom_smu11_syspll1_0_clock_id {
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SMU11_SYSPLL1_0_UCLKA_ID = 0, // UCLK_a
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};
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enum atom_smu11_syspll1_1_clock_id {
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SMU11_SYSPLL1_0_UCLKB_ID = 0, // UCLK_b
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};
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enum atom_smu11_syspll1_2_clock_id {
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SMU11_SYSPLL1_0_FCLK_ID = 0, // FCLK
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};
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enum atom_smu11_syspll2_clock_id {
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SMU11_SYSPLL2_GFXCLK_ID = 0, // GFXCLK
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};
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enum atom_smu11_syspll3_0_clock_id {
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SMU11_SYSPLL3_0_WAFCLK_ID = 0, // WAFCLK
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SMU11_SYSPLL3_0_DISPCLK_ID = 1, // DISPCLK
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SMU11_SYSPLL3_0_DPREFCLK_ID = 2, // DPREFCLK
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};
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enum atom_smu11_syspll3_1_clock_id {
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SMU11_SYSPLL3_1_MP1CLK_ID = 0, // MP1CLK
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SMU11_SYSPLL3_1_SMNCLK_ID = 1, // SMNCLK
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SMU11_SYSPLL3_1_LCLK_ID = 2, // LCLK
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};
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struct atom_get_smu_clock_info_output_parameters_v3_1
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{
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union {
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