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mtd: nand: pxa3xx: make ECC configuration checks more explicit
The Armada BCH configuration in this driver uses one of the two following ECC schemes: 16-bit correction per 2048 bytes 16-bit correction per 1024 bytes These are sufficient for mapping to the 4-bit per 512-bytes and 8-bit per 512-bytes (respectively) minimum correctability requirements of many common NAND. The current code only checks for the required strength (4-bit or 8-bit) without checking the ECC step size that is associated with that strength (and simply assumes it is 512). While that is often a safe assumption to make, let's make it explicit, since we have that information. Signed-off-by: Brian Norris <computersforpeace@gmail.com> Acked-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Tested-by: Daniel Mack <zonque@gmail.com>
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@ -1360,9 +1360,13 @@ static int pxa_ecc_init(struct pxa3xx_nand_info *info,
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static int armada370_ecc_init(struct pxa3xx_nand_info *info,
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struct nand_ecc_ctrl *ecc,
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int strength, int page_size)
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int strength, int ecc_stepsize, int page_size)
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{
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if (strength == 4 && page_size == 4096) {
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/*
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* Required ECC: 4-bit correction per 512 bytes
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* Select: 16-bit correction per 2048 bytes
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*/
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if (strength == 4 && ecc_stepsize == 512 && page_size == 4096) {
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info->ecc_bch = 1;
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info->chunk_size = 2048;
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info->spare_size = 32;
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@ -1373,7 +1377,11 @@ static int armada370_ecc_init(struct pxa3xx_nand_info *info,
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ecc->strength = 16;
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return 1;
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} else if (strength == 8 && page_size == 4096) {
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/*
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* Required ECC: 8-bit correction per 512 bytes
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* Select: 16-bit correction per 1024 bytes
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*/
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} else if (strength == 8 && ecc_stepsize == 512 && page_size == 4096) {
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info->ecc_bch = 1;
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info->chunk_size = 1024;
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info->spare_size = 0;
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@ -1481,6 +1489,7 @@ static int pxa3xx_nand_scan(struct mtd_info *mtd)
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if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370)
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ret = armada370_ecc_init(info, &chip->ecc,
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chip->ecc_strength_ds,
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chip->ecc_step_ds,
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mtd->writesize);
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else
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ret = pxa_ecc_init(info, &chip->ecc,
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