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Samsung DTS ARM changes for v5.5

Browse Source 
1. Add ARM architected timers on Exynos5 for KVM-based virtualization,
 2. Extend chip identification needed for future Adaptive Supply Voltage,
 3. Add audio support to Arndale board,
 4. Fix init order of clock providers on s3c64xx,
 5. A lot of cleanups and adjustments of DTS with DT schema.
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Merge tag 'samsung-dt-5.5' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into arm/dt

Samsung DTS ARM changes for v5.5

1. Add ARM architected timers on Exynos5 for KVM-based virtualization,
2. Extend chip identification needed for future Adaptive Supply Voltage,
3. Add audio support to Arndale board,
4. Fix init order of clock providers on s3c64xx,
5. A lot of cleanups and adjustments of DTS with DT schema.

* tag 'samsung-dt-5.5' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
  ARM: dts: s3c64xx: Fix init order of clock providers
  ARM: dts: exynos: Rename SysRAM node to "sram"
  ARM: dts: exynos: Rename power domain nodes to "power-domain" in Exynos4
  ARM: dts: exynos: Add audio support (WM1811 CODEC boards) to Arndale board
  ARM: dts: exynos: Use defines for MCT interrupt GIC SPI/PPI specifier
  ARM: dts: exynos: Remove MCT subnode for interrupt map on Exynos54xx
  ARM: dts: exynos: Remove MCT subnode for interrupt map on Exynos5250
  ARM: dts: exynos: Remove MCT subnode for interrupt map on Exynos4412
  ARM: dts: exynos: Remove MCT subnode for interrupt map on Exynos4210
  ARM: dts: exynos: Rename Multi Core Timer node to "timer"
  ARM: dts: exynos: Split phandle in dmas property
  ARM: dts: exynos: Remove obsolete IRQ lines on Exynos3250
  ARM: dts: exynos: Add samsung,asv-bin property to Odroid XU3 Lite
  ARM: dts: exynos: Add "syscon" compatible string to chipid node on Exynos5
  ARM: dts: exynos: Add support ARM architected timers on Exynos5

Link: https://lore.kernel.org/r/20191021180453.29455-4-krzk@kernel.org
Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson 2019-10-21 14:37:07 -07:00
commit 60107c77a2
16 changed files with 126 additions and 113 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

13
arch/arm/boot/dts/exynos3250.dtsi
View File

@ -138,7 +138,7 @@ soc: soc {
#size-cells = <1>;
ranges;
sysram@2020000 {
sram@2020000 {
compatible = "mmio-sram";
reg = <0x02020000 0x40000>;
#address-cells = <1>;
@ -265,7 +265,7 @@ gic: interrupt-controller@10481000 {
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
};
mct@10050000 {
timer@10050000 {
compatible = "samsung,exynos4210-mct";
reg = <0x10050000 0x800>;
interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
@ -314,8 +314,7 @@ jpeg: codec@11830000 {
sysmmu_jpeg: sysmmu@11a60000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x11a60000 0x1000>;
interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "sysmmu", "master";
clocks = <&cmu CLK_SMMUJPEG>, <&cmu CLK_JPEG>;
power-domains = <&pd_cam>;
@ -355,8 +354,7 @@ dsi_0: dsi@11c80000 {
sysmmu_fimd0: sysmmu@11e20000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x11e20000 0x1000>;
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "sysmmu", "master";
clocks = <&cmu CLK_SMMUFIMD0>, <&cmu CLK_FIMD0>;
power-domains = <&pd_lcd0>;
@ -507,8 +505,7 @@ mfc: codec@13400000 {
sysmmu_mfc: sysmmu@13620000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x13620000 0x1000>;
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "sysmmu", "master";
clocks = <&cmu CLK_SMMUMFC_L>, <&cmu CLK_MFC>;
power-domains = <&pd_mfc>;

14
arch/arm/boot/dts/exynos4.dtsi
View File

@ -111,28 +111,28 @@ mipi_phy: video-phy {
syscon = <&pmu_system_controller>;
};
pd_mfc: mfc-power-domain@10023c40 {
pd_mfc: power-domain@10023c40 {
compatible = "samsung,exynos4210-pd";
reg = <0x10023C40 0x20>;
#power-domain-cells = <0>;
label = "MFC";
};
pd_g3d: g3d-power-domain@10023c60 {
pd_g3d: power-domain@10023c60 {
compatible = "samsung,exynos4210-pd";
reg = <0x10023C60 0x20>;
#power-domain-cells = <0>;
label = "G3D";
};
pd_lcd0: lcd0-power-domain@10023c80 {
pd_lcd0: power-domain@10023c80 {
compatible = "samsung,exynos4210-pd";
reg = <0x10023C80 0x20>;
#power-domain-cells = <0>;
label = "LCD0";
};
pd_tv: tv-power-domain@10023c20 {
pd_tv: power-domain@10023c20 {
compatible = "samsung,exynos4210-pd";
reg = <0x10023C20 0x20>;
#power-domain-cells = <0>;
@ -140,21 +140,21 @@ pd_tv: tv-power-domain@10023c20 {
label = "TV";
};
pd_cam: cam-power-domain@10023c00 {
pd_cam: power-domain@10023c00 {
compatible = "samsung,exynos4210-pd";
reg = <0x10023C00 0x20>;
#power-domain-cells = <0>;
label = "CAM";
};
pd_gps: gps-power-domain@10023ce0 {
pd_gps: power-domain@10023ce0 {
compatible = "samsung,exynos4210-pd";
reg = <0x10023CE0 0x20>;
#power-domain-cells = <0>;
label = "GPS";
};
pd_gps_alive: gps-alive-power-domain@10023d00 {
pd_gps_alive: power-domain@10023d00 {
compatible = "samsung,exynos4210-pd";
reg = <0x10023D00 0x20>;
#power-domain-cells = <0>;

27
arch/arm/boot/dts/exynos4210.dtsi
View File

@ -72,7 +72,7 @@ cpu1: cpu@901 {
};
soc: soc {
sysram: sysram@2020000 {
sysram: sram@2020000 {
compatible = "mmio-sram";
reg = <0x02020000 0x20000>;
#address-cells = <1>;
@ -90,7 +90,7 @@ smp-sysram@1f000 {
};
};
pd_lcd1: lcd1-power-domain@10023ca0 {
pd_lcd1: power-domain@10023ca0 {
compatible = "samsung,exynos4210-pd";
reg = <0x10023CA0 0x20>;
#power-domain-cells = <0>;
@ -106,26 +106,17 @@ l2c: l2-cache-controller@10502000 {
arm,data-latency = <2 2 1>;
};
mct: mct@10050000 {
mct: timer@10050000 {
compatible = "samsung,exynos4210-mct";
reg = <0x10050000 0x800>;
interrupt-parent = <&mct_map>;
interrupts = <0>, <1>, <2>, <3>, <4>, <5>;
clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
clock-names = "fin_pll", "mct";
mct_map: mct-map {
#interrupt-cells = <1>;
#address-cells = <0>;
#size-cells = <0>;
interrupt-map =
<0 &gic 0 57 IRQ_TYPE_LEVEL_HIGH>,
<1 &gic 0 69 IRQ_TYPE_LEVEL_HIGH>,
<2 &combiner 12 6>,
<3 &combiner 12 7>,
<4 &gic 0 42 IRQ_TYPE_LEVEL_HIGH>,
<5 &gic 0 48 IRQ_TYPE_LEVEL_HIGH>;
};
interrupts-extended = <&gic GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
<&combiner 12 6>,
<&combiner 12 7>,
<&gic GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
};
watchdog: watchdog@10060000 {

25
arch/arm/boot/dts/exynos4412.dtsi
View File

@ -188,7 +188,7 @@ pinctrl_3: pinctrl@106e0000 {
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
};
sysram@2020000 {
sram@2020000 {
compatible = "mmio-sram";
reg = <0x02020000 0x40000>;
#address-cells = <1>;
@ -206,7 +206,7 @@ smp-sysram@2f000 {
};
};
pd_isp: isp-power-domain@10023ca0 {
pd_isp: power-domain@10023ca0 {
compatible = "samsung,exynos4210-pd";
reg = <0x10023CA0 0x20>;
#power-domain-cells = <0>;
@ -243,25 +243,16 @@ isp_clock: clock-controller@10048000 {
clock-names = "aclk200", "aclk400_mcuisp";
};
mct@10050000 {
timer@10050000 {
compatible = "samsung,exynos4412-mct";
reg = <0x10050000 0x800>;
interrupt-parent = <&mct_map>;
interrupts = <0>, <1>, <2>, <3>, <4>;
clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
clock-names = "fin_pll", "mct";
mct_map: mct-map {
#interrupt-cells = <1>;
#address-cells = <0>;
#size-cells = <0>;
interrupt-map =
<0 &gic 0 57 IRQ_TYPE_LEVEL_HIGH>,
<1 &combiner 12 5>,
<2 &combiner 12 6>,
<3 &combiner 12 7>,
<4 &gic 1 12 IRQ_TYPE_LEVEL_HIGH>;
};
interrupts-extended = <&gic GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
<&combiner 12 5>,
<&combiner 12 6>,
<&combiner 12 7>,
<&gic GIC_PPI 12 IRQ_TYPE_LEVEL_HIGH>;
};
watchdog: watchdog@10060000 {

4
arch/arm/boot/dts/exynos5.dtsi
View File

@ -35,8 +35,8 @@ soc: soc {
#size-cells = <1>;
ranges;
chipid@10000000 {
compatible = "samsung,exynos4210-chipid";
chipid: chipid@10000000 {
compatible = "samsung,exynos4210-chipid", "syscon";
reg = <0x10000000 0x100>;
};

27
arch/arm/boot/dts/exynos5250-arndale.dts
View File

@ -11,6 +11,7 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/clock/samsung,s2mps11.h>
#include <dt-bindings/sound/samsung-i2s.h>
#include "exynos5250.dtsi"
/ {
@ -135,6 +136,12 @@ vcc_3v3_reg: regulator@5 {
};
};
sound {
compatible = "samsung,arndale-wm1811";
samsung,audio-cpu = <&i2s0>;
samsung,audio-codec = <&wm1811>;
};
fixed-rate-clocks {
xxti {
compatible = "samsung,clock-xxti";
@ -151,6 +158,16 @@ usb_hub: usb-hub {
};
};
&clock {
assigned-clocks = <&clock CLK_FOUT_EPLL>;
assigned-clock-rates = <49152000>;
};
&clock_audss {
assigned-clocks = <&clock_audss EXYNOS_MOUT_AUDSS>;
assigned-clock-parents = <&clock CLK_FOUT_EPLL>;
};
&cpu0 {
cpu0-supply = <&buck2_reg>;
};
@ -502,9 +519,11 @@ buck9_reg: BUCK9 {
&i2c_3 {
status = "okay";
wm1811a@1a {
wm1811: codec@1a {
compatible = "wlf,wm1811";
reg = <0x1a>;
clocks = <&i2s0 CLK_I2S_CDCLK>;
clock-names = "MCLK1";
AVDD2-supply = <&main_dc_reg>;
CPVDD-supply = <&main_dc_reg>;
@ -540,9 +559,15 @@ sata_phy_i2c:sata-phy@38 {
};
&i2s0 {
assigned-clocks = <&i2s0 CLK_I2S_RCLK_SRC>;
assigned-clock-parents = <&clock_audss EXYNOS_I2S_BUS>;
status = "okay";
};
&i2s0_bus {
samsung,pin-drv = <EXYNOS4_PIN_DRV_LV2>;
};
&mali {
mali-supply = <&buck4_reg>;
status = "okay";

41
arch/arm/boot/dts/exynos5250.dtsi
View File

@ -164,7 +164,7 @@ pmu {
};
soc: soc {
sysram@2020000 {
sram@2020000 {
compatible = "mmio-sram";
reg = <0x02020000 0x30000>;
#address-cells = <1>;
@ -233,28 +233,17 @@ clock_audss: audss-clock-controller@3810000 {
power-domains = <&pd_mau>;
};
mct@101c0000 {
timer@101c0000 {
compatible = "samsung,exynos4210-mct";
reg = <0x101C0000 0x800>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&mct_map>;
interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
<4 0>, <5 0>;
clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
clock-names = "fin_pll", "mct";
mct_map: mct-map {
#interrupt-cells = <2>;
#address-cells = <0>;
#size-cells = <0>;
interrupt-map = <0x0 0 &combiner 23 3>,
<0x1 0 &combiner 23 4>,
<0x2 0 &combiner 25 2>,
<0x3 0 &combiner 25 3>,
<0x4 0 &gic 0 120 IRQ_TYPE_LEVEL_HIGH>,
<0x5 0 &gic 0 121 IRQ_TYPE_LEVEL_HIGH>;
};
interrupts-extended = <&combiner 23 3>,
<&combiner 23 4>,
<&combiner 25 2>,
<&combiner 25 3>,
<&gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
};
pinctrl_0: pinctrl@11400000 {
@ -586,9 +575,9 @@ i2s0: i2s@3830000 {
compatible = "samsung,s5pv210-i2s";
status = "disabled";
reg = <0x03830000 0x100>;
dmas = <&pdma0 10
&pdma0 9
&pdma0 8>;
dmas = <&pdma0 10>,
<&pdma0 9>,
<&pdma0 8>;
dma-names = "tx", "rx", "tx-sec";
clocks = <&clock_audss EXYNOS_I2S_BUS>,
<&clock_audss EXYNOS_I2S_BUS>,
@ -606,8 +595,8 @@ i2s1: i2s@12d60000 {
compatible = "samsung,s3c6410-i2s";
status = "disabled";
reg = <0x12D60000 0x100>;
dmas = <&pdma1 12
&pdma1 11>;
dmas = <&pdma1 12>,
<&pdma1 11>;
dma-names = "tx", "rx";
clocks = <&clock CLK_I2S1>, <&clock CLK_DIV_I2S1>;
clock-names = "iis", "i2s_opclk0";
@ -621,8 +610,8 @@ i2s2: i2s@12d70000 {
compatible = "samsung,s3c6410-i2s";
status = "disabled";
reg = <0x12D70000 0x100>;
dmas = <&pdma0 12
&pdma0 11>;
dmas = <&pdma0 12>,
<&pdma0 11>;
dma-names = "tx", "rx";
clocks = <&clock CLK_I2S2>, <&clock CLK_DIV_I2S2>;
clock-names = "iis", "i2s_opclk0";

2
arch/arm/boot/dts/exynos5260.dtsi
View File

@ -180,7 +180,7 @@ chipid: chipid@10000000 {
reg = <0x10000000 0x100>;
};
mct: mct@100b0000 {
mct: timer@100b0000 {
compatible = "samsung,exynos4210-mct";
reg = <0x100B0000 0x1000>;
clocks = <&fin_pll>, <&clock_peri PERI_CLK_MCT>;

6
arch/arm/boot/dts/exynos5410.dtsi
View File

@ -222,9 +222,9 @@ pdma1: pdma@121b0000 {
audi2s0: i2s@3830000 {
compatible = "samsung,exynos5420-i2s";
reg = <0x03830000 0x100>;
dmas = <&pdma0 10
&pdma0 9
&pdma0 8>;
dmas = <&pdma0 10>,
<&pdma0 9>,
<&pdma0 8>;
dma-names = "tx", "rx", "tx-sec";
clocks = <&clock_audss EXYNOS_I2S_BUS>,
<&clock_audss EXYNOS_I2S_BUS>,

4
arch/arm/boot/dts/exynos5420-peach-pit.dts
View File

@ -1065,6 +1065,10 @@ &serial_3 {
status = "okay";
};
&timer {
arm,cpu-registers-not-fw-configured;
};
&tmu_cpu0 {
vtmu-supply = <&ldo10_reg>;
};

14
arch/arm/boot/dts/exynos5420.dtsi
View File

@ -434,9 +434,9 @@ mdma1: mdma@11c10000 {
i2s0: i2s@3830000 {
compatible = "samsung,exynos5420-i2s";
reg = <0x03830000 0x100>;
dmas = <&adma 0
&adma 2
&adma 1>;
dmas = <&adma 0>,
<&adma 2>,
<&adma 1>;
dma-names = "tx", "rx", "tx-sec";
clocks = <&clock_audss EXYNOS_I2S_BUS>,
<&clock_audss EXYNOS_I2S_BUS>,
@ -455,8 +455,8 @@ &adma 2
i2s1: i2s@12d60000 {
compatible = "samsung,exynos5420-i2s";
reg = <0x12D60000 0x100>;
dmas = <&pdma1 12
&pdma1 11>;
dmas = <&pdma1 12>,
<&pdma1 11>;
dma-names = "tx", "rx";
clocks = <&clock CLK_I2S1>, <&clock CLK_SCLK_I2S1>;
clock-names = "iis", "i2s_opclk0";
@ -471,8 +471,8 @@ i2s1: i2s@12d60000 {
i2s2: i2s@12d70000 {
compatible = "samsung,exynos5420-i2s";
reg = <0x12D70000 0x100>;
dmas = <&pdma0 12
&pdma0 11>;
dmas = <&pdma0 12>,
<&pdma0 11>;
dma-names = "tx", "rx";
clocks = <&clock CLK_I2S2>, <&clock CLK_SCLK_I2S2>;
clock-names = "iis", "i2s_opclk0";

4
arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts
View File

@ -26,6 +26,10 @@ &arm_a15_pmu {
status = "disabled";
};
&chipid {
samsung,asv-bin = <2>;
};
&pwm {
/*
* PWM 0 -- fan

46
arch/arm/boot/dts/exynos54xx.dtsi
View File

@ -45,8 +45,17 @@ arm_a15_pmu: arm-a15-pmu {
status = "disabled";
};
timer: timer {
compatible = "arm,armv7-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
clock-frequency = <24000000>;
};
soc: soc {
sysram@2020000 {
sram@2020000 {
compatible = "mmio-sram";
reg = <0x02020000 0x54000>;
#address-cells = <1>;
@ -64,30 +73,21 @@ smp-sysram@53000 {
};
};
mct: mct@101c0000 {
mct: timer@101c0000 {
compatible = "samsung,exynos4210-mct";
reg = <0x101c0000 0xb00>;
interrupt-parent = <&mct_map>;
interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>,
<8>, <9>, <10>, <11>;
mct_map: mct-map {
#interrupt-cells = <1>;
#address-cells = <0>;
#size-cells = <0>;
interrupt-map = <0 &combiner 23 3>,
<1 &combiner 23 4>,
<2 &combiner 25 2>,
<3 &combiner 25 3>,
<4 &gic 0 120 IRQ_TYPE_LEVEL_HIGH>,
<5 &gic 0 121 IRQ_TYPE_LEVEL_HIGH>,
<6 &gic 0 122 IRQ_TYPE_LEVEL_HIGH>,
<7 &gic 0 123 IRQ_TYPE_LEVEL_HIGH>,
<8 &gic 0 128 IRQ_TYPE_LEVEL_HIGH>,
<9 &gic 0 129 IRQ_TYPE_LEVEL_HIGH>,
<10 &gic 0 130 IRQ_TYPE_LEVEL_HIGH>,
<11 &gic 0 131 IRQ_TYPE_LEVEL_HIGH>;
};
interrupts-extended = <&combiner 23 3>,
<&combiner 23 4>,
<&combiner 25 2>,
<&combiner 25 3>,
<&gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
};
watchdog: watchdog@101d0000 {

4
arch/arm/boot/dts/exynos5800-peach-pi.dts
View File

@ -1034,6 +1034,10 @@ &serial_3 {
status = "okay";
};
&timer {
arm,cpu-registers-not-fw-configured;
};
&tmu_cpu0 {
vtmu-supply = <&ldo10_reg>;
};

4
arch/arm/boot/dts/s3c6410-mini6410.dts
View File

@ -165,6 +165,10 @@ buzzer {
};
};
&clocks {
clocks = <&fin_pll>;
};
&sdhci0 {
pinctrl-names = "default";
pinctrl-0 = <&sd0_clk>, <&sd0_cmd>, <&sd0_cd>, <&sd0_bus4>;

4
arch/arm/boot/dts/s3c6410-smdk6410.dts
View File

@ -69,6 +69,10 @@ ethernet@18000000 {
};
};
&clocks {
clocks = <&fin_pll>;
};
&sdhci0 {
pinctrl-names = "default";
pinctrl-0 = <&sd0_clk>, <&sd0_cmd>, <&sd0_cd>, <&sd0_bus4>;