mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-11-25 00:20:53 +07:00
Merge branch 'remotes/lorenzo/pci/tegra'
- Convert tegra to use shared DT "ranges" parsing (Rob Herring) * remotes/lorenzo/pci/tegra: PCI: tegra: Use pci_parse_request_of_pci_ranges()
This commit is contained in:
Bjorn Helgaas
commit
5f38dec435
@ -355,16 +355,6 @@ struct tegra_pcie {
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int irq;
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struct resource cs;
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struct resource io;
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struct resource pio;
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struct resource mem;
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struct resource prefetch;
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struct resource busn;
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struct {
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resource_size_t mem;
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resource_size_t io;
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} offset;
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struct clk *pex_clk;
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struct clk *afi_clk;
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@ -797,38 +787,6 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, 0x0bf1, tegra_pcie_relax_enable);
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, 0x0e1c, tegra_pcie_relax_enable);
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, 0x0e1d, tegra_pcie_relax_enable);
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static int tegra_pcie_request_resources(struct tegra_pcie *pcie)
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{
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struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie);
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struct list_head *windows = &host->windows;
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struct device *dev = pcie->dev;
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int err;
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pci_add_resource_offset(windows, &pcie->pio, pcie->offset.io);
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pci_add_resource_offset(windows, &pcie->mem, pcie->offset.mem);
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pci_add_resource_offset(windows, &pcie->prefetch, pcie->offset.mem);
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pci_add_resource(windows, &pcie->busn);
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err = devm_request_pci_bus_resources(dev, windows);
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if (err < 0) {
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pci_free_resource_list(windows);
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return err;
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}
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pci_remap_iospace(&pcie->pio, pcie->io.start);
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return 0;
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}
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static void tegra_pcie_free_resources(struct tegra_pcie *pcie)
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{
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struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie);
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struct list_head *windows = &host->windows;
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pci_unmap_iospace(&pcie->pio);
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pci_free_resource_list(windows);
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}
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static int tegra_pcie_map_irq(const struct pci_dev *pdev, u8 slot, u8 pin)
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{
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struct tegra_pcie *pcie = pdev->bus->sysdata;
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@ -909,36 +867,49 @@ static irqreturn_t tegra_pcie_isr(int irq, void *arg)
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*/
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static void tegra_pcie_setup_translations(struct tegra_pcie *pcie)
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{
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u32 fpci_bar, size, axi_address;
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u32 size;
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struct resource_entry *entry;
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struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie);
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/* Bar 0: type 1 extended configuration space */
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size = resource_size(&pcie->cs);
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afi_writel(pcie, pcie->cs.start, AFI_AXI_BAR0_START);
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afi_writel(pcie, size >> 12, AFI_AXI_BAR0_SZ);
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/* Bar 1: downstream IO bar */
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fpci_bar = 0xfdfc0000;
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size = resource_size(&pcie->io);
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axi_address = pcie->io.start;
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afi_writel(pcie, axi_address, AFI_AXI_BAR1_START);
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afi_writel(pcie, size >> 12, AFI_AXI_BAR1_SZ);
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afi_writel(pcie, fpci_bar, AFI_FPCI_BAR1);
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resource_list_for_each_entry(entry, &bridge->windows) {
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u32 fpci_bar, axi_address;
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struct resource *res = entry->res;
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/* Bar 2: prefetchable memory BAR */
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fpci_bar = (((pcie->prefetch.start >> 12) & 0x0fffffff) << 4) | 0x1;
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size = resource_size(&pcie->prefetch);
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axi_address = pcie->prefetch.start;
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afi_writel(pcie, axi_address, AFI_AXI_BAR2_START);
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afi_writel(pcie, size >> 12, AFI_AXI_BAR2_SZ);
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afi_writel(pcie, fpci_bar, AFI_FPCI_BAR2);
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size = resource_size(res);
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/* Bar 3: non prefetchable memory BAR */
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fpci_bar = (((pcie->mem.start >> 12) & 0x0fffffff) << 4) | 0x1;
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size = resource_size(&pcie->mem);
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axi_address = pcie->mem.start;
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afi_writel(pcie, axi_address, AFI_AXI_BAR3_START);
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afi_writel(pcie, size >> 12, AFI_AXI_BAR3_SZ);
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afi_writel(pcie, fpci_bar, AFI_FPCI_BAR3);
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switch (resource_type(res)) {
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case IORESOURCE_IO:
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/* Bar 1: downstream IO bar */
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fpci_bar = 0xfdfc0000;
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axi_address = pci_pio_to_address(res->start);
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afi_writel(pcie, axi_address, AFI_AXI_BAR1_START);
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afi_writel(pcie, size >> 12, AFI_AXI_BAR1_SZ);
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afi_writel(pcie, fpci_bar, AFI_FPCI_BAR1);
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break;
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case IORESOURCE_MEM:
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fpci_bar = (((res->start >> 12) & 0x0fffffff) << 4) | 0x1;
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axi_address = res->start;
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if (res->flags & IORESOURCE_PREFETCH) {
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/* Bar 2: prefetchable memory BAR */
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afi_writel(pcie, axi_address, AFI_AXI_BAR2_START);
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afi_writel(pcie, size >> 12, AFI_AXI_BAR2_SZ);
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afi_writel(pcie, fpci_bar, AFI_FPCI_BAR2);
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} else {
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/* Bar 3: non prefetchable memory BAR */
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afi_writel(pcie, axi_address, AFI_AXI_BAR3_START);
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afi_writel(pcie, size >> 12, AFI_AXI_BAR3_SZ);
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afi_writel(pcie, fpci_bar, AFI_FPCI_BAR3);
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}
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break;
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}
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}
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/* NULL out the remaining BARs as they are not used */
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afi_writel(pcie, 0, AFI_AXI_BAR4_START);
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@ -2157,76 +2128,10 @@ static int tegra_pcie_parse_dt(struct tegra_pcie *pcie)
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struct device *dev = pcie->dev;
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struct device_node *np = dev->of_node, *port;
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const struct tegra_pcie_soc *soc = pcie->soc;
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struct of_pci_range_parser parser;
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struct of_pci_range range;
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u32 lanes = 0, mask = 0;
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unsigned int lane = 0;
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struct resource res;
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int err;
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if (of_pci_range_parser_init(&parser, np)) {
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dev_err(dev, "missing \"ranges\" property\n");
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return -EINVAL;
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}
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for_each_of_pci_range(&parser, &range) {
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err = of_pci_range_to_resource(&range, np, &res);
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if (err < 0)
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return err;
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switch (res.flags & IORESOURCE_TYPE_BITS) {
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case IORESOURCE_IO:
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/* Track the bus -> CPU I/O mapping offset. */
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pcie->offset.io = res.start - range.pci_addr;
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memcpy(&pcie->pio, &res, sizeof(res));
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pcie->pio.name = np->full_name;
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/*
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* The Tegra PCIe host bridge uses this to program the
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* mapping of the I/O space to the physical address,
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* so we override the .start and .end fields here that
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* of_pci_range_to_resource() converted to I/O space.
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* We also set the IORESOURCE_MEM type to clarify that
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* the resource is in the physical memory space.
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*/
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pcie->io.start = range.cpu_addr;
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pcie->io.end = range.cpu_addr + range.size - 1;
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pcie->io.flags = IORESOURCE_MEM;
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pcie->io.name = "I/O";
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memcpy(&res, &pcie->io, sizeof(res));
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break;
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case IORESOURCE_MEM:
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/*
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* Track the bus -> CPU memory mapping offset. This
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* assumes that the prefetchable and non-prefetchable
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* regions will be the last of type IORESOURCE_MEM in
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* the ranges property.
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* */
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pcie->offset.mem = res.start - range.pci_addr;
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if (res.flags & IORESOURCE_PREFETCH) {
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memcpy(&pcie->prefetch, &res, sizeof(res));
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pcie->prefetch.name = "prefetchable";
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} else {
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memcpy(&pcie->mem, &res, sizeof(res));
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pcie->mem.name = "non-prefetchable";
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}
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break;
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}
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}
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err = of_pci_parse_bus_range(np, &pcie->busn);
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if (err < 0) {
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dev_err(dev, "failed to parse ranges property: %d\n", err);
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pcie->busn.name = np->name;
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pcie->busn.start = 0;
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pcie->busn.end = 0xff;
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pcie->busn.flags = IORESOURCE_BUS;
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}
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/* parse root ports */
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for_each_child_of_node(np, port) {
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struct tegra_pcie_port *rp;
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@ -2766,6 +2671,7 @@ static int tegra_pcie_probe(struct platform_device *pdev)
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struct pci_host_bridge *host;
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struct tegra_pcie *pcie;
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struct pci_bus *child;
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struct resource *bus;
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int err;
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host = devm_pci_alloc_host_bridge(dev, sizeof(*pcie));
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@ -2780,6 +2686,12 @@ static int tegra_pcie_probe(struct platform_device *pdev)
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INIT_LIST_HEAD(&pcie->ports);
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pcie->dev = dev;
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err = pci_parse_request_of_pci_ranges(dev, &host->windows, NULL, &bus);
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if (err) {
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dev_err(dev, "Getting bridge resources failed\n");
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return err;
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}
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err = tegra_pcie_parse_dt(pcie);
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if (err < 0)
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return err;
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@ -2803,11 +2715,7 @@ static int tegra_pcie_probe(struct platform_device *pdev)
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goto teardown_msi;
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}
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err = tegra_pcie_request_resources(pcie);
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if (err)
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goto pm_runtime_put;
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host->busnr = pcie->busn.start;
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host->busnr = bus->start;
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host->dev.parent = &pdev->dev;
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host->ops = &tegra_pcie_ops;
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host->map_irq = tegra_pcie_map_irq;
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@ -2816,7 +2724,7 @@ static int tegra_pcie_probe(struct platform_device *pdev)
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err = pci_scan_root_bus_bridge(host);
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if (err < 0) {
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dev_err(dev, "failed to register host: %d\n", err);
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goto free_resources;
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goto pm_runtime_put;
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}
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pci_bus_size_bridges(host->bus);
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@ -2835,8 +2743,6 @@ static int tegra_pcie_probe(struct platform_device *pdev)
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return 0;
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free_resources:
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tegra_pcie_free_resources(pcie);
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pm_runtime_put:
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pm_runtime_put_sync(pcie->dev);
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pm_runtime_disable(pcie->dev);
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@ -2858,7 +2764,6 @@ static int tegra_pcie_remove(struct platform_device *pdev)
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pci_stop_root_bus(host->bus);
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pci_remove_root_bus(host->bus);
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tegra_pcie_free_resources(pcie);
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pm_runtime_put_sync(pcie->dev);
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pm_runtime_disable(pcie->dev);
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