mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-13 23:47:04 +07:00
mmc: meson-gx: remove Rx phase tuning
This remove all the code related to phase settings. Using the Rx phase for tuning has not been reliable. We had several issues over the past months, on both v2 and v3 mmc chips After discussing the issue matter with Amlogic, They suggested to set a phase shift of 180 between Core and Tx and use signal resampling for the tuning. Since we won't be playing with the phase anymore, let's remove all the clock code related to it and set the appropriate value on init. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Tested-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
This commit is contained in:
Jerome Brunet
Ulf Hansson
parent
dc38ac8141
commit
5e6f75f423
@ -49,6 +49,8 @@
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#define CLK_CORE_PHASE_MASK GENMASK(9, 8)
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#define CLK_TX_PHASE_MASK GENMASK(11, 10)
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#define CLK_RX_PHASE_MASK GENMASK(13, 12)
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#define CLK_PHASE_0 0
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#define CLK_PHASE_180 2
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#define CLK_V2_TX_DELAY_MASK GENMASK(19, 16)
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#define CLK_V2_RX_DELAY_MASK GENMASK(23, 20)
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#define CLK_V2_ALWAYS_ON BIT(24)
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@ -57,10 +59,6 @@
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#define CLK_V3_RX_DELAY_MASK GENMASK(27, 22)
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#define CLK_V3_ALWAYS_ON BIT(28)
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#define CLK_DELAY_STEP_PS 200
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#define CLK_PHASE_STEP 30
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#define CLK_PHASE_POINT_NUM (360 / CLK_PHASE_STEP)
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#define CLK_TX_DELAY_MASK(h) (h->data->tx_delay_mask)
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#define CLK_RX_DELAY_MASK(h) (h->data->rx_delay_mask)
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#define CLK_ALWAYS_ON(h) (h->data->always_on)
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@ -165,9 +163,8 @@ struct meson_host {
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void __iomem *regs;
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struct clk *core_clk;
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struct clk *mux_clk;
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struct clk *mmc_clk;
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struct clk *rx_clk;
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struct clk *tx_clk;
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unsigned long req_rate;
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bool ddr;
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@ -209,90 +206,6 @@ struct meson_host {
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#define CMD_RESP_MASK GENMASK(31, 1)
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#define CMD_RESP_SRAM BIT(0)
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struct meson_mmc_phase {
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struct clk_hw hw;
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void __iomem *reg;
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unsigned long phase_mask;
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unsigned long delay_mask;
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unsigned int delay_step_ps;
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};
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#define to_meson_mmc_phase(_hw) container_of(_hw, struct meson_mmc_phase, hw)
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static int meson_mmc_clk_get_phase(struct clk_hw *hw)
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{
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struct meson_mmc_phase *mmc = to_meson_mmc_phase(hw);
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unsigned int phase_num = 1 << hweight_long(mmc->phase_mask);
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unsigned long period_ps, p, d;
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int degrees;
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u32 val;
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val = readl(mmc->reg);
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p = (val & mmc->phase_mask) >> __ffs(mmc->phase_mask);
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degrees = p * 360 / phase_num;
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if (mmc->delay_mask) {
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period_ps = DIV_ROUND_UP((unsigned long)NSEC_PER_SEC * 1000,
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clk_get_rate(hw->clk));
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d = (val & mmc->delay_mask) >> __ffs(mmc->delay_mask);
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degrees += d * mmc->delay_step_ps * 360 / period_ps;
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degrees %= 360;
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}
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return degrees;
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}
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static void meson_mmc_apply_phase_delay(struct meson_mmc_phase *mmc,
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unsigned int phase,
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unsigned int delay)
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{
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u32 val;
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val = readl(mmc->reg);
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val &= ~mmc->phase_mask;
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val |= phase << __ffs(mmc->phase_mask);
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if (mmc->delay_mask) {
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val &= ~mmc->delay_mask;
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val |= delay << __ffs(mmc->delay_mask);
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}
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writel(val, mmc->reg);
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}
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static int meson_mmc_clk_set_phase(struct clk_hw *hw, int degrees)
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{
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struct meson_mmc_phase *mmc = to_meson_mmc_phase(hw);
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unsigned int phase_num = 1 << hweight_long(mmc->phase_mask);
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unsigned long period_ps, d = 0, r;
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uint64_t p;
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p = degrees % 360;
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if (!mmc->delay_mask) {
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p = DIV_ROUND_CLOSEST_ULL(p, 360 / phase_num);
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} else {
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period_ps = DIV_ROUND_UP((unsigned long)NSEC_PER_SEC * 1000,
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clk_get_rate(hw->clk));
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/* First compute the phase index (p), the remainder (r) is the
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* part we'll try to acheive using the delays (d).
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*/
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r = do_div(p, 360 / phase_num);
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d = DIV_ROUND_CLOSEST(r * period_ps,
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360 * mmc->delay_step_ps);
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d = min(d, mmc->delay_mask >> __ffs(mmc->delay_mask));
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}
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meson_mmc_apply_phase_delay(mmc, p, d);
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return 0;
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}
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static const struct clk_ops meson_mmc_clk_phase_ops = {
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.get_phase = meson_mmc_clk_get_phase,
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.set_phase = meson_mmc_clk_set_phase,
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};
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static unsigned int meson_mmc_get_timeout_msecs(struct mmc_data *data)
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{
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unsigned int timeout = data->timeout_ns / NSEC_PER_MSEC;
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@ -492,8 +405,6 @@ static int meson_mmc_clk_init(struct meson_host *host)
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struct clk_init_data init;
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struct clk_mux *mux;
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struct clk_divider *div;
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struct meson_mmc_phase *core, *tx, *rx;
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struct clk *clk;
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char clk_name[32];
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int i, ret = 0;
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const char *mux_parent_names[MUX_CLK_NUM_PARENTS];
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@ -501,9 +412,11 @@ static int meson_mmc_clk_init(struct meson_host *host)
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u32 clk_reg;
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/* init SD_EMMC_CLOCK to sane defaults w/min clock rate */
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clk_reg = 0;
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clk_reg |= CLK_ALWAYS_ON(host);
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clk_reg = CLK_ALWAYS_ON(host);
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clk_reg |= CLK_DIV_MASK;
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clk_reg |= FIELD_PREP(CLK_CORE_PHASE_MASK, CLK_PHASE_180);
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clk_reg |= FIELD_PREP(CLK_TX_PHASE_MASK, CLK_PHASE_0);
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clk_reg |= FIELD_PREP(CLK_RX_PHASE_MASK, CLK_PHASE_0);
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writel(clk_reg, host->regs + SD_EMMC_CLOCK);
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/* get the mux parents */
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@ -539,9 +452,9 @@ static int meson_mmc_clk_init(struct meson_host *host)
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mux->mask = CLK_SRC_MASK >> mux->shift;
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mux->hw.init = &init;
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clk = devm_clk_register(host->dev, &mux->hw);
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if (WARN_ON(IS_ERR(clk)))
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return PTR_ERR(clk);
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host->mux_clk = devm_clk_register(host->dev, &mux->hw);
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if (WARN_ON(IS_ERR(host->mux_clk)))
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return PTR_ERR(host->mux_clk);
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/* create the divider */
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div = devm_kzalloc(host->dev, sizeof(*div), GFP_KERNEL);
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@ -552,7 +465,7 @@ static int meson_mmc_clk_init(struct meson_host *host)
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init.name = clk_name;
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init.ops = &clk_divider_ops;
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init.flags = CLK_SET_RATE_PARENT;
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clk_parent[0] = __clk_get_name(clk);
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clk_parent[0] = __clk_get_name(host->mux_clk);
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init.parent_names = clk_parent;
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init.num_parents = 1;
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@ -562,192 +475,19 @@ static int meson_mmc_clk_init(struct meson_host *host)
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div->hw.init = &init;
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div->flags = CLK_DIVIDER_ONE_BASED;
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clk = devm_clk_register(host->dev, &div->hw);
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if (WARN_ON(IS_ERR(clk)))
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return PTR_ERR(clk);
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/* create the mmc core clock */
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core = devm_kzalloc(host->dev, sizeof(*core), GFP_KERNEL);
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if (!core)
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return -ENOMEM;
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snprintf(clk_name, sizeof(clk_name), "%s#core", dev_name(host->dev));
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init.name = clk_name;
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init.ops = &meson_mmc_clk_phase_ops;
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init.flags = CLK_SET_RATE_PARENT;
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clk_parent[0] = __clk_get_name(clk);
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init.parent_names = clk_parent;
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init.num_parents = 1;
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core->reg = host->regs + SD_EMMC_CLOCK;
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core->phase_mask = CLK_CORE_PHASE_MASK;
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core->hw.init = &init;
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host->mmc_clk = devm_clk_register(host->dev, &core->hw);
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if (WARN_ON(PTR_ERR_OR_ZERO(host->mmc_clk)))
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host->mmc_clk = devm_clk_register(host->dev, &div->hw);
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if (WARN_ON(IS_ERR(host->mmc_clk)))
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return PTR_ERR(host->mmc_clk);
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/* create the mmc tx clock */
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tx = devm_kzalloc(host->dev, sizeof(*tx), GFP_KERNEL);
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if (!tx)
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return -ENOMEM;
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snprintf(clk_name, sizeof(clk_name), "%s#tx", dev_name(host->dev));
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init.name = clk_name;
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init.ops = &meson_mmc_clk_phase_ops;
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init.flags = 0;
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clk_parent[0] = __clk_get_name(host->mmc_clk);
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init.parent_names = clk_parent;
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init.num_parents = 1;
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tx->reg = host->regs + SD_EMMC_CLOCK;
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tx->phase_mask = CLK_TX_PHASE_MASK;
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tx->delay_mask = CLK_TX_DELAY_MASK(host);
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tx->delay_step_ps = CLK_DELAY_STEP_PS;
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tx->hw.init = &init;
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host->tx_clk = devm_clk_register(host->dev, &tx->hw);
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if (WARN_ON(PTR_ERR_OR_ZERO(host->tx_clk)))
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return PTR_ERR(host->tx_clk);
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/* create the mmc rx clock */
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rx = devm_kzalloc(host->dev, sizeof(*rx), GFP_KERNEL);
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if (!rx)
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return -ENOMEM;
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snprintf(clk_name, sizeof(clk_name), "%s#rx", dev_name(host->dev));
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init.name = clk_name;
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init.ops = &meson_mmc_clk_phase_ops;
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init.flags = 0;
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clk_parent[0] = __clk_get_name(host->mmc_clk);
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init.parent_names = clk_parent;
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init.num_parents = 1;
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rx->reg = host->regs + SD_EMMC_CLOCK;
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rx->phase_mask = CLK_RX_PHASE_MASK;
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rx->delay_mask = CLK_RX_DELAY_MASK(host);
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rx->delay_step_ps = CLK_DELAY_STEP_PS;
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rx->hw.init = &init;
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host->rx_clk = devm_clk_register(host->dev, &rx->hw);
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if (WARN_ON(PTR_ERR_OR_ZERO(host->rx_clk)))
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return PTR_ERR(host->rx_clk);
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/* init SD_EMMC_CLOCK to sane defaults w/min clock rate */
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host->mmc->f_min = clk_round_rate(host->mmc_clk, 400000);
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ret = clk_set_rate(host->mmc_clk, host->mmc->f_min);
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if (ret)
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return ret;
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clk_set_phase(host->mmc_clk, 180);
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clk_set_phase(host->tx_clk, 0);
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clk_set_phase(host->rx_clk, 0);
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return clk_prepare_enable(host->mmc_clk);
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}
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static void meson_mmc_shift_map(unsigned long *map, unsigned long shift)
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{
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DECLARE_BITMAP(left, CLK_PHASE_POINT_NUM);
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DECLARE_BITMAP(right, CLK_PHASE_POINT_NUM);
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/*
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* shift the bitmap right and reintroduce the dropped bits on the left
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* of the bitmap
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*/
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bitmap_shift_right(right, map, shift, CLK_PHASE_POINT_NUM);
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bitmap_shift_left(left, map, CLK_PHASE_POINT_NUM - shift,
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CLK_PHASE_POINT_NUM);
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bitmap_or(map, left, right, CLK_PHASE_POINT_NUM);
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}
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static void meson_mmc_find_next_region(unsigned long *map,
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unsigned long *start,
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unsigned long *stop)
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{
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*start = find_next_bit(map, CLK_PHASE_POINT_NUM, *start);
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*stop = find_next_zero_bit(map, CLK_PHASE_POINT_NUM, *start);
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}
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static int meson_mmc_find_tuning_point(unsigned long *test)
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{
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unsigned long shift, stop, offset = 0, start = 0, size = 0;
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/* Get the all good/all bad situation out the way */
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if (bitmap_full(test, CLK_PHASE_POINT_NUM))
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return 0; /* All points are good so point 0 will do */
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else if (bitmap_empty(test, CLK_PHASE_POINT_NUM))
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return -EIO; /* No successful tuning point */
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/*
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* Now we know there is a least one region find. Make sure it does
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* not wrap by the shifting the bitmap if necessary
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*/
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shift = find_first_zero_bit(test, CLK_PHASE_POINT_NUM);
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if (shift != 0)
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meson_mmc_shift_map(test, shift);
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while (start < CLK_PHASE_POINT_NUM) {
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meson_mmc_find_next_region(test, &start, &stop);
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if ((stop - start) > size) {
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offset = start;
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size = stop - start;
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}
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start = stop;
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}
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/* Get the center point of the region */
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offset += (size / 2);
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/* Shift the result back */
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offset = (offset + shift) % CLK_PHASE_POINT_NUM;
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return offset;
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}
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static int meson_mmc_clk_phase_tuning(struct mmc_host *mmc, u32 opcode,
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struct clk *clk)
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{
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int point, ret;
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DECLARE_BITMAP(test, CLK_PHASE_POINT_NUM);
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dev_dbg(mmc_dev(mmc), "%s phase/delay tunning...\n",
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__clk_get_name(clk));
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bitmap_zero(test, CLK_PHASE_POINT_NUM);
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/* Explore tuning points */
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for (point = 0; point < CLK_PHASE_POINT_NUM; point++) {
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clk_set_phase(clk, point * CLK_PHASE_STEP);
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ret = mmc_send_tuning(mmc, opcode, NULL);
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if (!ret)
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set_bit(point, test);
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}
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/* Find the optimal tuning point and apply it */
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point = meson_mmc_find_tuning_point(test);
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if (point < 0)
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return point; /* tuning failed */
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clk_set_phase(clk, point * CLK_PHASE_STEP);
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dev_dbg(mmc_dev(mmc), "success with phase: %d\n",
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clk_get_phase(clk));
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return 0;
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}
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static int meson_mmc_execute_tuning(struct mmc_host *mmc, u32 opcode)
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{
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struct meson_host *host = mmc_priv(mmc);
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int adj = 0;
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/* enable signal resampling w/o delay */
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adj = ADJUST_ADJ_EN;
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writel(adj, host->regs + host->data->adjust);
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return meson_mmc_clk_phase_tuning(mmc, opcode, host->rx_clk);
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}
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static int meson_mmc_prepare_ios_clock(struct meson_host *host,
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struct mmc_ios *ios)
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{
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@ -796,9 +536,6 @@ static void meson_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
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/* disable signal resampling */
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writel(0, host->regs + host->data->adjust);
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/* Reset rx phase */
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clk_set_phase(host->rx_clk, 0);
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break;
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case MMC_POWER_ON:
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@ -1226,7 +963,6 @@ static const struct mmc_host_ops meson_mmc_ops = {
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.get_cd = meson_mmc_get_cd,
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.pre_req = meson_mmc_pre_req,
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.post_req = meson_mmc_post_req,
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.execute_tuning = meson_mmc_execute_tuning,
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.card_busy = meson_mmc_card_busy,
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.start_signal_voltage_switch = meson_mmc_voltage_switch,
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};
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