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drm/nouveau/clock: fix missing pll type/addr when matching default entry

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This issue is a regression from 70790f4f81,
and causes us to miss a special-case for C51 (NV4E) chipsets and return
the wrong reference frequency for the VPLLs.

Should fix fdo#56202

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Ben Skeggs 2012-10-22 14:10:16 +10:00
parent 2c25b73995
commit 5e5a195ecc
1 changed files with 4 additions and 6 deletions
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10
drivers/gpu/drm/nouveau/core/subdev/bios/pll.c
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@ -157,11 +157,10 @@ pll_map_reg(struct nouveau_bios *bios, u32 reg, u32 *type, u8 *ver, u8 *len)
while (map->reg) {
if (map->reg == reg && *ver >= 0x20) {
u16 addr = (data += hdr);
*type = map->type;
while (cnt--) {
if (nv_ro32(bios, data) == map->reg) {
*type = map->type;
if (nv_ro32(bios, data) == map->reg)
return data;
}
data += *len;
}
return addr;
@ -200,11 +199,10 @@ pll_map_type(struct nouveau_bios *bios, u8 type, u32 *reg, u8 *ver, u8 *len)
while (map->reg) {
if (map->type == type && *ver >= 0x20) {
u16 addr = (data += hdr);
*reg = map->reg;
while (cnt--) {
if (nv_ro32(bios, data) == map->reg) {
*reg = map->reg;
if (nv_ro32(bios, data) == map->reg)
return data;
}
data += *len;
}
return addr;