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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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drm/amd/pp: Implement edit_dpm_table on smu7
v2: - check clk against OverDrive limits from VBIOS
- set OD flag when user commit the setting.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Rex Zhu
Alex Deucher
parent
b7e919b940
commit
5e4d4fbea5
@ -4808,6 +4808,169 @@ static int smu7_get_thermal_temperature_range(struct pp_hwmgr *hwmgr,
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return 0;
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}
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static bool smu7_check_clk_voltage_valid(struct pp_hwmgr *hwmgr,
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enum PP_OD_DPM_TABLE_COMMAND type,
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uint32_t clk,
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uint32_t voltage)
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{
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struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
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struct phm_ppt_v1_information *table_info =
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(struct phm_ppt_v1_information *)(hwmgr->pptable);
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uint32_t min_vddc;
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struct phm_ppt_v1_clock_voltage_dependency_table *dep_sclk_table;
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if (table_info == NULL)
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return -EINVAL;
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dep_sclk_table = table_info->vdd_dep_on_sclk;
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min_vddc = dep_sclk_table->entries[0].vddc;
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if (voltage < min_vddc || voltage > 2000) {
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pr_info("OD voltage is out of range [%d - 2000] mV\n", min_vddc);
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return false;
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}
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if (type == PP_OD_EDIT_SCLK_VDDC_TABLE) {
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if (data->vbios_boot_state.sclk_bootup_value > clk ||
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hwmgr->platform_descriptor.overdriveLimit.engineClock < clk) {
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pr_info("OD engine clock is out of range [%d - %d] MHz\n",
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data->vbios_boot_state.sclk_bootup_value,
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hwmgr->platform_descriptor.overdriveLimit.engineClock / 100);
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return false;
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}
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} else if (type == PP_OD_EDIT_MCLK_VDDC_TABLE) {
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if (data->vbios_boot_state.mclk_bootup_value > clk ||
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hwmgr->platform_descriptor.overdriveLimit.memoryClock < clk) {
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pr_info("OD memory clock is out of range [%d - %d] MHz\n",
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data->vbios_boot_state.mclk_bootup_value/100,
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hwmgr->platform_descriptor.overdriveLimit.memoryClock / 100);
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return false;
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}
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} else {
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return false;
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}
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return true;
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}
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static void smu7_check_dpm_table_updated(struct pp_hwmgr *hwmgr)
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{
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struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
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struct smu7_odn_dpm_table *odn_table = &(data->odn_dpm_table);
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struct phm_ppt_v1_information *table_info =
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(struct phm_ppt_v1_information *)(hwmgr->pptable);
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uint32_t i;
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struct phm_ppt_v1_clock_voltage_dependency_table *dep_table;
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struct phm_ppt_v1_clock_voltage_dependency_table *odn_dep_table;
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if (table_info == NULL)
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return;
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for (i=0; i<data->dpm_table.sclk_table.count; i++) {
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if (odn_table->odn_core_clock_dpm_levels.entries[i].clock !=
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data->dpm_table.sclk_table.dpm_levels[i].value) {
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data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK;
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break;
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}
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}
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for (i=0; i<data->dpm_table.sclk_table.count; i++) {
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if (odn_table->odn_memory_clock_dpm_levels.entries[i].clock !=
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data->dpm_table.mclk_table.dpm_levels[i].value) {
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data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK;
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break;
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}
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}
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dep_table = table_info->vdd_dep_on_mclk;
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odn_dep_table = (struct phm_ppt_v1_clock_voltage_dependency_table *)&(odn_table->vdd_dependency_on_mclk);
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for (i=0; i<dep_table->count; i++) {
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if (dep_table->entries[i].vddc != odn_dep_table->entries[i].vddc) {
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data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_VDDC;
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return;
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}
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}
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dep_table = table_info->vdd_dep_on_sclk;
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odn_dep_table = (struct phm_ppt_v1_clock_voltage_dependency_table *)&(odn_table->vdd_dependency_on_sclk);
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for (i=0; i<dep_table->count; i++) {
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if (dep_table->entries[i].vddc != odn_dep_table->entries[i].vddc) {
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data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_VDDC;
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return;
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}
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}
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}
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static int smu7_odn_edit_dpm_table(struct pp_hwmgr *hwmgr,
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enum PP_OD_DPM_TABLE_COMMAND type,
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long *input, uint32_t size)
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{
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uint32_t i;
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struct phm_odn_clock_levels *podn_dpm_table_in_backend = NULL;
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struct smu7_odn_clock_voltage_dependency_table *podn_vdd_dep_in_backend = NULL;
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struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
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uint32_t input_clk;
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uint32_t input_vol;
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uint32_t input_level;
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PP_ASSERT_WITH_CODE(input, "NULL user input for clock and voltage",
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return -EINVAL);
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if (!hwmgr->od_enabled) {
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pr_info("OverDrive feature not enabled\n");
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return -EINVAL;
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}
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if (PP_OD_EDIT_SCLK_VDDC_TABLE == type) {
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podn_dpm_table_in_backend = &data->odn_dpm_table.odn_core_clock_dpm_levels;
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podn_vdd_dep_in_backend = &data->odn_dpm_table.vdd_dependency_on_sclk;
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PP_ASSERT_WITH_CODE((podn_dpm_table_in_backend && podn_vdd_dep_in_backend),
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"Failed to get ODN SCLK and Voltage tables",
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return -EINVAL);
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} else if (PP_OD_EDIT_MCLK_VDDC_TABLE == type) {
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podn_dpm_table_in_backend = &data->odn_dpm_table.odn_memory_clock_dpm_levels;
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podn_vdd_dep_in_backend = &data->odn_dpm_table.vdd_dependency_on_mclk;
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PP_ASSERT_WITH_CODE((podn_dpm_table_in_backend && podn_vdd_dep_in_backend),
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"Failed to get ODN MCLK and Voltage tables",
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return -EINVAL);
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} else if (PP_OD_RESTORE_DEFAULT_TABLE == type) {
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smu7_odn_initial_default_setting(hwmgr);
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return 0;
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} else if (PP_OD_COMMIT_DPM_TABLE == type) {
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smu7_check_dpm_table_updated(hwmgr);
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return 0;
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} else {
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return -EINVAL;
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}
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for (i = 0; i < size; i += 3) {
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if (i + 3 > size || input[i] >= podn_dpm_table_in_backend->num_of_pl) {
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pr_info("invalid clock voltage input \n");
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return 0;
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}
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input_level = input[i];
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input_clk = input[i+1] * 100;
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input_vol = input[i+2];
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if (smu7_check_clk_voltage_valid(hwmgr, type, input_clk, input_vol)) {
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podn_dpm_table_in_backend->entries[input_level].clock = input_clk;
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podn_vdd_dep_in_backend->entries[input_level].clk = input_clk;
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podn_dpm_table_in_backend->entries[input_level].vddc = input_vol;
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podn_vdd_dep_in_backend->entries[input_level].vddc = input_vol;
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} else {
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return -EINVAL;
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}
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}
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return 0;
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}
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static const struct pp_hwmgr_func smu7_hwmgr_funcs = {
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.backend_init = &smu7_hwmgr_backend_init,
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.backend_fini = &smu7_hwmgr_backend_fini,
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@ -4862,6 +5025,7 @@ static const struct pp_hwmgr_func smu7_hwmgr_funcs = {
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.notify_cac_buffer_info = smu7_notify_cac_buffer_info,
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.get_max_high_clocks = smu7_get_max_high_clocks,
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.get_thermal_temperature_range = smu7_get_thermal_temperature_range,
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.odn_edit_dpm_table = smu7_odn_edit_dpm_table,
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};
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uint8_t smu7_get_sleep_divider_id_from_clock(uint32_t clock,
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@ -4893,4 +5057,3 @@ int smu7_init_function_pointers(struct pp_hwmgr *hwmgr)
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return ret;
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}
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