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ARM: dts: qcom: Add nodes for SMP boot in IPQ40xx

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Add missing nodes and properties to enable SMP
support on IPQ40xx devices.

Booting without "saw_l2" node:

[    0.001400] CPU: Testing write buffer coherency: ok
[    0.001856] CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
[    0.060163] Setting up static identity map for 0x80300000 - 0x80300060
[    0.080140] rcu: Hierarchical SRCU implementation.
[    0.120258] smp: Bringing up secondary CPUs ...
[    0.200540] CPU1: failed to boot: -19
[    0.280689] CPU2: failed to boot: -19
[    0.360874] CPU3: failed to boot: -19
[    0.360966] smp: Brought up 1 node, 1 CPU
[    0.360979] SMP: Total of 1 processors activated (96.00 BogoMIPS).
[    0.360988] CPU: All CPU(s) started in SVC mode.

Then, booting with "saw_l2" node present (this patch applied):

[    0.001450] CPU: Testing write buffer coherency: ok
[    0.001904] CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
[    0.060161] Setting up static identity map for 0x80300000 - 0x80300060
[    0.080137] rcu: Hierarchical SRCU implementation.
[    0.120252] smp: Bringing up secondary CPUs ...
[    0.200958] CPU1: thread -1, cpu 1, socket 0, mpidr 80000001
[    0.281091] CPU2: thread -1, cpu 2, socket 0, mpidr 80000002
[    0.361264] CPU3: thread -1, cpu 3, socket 0, mpidr 80000003
[    0.361430] smp: Brought up 1 node, 4 CPUs
[    0.361460] SMP: Total of 4 processors activated (384.00 BogoMIPS).
[    0.361469] CPU: All CPU(s) started in SVC mode.

Signed-off-by: Damir Franusic <damir.franusic@sartura.hr>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Cc: Robert Marko <robert.marko@sartura.hr>
Cc: Andy Gross <agross@kernel.org>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: linux-arm-msm@vger.kernel.org
Link: https://lore.kernel.org/r/20191121152902.21394-1-damir.franusic@gmail.com
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
This commit is contained in:
Damir Franusic 2019-11-21 16:29:02 +01:00 committed by Bjorn Andersson
parent ced44b9da5
commit 5e45489220
1 changed files with 7 additions and 0 deletions
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7
arch/arm/boot/dts/qcom-ipq4019.dtsi
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@ -102,6 +102,7 @@ cpu@3 {
L2: l2-cache {
compatible = "cache";
cache-level = <2>;
qcom,saw = <&saw_l2>;
};
};
@ -353,6 +354,12 @@ saw3: regulator@b0b9000 {
regulator;
};
saw_l2: regulator@b012000 {
compatible = "qcom,saw2";
reg = <0xb012000 0x1000>;
regulator;
};
blsp1_uart1: serial@78af000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0x78af000 0x200>;