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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-11-24 12:20:52 +07:00
omap1: Fix gpio mpuio bank to work for multi-omap for 7xx/15xx/16xx
We need to divide the 15xx/16xx offset by 2 for 7xx. Use bank->stride for that. This allows us to get rid of the duplicate defines for the MPUIO registers. Note that this will cause omap-keypad.c driver to not work on 7xx. However, the right fix there is to move over to matrix_keypad instead as suggested by Cory Maccarrone <darkstar6262@gmail.com> and Janusz Krzysztofik <jkrzyszt@tis.icnet.pl>. Cc: Cory Maccarrone <darkstar6262@gmail.com> Acked-by: Janusz Krzysztofik <jkrzyszt@tis.icnet.pl> Signed-off-by: Tony Lindgren <tony@atomide.com>
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77640aabd7
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@ -38,6 +38,7 @@ static struct __initdata omap_gpio_platform_data omap15xx_mpu_gpio_config = {
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.virtual_irq_start = IH_MPUIO_BASE,
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.bank_type = METHOD_MPUIO,
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.bank_width = 16,
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.bank_stride = 1,
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};
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static struct __initdata platform_device omap15xx_mpu_gpio = {
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@ -41,6 +41,7 @@ static struct __initdata omap_gpio_platform_data omap16xx_mpu_gpio_config = {
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.virtual_irq_start = IH_MPUIO_BASE,
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.bank_type = METHOD_MPUIO,
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.bank_width = 16,
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.bank_stride = 1,
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};
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static struct __initdata platform_device omap16xx_mpu_gpio = {
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@ -43,6 +43,7 @@ static struct __initdata omap_gpio_platform_data omap7xx_mpu_gpio_config = {
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.virtual_irq_start = IH_MPUIO_BASE,
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.bank_type = METHOD_MPUIO,
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.bank_width = 32,
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.bank_stride = 2,
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};
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static struct __initdata platform_device omap7xx_mpu_gpio = {
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@ -159,6 +159,7 @@ struct gpio_bank {
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u32 dbck_enable_mask;
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struct device *dev;
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bool dbck_flag;
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int stride;
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};
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#ifdef CONFIG_ARCH_OMAP3
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@ -267,7 +268,7 @@ static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
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switch (bank->method) {
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#ifdef CONFIG_ARCH_OMAP1
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case METHOD_MPUIO:
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reg += OMAP_MPUIO_IO_CNTL;
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reg += OMAP_MPUIO_IO_CNTL / bank->stride;
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break;
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#endif
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#ifdef CONFIG_ARCH_OMAP15XX
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@ -315,7 +316,7 @@ static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
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switch (bank->method) {
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#ifdef CONFIG_ARCH_OMAP1
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case METHOD_MPUIO:
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reg += OMAP_MPUIO_OUTPUT;
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reg += OMAP_MPUIO_OUTPUT / bank->stride;
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l = __raw_readl(reg);
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if (enable)
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l |= 1 << gpio;
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@ -387,7 +388,7 @@ static int _get_gpio_datain(struct gpio_bank *bank, int gpio)
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switch (bank->method) {
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#ifdef CONFIG_ARCH_OMAP1
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case METHOD_MPUIO:
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reg += OMAP_MPUIO_INPUT_LATCH;
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reg += OMAP_MPUIO_INPUT_LATCH / bank->stride;
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break;
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#endif
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#ifdef CONFIG_ARCH_OMAP15XX
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@ -433,7 +434,7 @@ static int _get_gpio_dataout(struct gpio_bank *bank, int gpio)
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switch (bank->method) {
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#ifdef CONFIG_ARCH_OMAP1
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case METHOD_MPUIO:
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reg += OMAP_MPUIO_OUTPUT;
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reg += OMAP_MPUIO_OUTPUT / bank->stride;
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break;
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#endif
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#ifdef CONFIG_ARCH_OMAP15XX
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@ -620,7 +621,7 @@ static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio)
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switch (bank->method) {
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case METHOD_MPUIO:
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reg += OMAP_MPUIO_GPIO_INT_EDGE;
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reg += OMAP_MPUIO_GPIO_INT_EDGE / bank->stride;
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break;
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#ifdef CONFIG_ARCH_OMAP15XX
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case METHOD_GPIO_1510:
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@ -654,7 +655,7 @@ static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
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switch (bank->method) {
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#ifdef CONFIG_ARCH_OMAP1
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case METHOD_MPUIO:
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reg += OMAP_MPUIO_GPIO_INT_EDGE;
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reg += OMAP_MPUIO_GPIO_INT_EDGE / bank->stride;
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l = __raw_readl(reg);
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if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
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bank->toggle_mask |= 1 << gpio;
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@ -840,7 +841,7 @@ static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
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switch (bank->method) {
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#ifdef CONFIG_ARCH_OMAP1
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case METHOD_MPUIO:
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reg += OMAP_MPUIO_GPIO_MASKIT;
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reg += OMAP_MPUIO_GPIO_MASKIT / bank->stride;
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mask = 0xffff;
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inv = 1;
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break;
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@ -897,7 +898,7 @@ static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enab
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switch (bank->method) {
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#ifdef CONFIG_ARCH_OMAP1
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case METHOD_MPUIO:
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reg += OMAP_MPUIO_GPIO_MASKIT;
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reg += OMAP_MPUIO_GPIO_MASKIT / bank->stride;
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l = __raw_readl(reg);
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if (enable)
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l &= ~(gpio_mask);
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@ -1147,7 +1148,8 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
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bank = get_irq_data(irq);
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#ifdef CONFIG_ARCH_OMAP1
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if (bank->method == METHOD_MPUIO)
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isr_reg = bank->base + OMAP_MPUIO_GPIO_INT;
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isr_reg = bank->base +
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OMAP_MPUIO_GPIO_INT / bank->stride;
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#endif
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#ifdef CONFIG_ARCH_OMAP15XX
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if (bank->method == METHOD_GPIO_1510)
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@ -1345,7 +1347,8 @@ static int omap_mpuio_suspend_noirq(struct device *dev)
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{
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struct platform_device *pdev = to_platform_device(dev);
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struct gpio_bank *bank = platform_get_drvdata(pdev);
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void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT;
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void __iomem *mask_reg = bank->base +
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OMAP_MPUIO_GPIO_MASKIT / bank->stride;
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unsigned long flags;
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spin_lock_irqsave(&bank->lock, flags);
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@ -1360,7 +1363,8 @@ static int omap_mpuio_resume_noirq(struct device *dev)
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{
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struct platform_device *pdev = to_platform_device(dev);
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struct gpio_bank *bank = platform_get_drvdata(pdev);
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void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT;
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void __iomem *mask_reg = bank->base +
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OMAP_MPUIO_GPIO_MASKIT / bank->stride;
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unsigned long flags;
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spin_lock_irqsave(&bank->lock, flags);
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@ -1440,7 +1444,7 @@ static int gpio_is_input(struct gpio_bank *bank, int mask)
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switch (bank->method) {
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case METHOD_MPUIO:
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reg += OMAP_MPUIO_IO_CNTL;
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reg += OMAP_MPUIO_IO_CNTL / bank->stride;
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break;
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case METHOD_GPIO_1510:
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reg += OMAP1510_GPIO_DIR_CONTROL;
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@ -1601,8 +1605,8 @@ static void omap_gpio_mod_init(struct gpio_bank *bank, int id)
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}
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} else if (cpu_class_is_omap1()) {
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if (bank_is_mpuio(bank))
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__raw_writew(0xffff, bank->base
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+ OMAP_MPUIO_GPIO_MASKIT);
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__raw_writew(0xffff, bank->base +
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OMAP_MPUIO_GPIO_MASKIT / bank->stride);
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if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) {
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__raw_writew(0xffff, bank->base
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+ OMAP1510_GPIO_INT_MASK);
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@ -1716,6 +1720,7 @@ static int __devinit omap_gpio_probe(struct platform_device *pdev)
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bank->method = pdata->bank_type;
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bank->dev = &pdev->dev;
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bank->dbck_flag = pdata->dbck_flag;
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bank->stride = pdata->bank_stride;
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bank_width = pdata->bank_width;
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spin_lock_init(&bank->lock);
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@ -32,22 +32,10 @@
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#define OMAP1_MPUIO_BASE 0xfffb5000
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#if (defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850))
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#define OMAP_MPUIO_INPUT_LATCH 0x00
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#define OMAP_MPUIO_OUTPUT 0x02
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#define OMAP_MPUIO_IO_CNTL 0x04
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#define OMAP_MPUIO_KBR_LATCH 0x08
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#define OMAP_MPUIO_KBC 0x0a
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#define OMAP_MPUIO_GPIO_EVENT_MODE 0x0c
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#define OMAP_MPUIO_GPIO_INT_EDGE 0x0e
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#define OMAP_MPUIO_KBD_INT 0x10
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#define OMAP_MPUIO_GPIO_INT 0x12
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#define OMAP_MPUIO_KBD_MASKIT 0x14
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#define OMAP_MPUIO_GPIO_MASKIT 0x16
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#define OMAP_MPUIO_GPIO_DEBOUNCING 0x18
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#define OMAP_MPUIO_LATCH 0x1a
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#else
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/*
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* These are the omap15xx/16xx offsets. The omap7xx offset are
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* OMAP_MPUIO_ / 2 offsets below.
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*/
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#define OMAP_MPUIO_INPUT_LATCH 0x00
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#define OMAP_MPUIO_OUTPUT 0x04
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#define OMAP_MPUIO_IO_CNTL 0x08
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@ -61,7 +49,6 @@
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#define OMAP_MPUIO_GPIO_MASKIT 0x2c
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#define OMAP_MPUIO_GPIO_DEBOUNCING 0x30
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#define OMAP_MPUIO_LATCH 0x34
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#endif
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#define OMAP34XX_NR_GPIOS 6
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@ -88,6 +75,7 @@ struct omap_gpio_platform_data {
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u16 virtual_irq_start;
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int bank_type;
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int bank_width; /* GPIO bank width */
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int bank_stride; /* Only needed for omap1 MPUIO */
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bool dbck_flag; /* dbck required or not - True for OMAP3&4 */
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};
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