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mtd: atmel_nand: Support variable RB_EDGE interrupts
The NFC controller used to accelerate the NAND transfers on SAMA5 chips can use either RB_EDGE0 or RB_EDGE3 as its ready/busy interrupt bit. Use the controller's compatible string to select the correct bit. For the binding: Acked-by: Rob Herring <robh@kernel.org> Reviewed-by: Wenyou Yang <Wenyou.yang@atmel.com> Tested-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Romain Izard <romain.izard.pro@gmail.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
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@ -34,7 +34,7 @@ Optional properties:
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- nand-on-flash-bbt: boolean to enable on flash bbt option if not present false
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- Nand Flash Controller(NFC) is a slave driver under Atmel nand flash
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- Required properties:
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- compatible : "atmel,sama5d3-nfc".
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- compatible : "atmel,sama5d3-nfc" or "atmel,sama5d4-nfc".
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- reg : should specify the address and size used for NFC command registers,
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NFC registers and NFC Sram. NFC Sram address and size can be absent
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if don't want to use it.
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@ -67,6 +67,10 @@ struct atmel_nand_caps {
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bool pmecc_correct_erase_page;
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};
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struct atmel_nand_nfc_caps {
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uint32_t rb_mask;
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};
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/* oob layout for large page size
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* bad block info is on bytes 0 and 1
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* the bytes have to be consecutives to avoid
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@ -111,6 +115,7 @@ struct atmel_nfc {
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/* Point to the sram bank which include readed data via NFC */
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void *data_in_sram;
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bool will_write_sram;
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const struct atmel_nand_nfc_caps *caps;
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};
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static struct atmel_nfc nand_nfc;
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@ -1675,9 +1680,9 @@ static irqreturn_t hsmc_interrupt(int irq, void *dev_id)
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nfc_writel(host->nfc->hsmc_regs, IDR, NFC_SR_XFR_DONE);
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ret = IRQ_HANDLED;
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}
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if (pending & NFC_SR_RB_EDGE) {
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if (pending & host->nfc->caps->rb_mask) {
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complete(&host->nfc->comp_ready);
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nfc_writel(host->nfc->hsmc_regs, IDR, NFC_SR_RB_EDGE);
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nfc_writel(host->nfc->hsmc_regs, IDR, host->nfc->caps->rb_mask);
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ret = IRQ_HANDLED;
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}
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if (pending & NFC_SR_CMD_DONE) {
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@ -1695,7 +1700,7 @@ static void nfc_prepare_interrupt(struct atmel_nand_host *host, u32 flag)
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if (flag & NFC_SR_XFR_DONE)
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init_completion(&host->nfc->comp_xfer_done);
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if (flag & NFC_SR_RB_EDGE)
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if (flag & host->nfc->caps->rb_mask)
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init_completion(&host->nfc->comp_ready);
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if (flag & NFC_SR_CMD_DONE)
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@ -1713,7 +1718,7 @@ static int nfc_wait_interrupt(struct atmel_nand_host *host, u32 flag)
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if (flag & NFC_SR_XFR_DONE)
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comp[index++] = &host->nfc->comp_xfer_done;
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if (flag & NFC_SR_RB_EDGE)
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if (flag & host->nfc->caps->rb_mask)
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comp[index++] = &host->nfc->comp_ready;
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if (flag & NFC_SR_CMD_DONE)
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@ -1781,7 +1786,7 @@ static int nfc_device_ready(struct mtd_info *mtd)
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dev_err(host->dev, "Lost the interrupt flags: 0x%08x\n",
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mask & status);
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return status & NFC_SR_RB_EDGE;
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return status & host->nfc->caps->rb_mask;
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}
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static void nfc_select_chip(struct mtd_info *mtd, int chip)
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@ -1954,8 +1959,8 @@ static void nfc_nand_command(struct mtd_info *mtd, unsigned int command,
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}
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/* fall through */
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default:
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nfc_prepare_interrupt(host, NFC_SR_RB_EDGE);
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nfc_wait_interrupt(host, NFC_SR_RB_EDGE);
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nfc_prepare_interrupt(host, host->nfc->caps->rb_mask);
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nfc_wait_interrupt(host, host->nfc->caps->rb_mask);
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}
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}
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@ -2352,6 +2357,11 @@ static int atmel_nand_nfc_probe(struct platform_device *pdev)
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}
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}
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nfc->caps = (const struct atmel_nand_nfc_caps *)
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of_device_get_match_data(&pdev->dev);
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if (!nfc->caps)
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return -ENODEV;
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nfc_writel(nfc->hsmc_regs, IDR, 0xffffffff);
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nfc_readl(nfc->hsmc_regs, SR); /* clear the NFC_SR */
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@ -2380,8 +2390,17 @@ static int atmel_nand_nfc_remove(struct platform_device *pdev)
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return 0;
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}
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static const struct atmel_nand_nfc_caps sama5d3_nfc_caps = {
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.rb_mask = NFC_SR_RB_EDGE0,
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};
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static const struct atmel_nand_nfc_caps sama5d4_nfc_caps = {
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.rb_mask = NFC_SR_RB_EDGE3,
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};
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static const struct of_device_id atmel_nand_nfc_match[] = {
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{ .compatible = "atmel,sama5d3-nfc" },
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{ .compatible = "atmel,sama5d3-nfc", .data = &sama5d3_nfc_caps },
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{ .compatible = "atmel,sama5d4-nfc", .data = &sama5d4_nfc_caps },
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, atmel_nand_nfc_match);
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@ -42,7 +42,8 @@
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#define NFC_SR_UNDEF (1 << 21)
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#define NFC_SR_AWB (1 << 22)
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#define NFC_SR_ASE (1 << 23)
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#define NFC_SR_RB_EDGE (1 << 24)
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#define NFC_SR_RB_EDGE0 (1 << 24)
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#define NFC_SR_RB_EDGE3 (1 << 27)
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#define ATMEL_HSMC_NFC_IER 0x0c
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#define ATMEL_HSMC_NFC_IDR 0x10
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