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drm/amdgpu: fix handling order in scheduler CS
We need to clear parser.ibs and num_ibs before amd_sched_fence_create, otherwise the IB could be freed twice if fence creates fails. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
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@ -858,11 +858,14 @@ int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
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job->base.sched = &ring->sched;
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job->base.s_entity = &parser.ctx->rings[ring->idx].entity;
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job->adev = parser.adev;
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job->ibs = parser.ibs;
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job->num_ibs = parser.num_ibs;
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job->owner = parser.filp;
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job->free_job = amdgpu_cs_free_job;
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job->ibs = parser.ibs;
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job->num_ibs = parser.num_ibs;
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parser.ibs = NULL;
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parser.num_ibs = 0;
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if (job->ibs[job->num_ibs - 1].user) {
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job->uf = parser.uf;
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job->ibs[job->num_ibs - 1].user = &job->uf;
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@ -884,9 +887,6 @@ int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
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&fence->base);
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job->ibs[job->num_ibs - 1].sequence = cs->out.handle;
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parser.ibs = NULL;
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parser.num_ibs = 0;
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trace_amdgpu_cs_ioctl(job);
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amd_sched_entity_push_job(&job->base);
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