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drm/i915: Teach intel_workarounds to use uncore mmio access
Start weaning ourselves off the implicit I915_WRITE macro madness and start using the explicit intel_uncore mmio access. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190412202458.10653-1-chris@chris-wilson.co.uk
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39564ae86d
commit
5d75dc2b08
drivers/gpu/drm/i915
@ -729,9 +729,9 @@ cfl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
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}
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static void
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wa_init_mcr(struct drm_i915_private *dev_priv, struct i915_wa_list *wal)
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wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal)
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{
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const struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
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const struct sseu_dev_info *sseu = &RUNTIME_INFO(i915)->sseu;
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u32 mcr_slice_subslice_mask;
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/*
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@ -747,14 +747,15 @@ wa_init_mcr(struct drm_i915_private *dev_priv, struct i915_wa_list *wal)
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* something more complex that requires checking the range of every
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* MMIO read).
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*/
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if (INTEL_GEN(dev_priv) >= 10 &&
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if (INTEL_GEN(i915) >= 10 &&
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is_power_of_2(sseu->slice_mask)) {
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/*
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* read FUSE3 for enabled L3 Bank IDs, if L3 Bank matches
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* enabled subslice, no need to redirect MCR packet
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*/
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u32 slice = fls(sseu->slice_mask);
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u32 fuse3 = I915_READ(GEN10_MIRROR_FUSE3);
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u32 fuse3 =
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intel_uncore_read(&i915->uncore, GEN10_MIRROR_FUSE3);
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u8 ss_mask = sseu->subslice_mask[slice];
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u8 enabled_mask = (ss_mask | ss_mask >>
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@ -768,7 +769,7 @@ wa_init_mcr(struct drm_i915_private *dev_priv, struct i915_wa_list *wal)
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WARN_ON((enabled_mask & disabled_mask) != enabled_mask);
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}
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if (INTEL_GEN(dev_priv) >= 11)
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if (INTEL_GEN(i915) >= 11)
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mcr_slice_subslice_mask = GEN11_MCR_SLICE_MASK |
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GEN11_MCR_SUBSLICE_MASK;
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else
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@ -788,7 +789,7 @@ wa_init_mcr(struct drm_i915_private *dev_priv, struct i915_wa_list *wal)
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wa_write_masked_or(wal,
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GEN8_MCR_SELECTOR,
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mcr_slice_subslice_mask,
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intel_calculate_mcr_s_ss_select(dev_priv));
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intel_calculate_mcr_s_ss_select(i915));
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}
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static void
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@ -897,15 +898,14 @@ void intel_gt_init_workarounds(struct drm_i915_private *i915)
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}
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static enum forcewake_domains
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wal_get_fw_for_rmw(struct drm_i915_private *dev_priv,
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const struct i915_wa_list *wal)
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wal_get_fw_for_rmw(struct intel_uncore *uncore, const struct i915_wa_list *wal)
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{
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enum forcewake_domains fw = 0;
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struct i915_wa *wa;
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unsigned int i;
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for (i = 0, wa = wal->list; i < wal->count; i++, wa++)
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fw |= intel_uncore_forcewake_for_reg(&dev_priv->uncore,
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fw |= intel_uncore_forcewake_for_reg(uncore,
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wa->reg,
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FW_REG_READ |
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FW_REG_WRITE);
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@ -914,7 +914,7 @@ wal_get_fw_for_rmw(struct drm_i915_private *dev_priv,
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}
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static void
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wa_list_apply(struct drm_i915_private *dev_priv, const struct i915_wa_list *wal)
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wa_list_apply(struct intel_uncore *uncore, const struct i915_wa_list *wal)
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{
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enum forcewake_domains fw;
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unsigned long flags;
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@ -924,27 +924,22 @@ wa_list_apply(struct drm_i915_private *dev_priv, const struct i915_wa_list *wal)
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if (!wal->count)
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return;
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fw = wal_get_fw_for_rmw(dev_priv, wal);
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fw = wal_get_fw_for_rmw(uncore, wal);
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spin_lock_irqsave(&dev_priv->uncore.lock, flags);
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intel_uncore_forcewake_get__locked(&dev_priv->uncore, fw);
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spin_lock_irqsave(&uncore->lock, flags);
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intel_uncore_forcewake_get__locked(uncore, fw);
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for (i = 0, wa = wal->list; i < wal->count; i++, wa++) {
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u32 val = I915_READ_FW(wa->reg);
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val &= ~wa->mask;
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val |= wa->val;
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I915_WRITE_FW(wa->reg, val);
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intel_uncore_rmw_fw(uncore, wa->reg, wa->mask, wa->val);
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}
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intel_uncore_forcewake_put__locked(&dev_priv->uncore, fw);
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spin_unlock_irqrestore(&dev_priv->uncore.lock, flags);
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intel_uncore_forcewake_put__locked(uncore, fw);
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spin_unlock_irqrestore(&uncore->lock, flags);
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}
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void intel_gt_apply_workarounds(struct drm_i915_private *dev_priv)
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void intel_gt_apply_workarounds(struct drm_i915_private *i915)
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{
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wa_list_apply(dev_priv, &dev_priv->gt_wa_list);
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wa_list_apply(&i915->uncore, &i915->gt_wa_list);
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}
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static bool
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@ -961,7 +956,7 @@ wa_verify(const struct i915_wa *wa, u32 cur, const char *name, const char *from)
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return true;
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}
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static bool wa_list_verify(struct drm_i915_private *dev_priv,
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static bool wa_list_verify(struct intel_uncore *uncore,
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const struct i915_wa_list *wal,
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const char *from)
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{
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@ -970,15 +965,17 @@ static bool wa_list_verify(struct drm_i915_private *dev_priv,
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bool ok = true;
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for (i = 0, wa = wal->list; i < wal->count; i++, wa++)
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ok &= wa_verify(wa, I915_READ(wa->reg), wal->name, from);
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ok &= wa_verify(wa,
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intel_uncore_read(uncore, wa->reg),
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wal->name, from);
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return ok;
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}
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bool intel_gt_verify_workarounds(struct drm_i915_private *dev_priv,
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bool intel_gt_verify_workarounds(struct drm_i915_private *i915,
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const char *from)
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{
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return wa_list_verify(dev_priv, &dev_priv->gt_wa_list, from);
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return wa_list_verify(&i915->uncore, &i915->gt_wa_list, from);
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}
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static void
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@ -1088,8 +1085,8 @@ void intel_engine_init_whitelist(struct intel_engine_cs *engine)
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void intel_engine_apply_whitelist(struct intel_engine_cs *engine)
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{
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struct drm_i915_private *dev_priv = engine->i915;
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const struct i915_wa_list *wal = &engine->whitelist;
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struct intel_uncore *uncore = engine->uncore;
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const u32 base = engine->mmio_base;
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struct i915_wa *wa;
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unsigned int i;
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@ -1098,13 +1095,15 @@ void intel_engine_apply_whitelist(struct intel_engine_cs *engine)
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return;
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for (i = 0, wa = wal->list; i < wal->count; i++, wa++)
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I915_WRITE(RING_FORCE_TO_NONPRIV(base, i),
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i915_mmio_reg_offset(wa->reg));
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intel_uncore_write(uncore,
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RING_FORCE_TO_NONPRIV(base, i),
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i915_mmio_reg_offset(wa->reg));
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/* And clear the rest just in case of garbage */
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for (; i < RING_MAX_NONPRIV_SLOTS; i++)
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I915_WRITE(RING_FORCE_TO_NONPRIV(base, i),
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i915_mmio_reg_offset(RING_NOPID(base)));
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intel_uncore_write(uncore,
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RING_FORCE_TO_NONPRIV(base, i),
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i915_mmio_reg_offset(RING_NOPID(base)));
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}
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static void
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@ -1253,7 +1252,7 @@ void intel_engine_init_workarounds(struct intel_engine_cs *engine)
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void intel_engine_apply_workarounds(struct intel_engine_cs *engine)
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{
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wa_list_apply(engine->i915, &engine->wa_list);
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wa_list_apply(engine->uncore, &engine->wa_list);
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}
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#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
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@ -20,9 +20,9 @@ static inline void intel_wa_list_free(struct i915_wa_list *wal)
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void intel_engine_init_ctx_wa(struct intel_engine_cs *engine);
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int intel_engine_emit_ctx_wa(struct i915_request *rq);
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void intel_gt_init_workarounds(struct drm_i915_private *dev_priv);
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void intel_gt_apply_workarounds(struct drm_i915_private *dev_priv);
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bool intel_gt_verify_workarounds(struct drm_i915_private *dev_priv,
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void intel_gt_init_workarounds(struct drm_i915_private *i915);
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void intel_gt_apply_workarounds(struct drm_i915_private *i915);
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bool intel_gt_verify_workarounds(struct drm_i915_private *i915,
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const char *from);
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void intel_engine_init_whitelist(struct intel_engine_cs *engine);
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@ -750,10 +750,11 @@ static bool verify_gt_engine_wa(struct drm_i915_private *i915,
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enum intel_engine_id id;
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bool ok = true;
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ok &= wa_list_verify(i915, &lists->gt_wa_list, str);
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ok &= wa_list_verify(&i915->uncore, &lists->gt_wa_list, str);
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for_each_engine(engine, i915, id)
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ok &= wa_list_verify(i915, &lists->engine[id].wa_list, str);
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ok &= wa_list_verify(engine->uncore,
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&lists->engine[id].wa_list, str);
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return ok;
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}
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