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coresight: ETM: Add support for Arm Cortex-A73 and Cortex-A35
Add ETM PIDs of the Arm cortex-A CPUs to the white list of ETMs. While at it add a helper macro to make it easier to add the new entries. Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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@ -1027,7 +1027,8 @@ static int etm4_probe(struct amba_device *adev, const struct amba_id *id)
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}
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pm_runtime_put(&adev->dev);
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dev_info(dev, "%s initialized\n", (char *)id->data);
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dev_info(dev, "CPU%d: ETM v%d.%d initialized\n",
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drvdata->cpu, drvdata->arch >> 4, drvdata->arch & 0xf);
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if (boot_enable) {
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coresight_enable(drvdata->csdev);
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@ -1045,23 +1046,19 @@ static int etm4_probe(struct amba_device *adev, const struct amba_id *id)
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return ret;
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}
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#define ETM4x_AMBA_ID(pid) \
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{ \
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.id = pid, \
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.mask = 0x000fffff, \
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}
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static const struct amba_id etm4_ids[] = {
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{ /* ETM 4.0 - Cortex-A53 */
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.id = 0x000bb95d,
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.mask = 0x000fffff,
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.data = "ETM 4.0",
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},
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{ /* ETM 4.0 - Cortex-A57 */
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.id = 0x000bb95e,
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.mask = 0x000fffff,
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.data = "ETM 4.0",
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},
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{ /* ETM 4.0 - A72, Maia, HiSilicon */
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.id = 0x000bb95a,
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.mask = 0x000fffff,
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.data = "ETM 4.0",
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},
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{ 0, 0},
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ETM4x_AMBA_ID(0x000bb95d), /* Cortex-A53 */
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ETM4x_AMBA_ID(0x000bb95e), /* Cortex-A57 */
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ETM4x_AMBA_ID(0x000bb95a), /* Cortex-A72 */
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ETM4x_AMBA_ID(0x000bb959), /* Cortex-A73 */
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ETM4x_AMBA_ID(0x000bb9da), /* Cortex-A35 */
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{},
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};
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static struct amba_driver etm4x_driver = {
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