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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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gma500: Add the core DRM files and headers
Not really a nice way to split this up further for submission. This provides all the DRM interfacing logic, the headers and relevant glue. Signed-off-by: Alan Cox <alan@linux.intel.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
This commit is contained in:
Alan Cox
Dave Airlie
parent
5091b7eb3f
commit
5c49fd3aa0
207
drivers/gpu/drm/gma500/psb_drm.h
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207
drivers/gpu/drm/gma500/psb_drm.h
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@ -0,0 +1,207 @@
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/**************************************************************************
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* Copyright (c) 2007-2011, Intel Corporation.
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* All Rights Reserved.
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* Copyright (c) 2008, Tungsten Graphics Inc. Cedar Park, TX., USA.
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* All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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*
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**************************************************************************/
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#ifndef _PSB_DRM_H_
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#define _PSB_DRM_H_
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#define PSB_NUM_PIPE 3
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#define PSB_GPU_ACCESS_READ (1ULL << 32)
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#define PSB_GPU_ACCESS_WRITE (1ULL << 33)
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#define PSB_GPU_ACCESS_MASK (PSB_GPU_ACCESS_READ | PSB_GPU_ACCESS_WRITE)
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#define PSB_BO_FLAG_COMMAND (1ULL << 52)
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/*
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* Feedback components:
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*/
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struct drm_psb_sizes_arg {
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u32 ta_mem_size;
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u32 mmu_size;
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u32 pds_size;
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u32 rastgeom_size;
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u32 tt_size;
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u32 vram_size;
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};
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struct drm_psb_dpst_lut_arg {
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uint8_t lut[256];
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int output_id;
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};
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#define PSB_DC_CRTC_SAVE 0x01
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#define PSB_DC_CRTC_RESTORE 0x02
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#define PSB_DC_OUTPUT_SAVE 0x04
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#define PSB_DC_OUTPUT_RESTORE 0x08
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#define PSB_DC_CRTC_MASK 0x03
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#define PSB_DC_OUTPUT_MASK 0x0C
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struct drm_psb_dc_state_arg {
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u32 flags;
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u32 obj_id;
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};
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struct drm_psb_mode_operation_arg {
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u32 obj_id;
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u16 operation;
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struct drm_mode_modeinfo mode;
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void *data;
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};
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struct drm_psb_stolen_memory_arg {
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u32 base;
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u32 size;
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};
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/*Display Register Bits*/
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#define REGRWBITS_PFIT_CONTROLS (1 << 0)
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#define REGRWBITS_PFIT_AUTOSCALE_RATIOS (1 << 1)
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#define REGRWBITS_PFIT_PROGRAMMED_SCALE_RATIOS (1 << 2)
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#define REGRWBITS_PIPEASRC (1 << 3)
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#define REGRWBITS_PIPEBSRC (1 << 4)
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#define REGRWBITS_VTOTAL_A (1 << 5)
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#define REGRWBITS_VTOTAL_B (1 << 6)
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#define REGRWBITS_DSPACNTR (1 << 8)
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#define REGRWBITS_DSPBCNTR (1 << 9)
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#define REGRWBITS_DSPCCNTR (1 << 10)
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/*Overlay Register Bits*/
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#define OV_REGRWBITS_OVADD (1 << 0)
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#define OV_REGRWBITS_OGAM_ALL (1 << 1)
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#define OVC_REGRWBITS_OVADD (1 << 2)
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#define OVC_REGRWBITS_OGAM_ALL (1 << 3)
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struct drm_psb_register_rw_arg {
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u32 b_force_hw_on;
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u32 display_read_mask;
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u32 display_write_mask;
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struct {
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u32 pfit_controls;
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u32 pfit_autoscale_ratios;
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u32 pfit_programmed_scale_ratios;
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u32 pipeasrc;
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u32 pipebsrc;
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u32 vtotal_a;
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u32 vtotal_b;
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} display;
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u32 overlay_read_mask;
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u32 overlay_write_mask;
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struct {
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u32 OVADD;
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u32 OGAMC0;
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u32 OGAMC1;
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u32 OGAMC2;
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u32 OGAMC3;
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u32 OGAMC4;
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u32 OGAMC5;
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u32 IEP_ENABLED;
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u32 IEP_BLE_MINMAX;
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u32 IEP_BSSCC_CONTROL;
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u32 b_wait_vblank;
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} overlay;
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u32 sprite_enable_mask;
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u32 sprite_disable_mask;
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struct {
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u32 dspa_control;
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u32 dspa_key_value;
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u32 dspa_key_mask;
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u32 dspc_control;
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u32 dspc_stride;
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u32 dspc_position;
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u32 dspc_linear_offset;
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u32 dspc_size;
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u32 dspc_surface;
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} sprite;
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u32 subpicture_enable_mask;
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u32 subpicture_disable_mask;
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};
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/* Controlling the kernel modesetting buffers */
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#define DRM_PSB_SIZES 0x07
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#define DRM_PSB_FUSE_REG 0x08
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#define DRM_PSB_DC_STATE 0x0A
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#define DRM_PSB_ADB 0x0B
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#define DRM_PSB_MODE_OPERATION 0x0C
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#define DRM_PSB_STOLEN_MEMORY 0x0D
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#define DRM_PSB_REGISTER_RW 0x0E
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/*
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* NOTE: Add new commands here, but increment
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* the values below and increment their
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* corresponding defines where they're
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* defined elsewhere.
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*/
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#define DRM_PSB_GEM_CREATE 0x10
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#define DRM_PSB_2D_OP 0x11 /* Will be merged later */
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#define DRM_PSB_GEM_MMAP 0x12
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#define DRM_PSB_DPST 0x1B
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#define DRM_PSB_GAMMA 0x1C
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#define DRM_PSB_DPST_BL 0x1D
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#define DRM_PSB_GET_PIPE_FROM_CRTC_ID 0x1F
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#define PSB_MODE_OPERATION_MODE_VALID 0x01
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#define PSB_MODE_OPERATION_SET_DC_BASE 0x02
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struct drm_psb_get_pipe_from_crtc_id_arg {
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/** ID of CRTC being requested **/
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u32 crtc_id;
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/** pipe of requested CRTC **/
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u32 pipe;
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};
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/* FIXME: move this into a medfield header once we are sure it isn't needed for an
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ioctl */
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struct psb_drm_dpu_rect {
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int x, y;
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int width, height;
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};
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struct drm_psb_gem_create {
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__u64 size;
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__u32 handle;
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__u32 flags;
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#define PSB_GEM_CREATE_STOLEN 1 /* Stolen memory can be used */
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};
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struct drm_psb_gem_mmap {
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__u32 handle;
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__u32 pad;
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/**
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* Fake offset to use for subsequent mmap call
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*
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* This is a fixed-size type for 32/64 compatibility.
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*/
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__u64 offset;
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};
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#endif
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1210
drivers/gpu/drm/gma500/psb_drv.c
Normal file
1210
drivers/gpu/drm/gma500/psb_drv.c
Normal file
File diff suppressed because it is too large
Load Diff
924
drivers/gpu/drm/gma500/psb_drv.h
Normal file
924
drivers/gpu/drm/gma500/psb_drv.h
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@ -0,0 +1,924 @@
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/**************************************************************************
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* Copyright (c) 2007-2011, Intel Corporation.
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* All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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*
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**************************************************************************/
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#ifndef _PSB_DRV_H_
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#define _PSB_DRV_H_
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#include <linux/kref.h>
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#include <drm/drmP.h>
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#include "drm_global.h"
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#include "gem_glue.h"
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#include "psb_drm.h"
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#include "psb_reg.h"
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#include "psb_intel_drv.h"
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#include "gtt.h"
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#include "power.h"
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#include "oaktrail.h"
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/* Append new drm mode definition here, align with libdrm definition */
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#define DRM_MODE_SCALE_NO_SCALE 2
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enum {
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CHIP_PSB_8108 = 0, /* Poulsbo */
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CHIP_PSB_8109 = 1, /* Poulsbo */
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CHIP_MRST_4100 = 2, /* Moorestown/Oaktrail */
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CHIP_MFLD_0130 = 3, /* Medfield */
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};
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#define IS_MRST(dev) (((dev)->pci_device & 0xfffc) == 0x4100)
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#define IS_MFLD(dev) (((dev)->pci_device & 0xfff8) == 0x0130)
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/*
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* Driver definitions
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*/
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#define DRIVER_NAME "gma500"
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#define DRIVER_DESC "DRM driver for the Intel GMA500"
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#define PSB_DRM_DRIVER_DATE "2011-06-06"
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#define PSB_DRM_DRIVER_MAJOR 1
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#define PSB_DRM_DRIVER_MINOR 0
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#define PSB_DRM_DRIVER_PATCHLEVEL 0
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/*
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* Hardware offsets
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*/
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#define PSB_VDC_OFFSET 0x00000000
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#define PSB_VDC_SIZE 0x000080000
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#define MRST_MMIO_SIZE 0x0000C0000
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#define MDFLD_MMIO_SIZE 0x000100000
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#define PSB_SGX_SIZE 0x8000
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#define PSB_SGX_OFFSET 0x00040000
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#define MRST_SGX_OFFSET 0x00080000
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/*
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* PCI resource identifiers
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*/
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#define PSB_MMIO_RESOURCE 0
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#define PSB_GATT_RESOURCE 2
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#define PSB_GTT_RESOURCE 3
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/*
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* PCI configuration
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*/
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#define PSB_GMCH_CTRL 0x52
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#define PSB_BSM 0x5C
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#define _PSB_GMCH_ENABLED 0x4
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#define PSB_PGETBL_CTL 0x2020
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#define _PSB_PGETBL_ENABLED 0x00000001
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#define PSB_SGX_2D_SLAVE_PORT 0x4000
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/* To get rid of */
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#define PSB_TT_PRIV0_LIMIT (256*1024*1024)
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#define PSB_TT_PRIV0_PLIMIT (PSB_TT_PRIV0_LIMIT >> PAGE_SHIFT)
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/*
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* SGX side MMU definitions (these can probably go)
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*/
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/*
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* Flags for external memory type field.
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*/
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#define PSB_MMU_CACHED_MEMORY 0x0001 /* Bind to MMU only */
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#define PSB_MMU_RO_MEMORY 0x0002 /* MMU RO memory */
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#define PSB_MMU_WO_MEMORY 0x0004 /* MMU WO memory */
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/*
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* PTE's and PDE's
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*/
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#define PSB_PDE_MASK 0x003FFFFF
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#define PSB_PDE_SHIFT 22
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#define PSB_PTE_SHIFT 12
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/*
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* Cache control
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*/
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#define PSB_PTE_VALID 0x0001 /* PTE / PDE valid */
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#define PSB_PTE_WO 0x0002 /* Write only */
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#define PSB_PTE_RO 0x0004 /* Read only */
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#define PSB_PTE_CACHED 0x0008 /* CPU cache coherent */
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/*
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* VDC registers and bits
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*/
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#define PSB_MSVDX_CLOCKGATING 0x2064
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#define PSB_TOPAZ_CLOCKGATING 0x2068
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#define PSB_HWSTAM 0x2098
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#define PSB_INSTPM 0x20C0
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#define PSB_INT_IDENTITY_R 0x20A4
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#define _MDFLD_PIPEC_EVENT_FLAG (1<<2)
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#define _MDFLD_PIPEC_VBLANK_FLAG (1<<3)
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#define _PSB_DPST_PIPEB_FLAG (1<<4)
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#define _MDFLD_PIPEB_EVENT_FLAG (1<<4)
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#define _PSB_VSYNC_PIPEB_FLAG (1<<5)
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#define _PSB_DPST_PIPEA_FLAG (1<<6)
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#define _PSB_PIPEA_EVENT_FLAG (1<<6)
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#define _PSB_VSYNC_PIPEA_FLAG (1<<7)
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#define _MDFLD_MIPIA_FLAG (1<<16)
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#define _MDFLD_MIPIC_FLAG (1<<17)
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#define _PSB_IRQ_SGX_FLAG (1<<18)
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#define _PSB_IRQ_MSVDX_FLAG (1<<19)
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#define _LNC_IRQ_TOPAZ_FLAG (1<<20)
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/* This flag includes all the display IRQ bits excepts the vblank irqs. */
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#define _MDFLD_DISP_ALL_IRQ_FLAG (_MDFLD_PIPEC_EVENT_FLAG | \
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_MDFLD_PIPEB_EVENT_FLAG | \
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_PSB_PIPEA_EVENT_FLAG | \
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_PSB_VSYNC_PIPEA_FLAG | \
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_MDFLD_MIPIA_FLAG | \
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_MDFLD_MIPIC_FLAG)
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#define PSB_INT_IDENTITY_R 0x20A4
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#define PSB_INT_MASK_R 0x20A8
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#define PSB_INT_ENABLE_R 0x20A0
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#define _PSB_MMU_ER_MASK 0x0001FF00
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#define _PSB_MMU_ER_HOST (1 << 16)
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#define GPIOA 0x5010
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#define GPIOB 0x5014
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#define GPIOC 0x5018
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#define GPIOD 0x501c
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#define GPIOE 0x5020
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#define GPIOF 0x5024
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#define GPIOG 0x5028
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#define GPIOH 0x502c
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#define GPIO_CLOCK_DIR_MASK (1 << 0)
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#define GPIO_CLOCK_DIR_IN (0 << 1)
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#define GPIO_CLOCK_DIR_OUT (1 << 1)
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#define GPIO_CLOCK_VAL_MASK (1 << 2)
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#define GPIO_CLOCK_VAL_OUT (1 << 3)
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#define GPIO_CLOCK_VAL_IN (1 << 4)
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#define GPIO_CLOCK_PULLUP_DISABLE (1 << 5)
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#define GPIO_DATA_DIR_MASK (1 << 8)
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#define GPIO_DATA_DIR_IN (0 << 9)
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#define GPIO_DATA_DIR_OUT (1 << 9)
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#define GPIO_DATA_VAL_MASK (1 << 10)
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#define GPIO_DATA_VAL_OUT (1 << 11)
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#define GPIO_DATA_VAL_IN (1 << 12)
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#define GPIO_DATA_PULLUP_DISABLE (1 << 13)
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#define VCLK_DIVISOR_VGA0 0x6000
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#define VCLK_DIVISOR_VGA1 0x6004
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#define VCLK_POST_DIV 0x6010
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#define PSB_COMM_2D (PSB_ENGINE_2D << 4)
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#define PSB_COMM_3D (PSB_ENGINE_3D << 4)
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#define PSB_COMM_TA (PSB_ENGINE_TA << 4)
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#define PSB_COMM_HP (PSB_ENGINE_HP << 4)
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#define PSB_COMM_USER_IRQ (1024 >> 2)
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#define PSB_COMM_USER_IRQ_LOST (PSB_COMM_USER_IRQ + 1)
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#define PSB_COMM_FW (2048 >> 2)
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#define PSB_UIRQ_VISTEST 1
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#define PSB_UIRQ_OOM_REPLY 2
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#define PSB_UIRQ_FIRE_TA_REPLY 3
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#define PSB_UIRQ_FIRE_RASTER_REPLY 4
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#define PSB_2D_SIZE (256*1024*1024)
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#define PSB_MAX_RELOC_PAGES 1024
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#define PSB_LOW_REG_OFFS 0x0204
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#define PSB_HIGH_REG_OFFS 0x0600
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#define PSB_NUM_VBLANKS 2
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#define PSB_2D_SIZE (256*1024*1024)
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#define PSB_MAX_RELOC_PAGES 1024
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#define PSB_LOW_REG_OFFS 0x0204
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#define PSB_HIGH_REG_OFFS 0x0600
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#define PSB_NUM_VBLANKS 2
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#define PSB_WATCHDOG_DELAY (DRM_HZ * 2)
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#define PSB_LID_DELAY (DRM_HZ / 10)
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#define MDFLD_PNW_B0 0x04
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#define MDFLD_PNW_C0 0x08
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#define MDFLD_DSR_2D_3D_0 (1 << 0)
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#define MDFLD_DSR_2D_3D_2 (1 << 1)
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#define MDFLD_DSR_CURSOR_0 (1 << 2)
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#define MDFLD_DSR_CURSOR_2 (1 << 3)
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#define MDFLD_DSR_OVERLAY_0 (1 << 4)
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#define MDFLD_DSR_OVERLAY_2 (1 << 5)
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#define MDFLD_DSR_MIPI_CONTROL (1 << 6)
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#define MDFLD_DSR_DAMAGE_MASK_0 ((1 << 0) | (1 << 2) | (1 << 4))
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#define MDFLD_DSR_DAMAGE_MASK_2 ((1 << 1) | (1 << 3) | (1 << 5))
|
||||
#define MDFLD_DSR_2D_3D (MDFLD_DSR_2D_3D_0 | MDFLD_DSR_2D_3D_2)
|
||||
|
||||
#define MDFLD_DSR_RR 45
|
||||
#define MDFLD_DPU_ENABLE (1 << 31)
|
||||
#define MDFLD_DSR_FULLSCREEN (1 << 30)
|
||||
#define MDFLD_DSR_DELAY (DRM_HZ / MDFLD_DSR_RR)
|
||||
|
||||
#define PSB_PWR_STATE_ON 1
|
||||
#define PSB_PWR_STATE_OFF 2
|
||||
|
||||
#define PSB_PMPOLICY_NOPM 0
|
||||
#define PSB_PMPOLICY_CLOCKGATING 1
|
||||
#define PSB_PMPOLICY_POWERDOWN 2
|
||||
|
||||
#define PSB_PMSTATE_POWERUP 0
|
||||
#define PSB_PMSTATE_CLOCKGATED 1
|
||||
#define PSB_PMSTATE_POWERDOWN 2
|
||||
#define PSB_PCIx_MSI_ADDR_LOC 0x94
|
||||
#define PSB_PCIx_MSI_DATA_LOC 0x98
|
||||
|
||||
/* Medfield crystal settings */
|
||||
#define KSEL_CRYSTAL_19 1
|
||||
#define KSEL_BYPASS_19 5
|
||||
#define KSEL_BYPASS_25 6
|
||||
#define KSEL_BYPASS_83_100 7
|
||||
|
||||
struct opregion_header;
|
||||
struct opregion_acpi;
|
||||
struct opregion_swsci;
|
||||
struct opregion_asle;
|
||||
|
||||
struct psb_intel_opregion {
|
||||
struct opregion_header *header;
|
||||
struct opregion_acpi *acpi;
|
||||
struct opregion_swsci *swsci;
|
||||
struct opregion_asle *asle;
|
||||
int enabled;
|
||||
};
|
||||
|
||||
struct psb_ops;
|
||||
|
||||
struct drm_psb_private {
|
||||
struct drm_device *dev;
|
||||
const struct psb_ops *ops;
|
||||
|
||||
struct psb_gtt gtt;
|
||||
|
||||
/* GTT Memory manager */
|
||||
struct psb_gtt_mm *gtt_mm;
|
||||
struct page *scratch_page;
|
||||
u32 *gtt_map;
|
||||
uint32_t stolen_base;
|
||||
void *vram_addr;
|
||||
unsigned long vram_stolen_size;
|
||||
int gtt_initialized;
|
||||
u16 gmch_ctrl; /* Saved GTT setup */
|
||||
u32 pge_ctl;
|
||||
|
||||
struct mutex gtt_mutex;
|
||||
struct resource *gtt_mem; /* Our PCI resource */
|
||||
|
||||
struct psb_mmu_driver *mmu;
|
||||
struct psb_mmu_pd *pf_pd;
|
||||
|
||||
/*
|
||||
* Register base
|
||||
*/
|
||||
|
||||
uint8_t *sgx_reg;
|
||||
uint8_t *vdc_reg;
|
||||
uint32_t gatt_free_offset;
|
||||
|
||||
/*
|
||||
* Fencing / irq.
|
||||
*/
|
||||
|
||||
uint32_t vdc_irq_mask;
|
||||
uint32_t pipestat[PSB_NUM_PIPE];
|
||||
|
||||
spinlock_t irqmask_lock;
|
||||
|
||||
/*
|
||||
* Power
|
||||
*/
|
||||
|
||||
bool suspended;
|
||||
bool display_power;
|
||||
int display_count;
|
||||
|
||||
/*
|
||||
* Modesetting
|
||||
*/
|
||||
struct psb_intel_mode_device mode_dev;
|
||||
|
||||
struct drm_crtc *plane_to_crtc_mapping[PSB_NUM_PIPE];
|
||||
struct drm_crtc *pipe_to_crtc_mapping[PSB_NUM_PIPE];
|
||||
uint32_t num_pipe;
|
||||
|
||||
/*
|
||||
* OSPM info (Power management base) (can go ?)
|
||||
*/
|
||||
uint32_t ospm_base;
|
||||
|
||||
/*
|
||||
* Sizes info
|
||||
*/
|
||||
|
||||
struct drm_psb_sizes_arg sizes;
|
||||
|
||||
u32 fuse_reg_value;
|
||||
u32 video_device_fuse;
|
||||
|
||||
/* PCI revision ID for B0:D2:F0 */
|
||||
uint8_t platform_rev_id;
|
||||
|
||||
/*
|
||||
* LVDS info
|
||||
*/
|
||||
int backlight_duty_cycle; /* restore backlight to this value */
|
||||
bool panel_wants_dither;
|
||||
struct drm_display_mode *panel_fixed_mode;
|
||||
struct drm_display_mode *lfp_lvds_vbt_mode;
|
||||
struct drm_display_mode *sdvo_lvds_vbt_mode;
|
||||
|
||||
struct bdb_lvds_backlight *lvds_bl; /* LVDS backlight info from VBT */
|
||||
struct psb_intel_i2c_chan *lvds_i2c_bus;
|
||||
|
||||
/* Feature bits from the VBIOS */
|
||||
unsigned int int_tv_support:1;
|
||||
unsigned int lvds_dither:1;
|
||||
unsigned int lvds_vbt:1;
|
||||
unsigned int int_crt_support:1;
|
||||
unsigned int lvds_use_ssc:1;
|
||||
int lvds_ssc_freq;
|
||||
bool is_lvds_on;
|
||||
bool is_mipi_on;
|
||||
u32 mipi_ctrl_display;
|
||||
|
||||
unsigned int core_freq;
|
||||
uint32_t iLVDS_enable;
|
||||
|
||||
/* Runtime PM state */
|
||||
int rpm_enabled;
|
||||
|
||||
/* MID specific */
|
||||
struct oaktrail_vbt vbt_data;
|
||||
struct oaktrail_gct_data gct_data;
|
||||
|
||||
/* MIPI Panel type etc */
|
||||
int panel_id;
|
||||
bool dual_mipi; /* dual display - DPI & DBI */
|
||||
bool dpi_panel_on; /* The DPI panel power is on */
|
||||
bool dpi_panel_on2; /* The DPI panel power is on */
|
||||
bool dbi_panel_on; /* The DBI panel power is on */
|
||||
bool dbi_panel_on2; /* The DBI panel power is on */
|
||||
u32 dsr_fb_update; /* DSR FB update counter */
|
||||
|
||||
/* Moorestown HDMI state */
|
||||
struct oaktrail_hdmi_dev *hdmi_priv;
|
||||
|
||||
/* Moorestown pipe config register value cache */
|
||||
uint32_t pipeconf;
|
||||
uint32_t pipeconf1;
|
||||
uint32_t pipeconf2;
|
||||
|
||||
/* Moorestown plane control register value cache */
|
||||
uint32_t dspcntr;
|
||||
uint32_t dspcntr1;
|
||||
uint32_t dspcntr2;
|
||||
|
||||
/* Moorestown MM backlight cache */
|
||||
uint8_t saveBKLTCNT;
|
||||
uint8_t saveBKLTREQ;
|
||||
uint8_t saveBKLTBRTL;
|
||||
|
||||
/*
|
||||
* Register state
|
||||
*/
|
||||
uint32_t saveDSPACNTR;
|
||||
uint32_t saveDSPBCNTR;
|
||||
uint32_t savePIPEACONF;
|
||||
uint32_t savePIPEBCONF;
|
||||
uint32_t savePIPEASRC;
|
||||
uint32_t savePIPEBSRC;
|
||||
uint32_t saveFPA0;
|
||||
uint32_t saveFPA1;
|
||||
uint32_t saveDPLL_A;
|
||||
uint32_t saveDPLL_A_MD;
|
||||
uint32_t saveHTOTAL_A;
|
||||
uint32_t saveHBLANK_A;
|
||||
uint32_t saveHSYNC_A;
|
||||
uint32_t saveVTOTAL_A;
|
||||
uint32_t saveVBLANK_A;
|
||||
uint32_t saveVSYNC_A;
|
||||
uint32_t saveDSPASTRIDE;
|
||||
uint32_t saveDSPASIZE;
|
||||
uint32_t saveDSPAPOS;
|
||||
uint32_t saveDSPABASE;
|
||||
uint32_t saveDSPASURF;
|
||||
uint32_t saveDSPASTATUS;
|
||||
uint32_t saveFPB0;
|
||||
uint32_t saveFPB1;
|
||||
uint32_t saveDPLL_B;
|
||||
uint32_t saveDPLL_B_MD;
|
||||
uint32_t saveHTOTAL_B;
|
||||
uint32_t saveHBLANK_B;
|
||||
uint32_t saveHSYNC_B;
|
||||
uint32_t saveVTOTAL_B;
|
||||
uint32_t saveVBLANK_B;
|
||||
uint32_t saveVSYNC_B;
|
||||
uint32_t saveDSPBSTRIDE;
|
||||
uint32_t saveDSPBSIZE;
|
||||
uint32_t saveDSPBPOS;
|
||||
uint32_t saveDSPBBASE;
|
||||
uint32_t saveDSPBSURF;
|
||||
uint32_t saveDSPBSTATUS;
|
||||
uint32_t saveVCLK_DIVISOR_VGA0;
|
||||
uint32_t saveVCLK_DIVISOR_VGA1;
|
||||
uint32_t saveVCLK_POST_DIV;
|
||||
uint32_t saveVGACNTRL;
|
||||
uint32_t saveADPA;
|
||||
uint32_t saveLVDS;
|
||||
uint32_t saveDVOA;
|
||||
uint32_t saveDVOB;
|
||||
uint32_t saveDVOC;
|
||||
uint32_t savePP_ON;
|
||||
uint32_t savePP_OFF;
|
||||
uint32_t savePP_CONTROL;
|
||||
uint32_t savePP_CYCLE;
|
||||
uint32_t savePFIT_CONTROL;
|
||||
uint32_t savePaletteA[256];
|
||||
uint32_t savePaletteB[256];
|
||||
uint32_t saveBLC_PWM_CTL2;
|
||||
uint32_t saveBLC_PWM_CTL;
|
||||
uint32_t saveCLOCKGATING;
|
||||
uint32_t saveDSPARB;
|
||||
uint32_t saveDSPATILEOFF;
|
||||
uint32_t saveDSPBTILEOFF;
|
||||
uint32_t saveDSPAADDR;
|
||||
uint32_t saveDSPBADDR;
|
||||
uint32_t savePFIT_AUTO_RATIOS;
|
||||
uint32_t savePFIT_PGM_RATIOS;
|
||||
uint32_t savePP_ON_DELAYS;
|
||||
uint32_t savePP_OFF_DELAYS;
|
||||
uint32_t savePP_DIVISOR;
|
||||
uint32_t saveBSM;
|
||||
uint32_t saveVBT;
|
||||
uint32_t saveBCLRPAT_A;
|
||||
uint32_t saveBCLRPAT_B;
|
||||
uint32_t saveDSPALINOFF;
|
||||
uint32_t saveDSPBLINOFF;
|
||||
uint32_t savePERF_MODE;
|
||||
uint32_t saveDSPFW1;
|
||||
uint32_t saveDSPFW2;
|
||||
uint32_t saveDSPFW3;
|
||||
uint32_t saveDSPFW4;
|
||||
uint32_t saveDSPFW5;
|
||||
uint32_t saveDSPFW6;
|
||||
uint32_t saveCHICKENBIT;
|
||||
uint32_t saveDSPACURSOR_CTRL;
|
||||
uint32_t saveDSPBCURSOR_CTRL;
|
||||
uint32_t saveDSPACURSOR_BASE;
|
||||
uint32_t saveDSPBCURSOR_BASE;
|
||||
uint32_t saveDSPACURSOR_POS;
|
||||
uint32_t saveDSPBCURSOR_POS;
|
||||
uint32_t save_palette_a[256];
|
||||
uint32_t save_palette_b[256];
|
||||
uint32_t saveOV_OVADD;
|
||||
uint32_t saveOV_OGAMC0;
|
||||
uint32_t saveOV_OGAMC1;
|
||||
uint32_t saveOV_OGAMC2;
|
||||
uint32_t saveOV_OGAMC3;
|
||||
uint32_t saveOV_OGAMC4;
|
||||
uint32_t saveOV_OGAMC5;
|
||||
uint32_t saveOVC_OVADD;
|
||||
uint32_t saveOVC_OGAMC0;
|
||||
uint32_t saveOVC_OGAMC1;
|
||||
uint32_t saveOVC_OGAMC2;
|
||||
uint32_t saveOVC_OGAMC3;
|
||||
uint32_t saveOVC_OGAMC4;
|
||||
uint32_t saveOVC_OGAMC5;
|
||||
|
||||
/* MSI reg save */
|
||||
uint32_t msi_addr;
|
||||
uint32_t msi_data;
|
||||
|
||||
/* Medfield specific register save state */
|
||||
uint32_t saveHDMIPHYMISCCTL;
|
||||
uint32_t saveHDMIB_CONTROL;
|
||||
uint32_t saveDSPCCNTR;
|
||||
uint32_t savePIPECCONF;
|
||||
uint32_t savePIPECSRC;
|
||||
uint32_t saveHTOTAL_C;
|
||||
uint32_t saveHBLANK_C;
|
||||
uint32_t saveHSYNC_C;
|
||||
uint32_t saveVTOTAL_C;
|
||||
uint32_t saveVBLANK_C;
|
||||
uint32_t saveVSYNC_C;
|
||||
uint32_t saveDSPCSTRIDE;
|
||||
uint32_t saveDSPCSIZE;
|
||||
uint32_t saveDSPCPOS;
|
||||
uint32_t saveDSPCSURF;
|
||||
uint32_t saveDSPCSTATUS;
|
||||
uint32_t saveDSPCLINOFF;
|
||||
uint32_t saveDSPCTILEOFF;
|
||||
uint32_t saveDSPCCURSOR_CTRL;
|
||||
uint32_t saveDSPCCURSOR_BASE;
|
||||
uint32_t saveDSPCCURSOR_POS;
|
||||
uint32_t save_palette_c[256];
|
||||
uint32_t saveOV_OVADD_C;
|
||||
uint32_t saveOV_OGAMC0_C;
|
||||
uint32_t saveOV_OGAMC1_C;
|
||||
uint32_t saveOV_OGAMC2_C;
|
||||
uint32_t saveOV_OGAMC3_C;
|
||||
uint32_t saveOV_OGAMC4_C;
|
||||
uint32_t saveOV_OGAMC5_C;
|
||||
|
||||
/* DSI register save */
|
||||
uint32_t saveDEVICE_READY_REG;
|
||||
uint32_t saveINTR_EN_REG;
|
||||
uint32_t saveDSI_FUNC_PRG_REG;
|
||||
uint32_t saveHS_TX_TIMEOUT_REG;
|
||||
uint32_t saveLP_RX_TIMEOUT_REG;
|
||||
uint32_t saveTURN_AROUND_TIMEOUT_REG;
|
||||
uint32_t saveDEVICE_RESET_REG;
|
||||
uint32_t saveDPI_RESOLUTION_REG;
|
||||
uint32_t saveHORIZ_SYNC_PAD_COUNT_REG;
|
||||
uint32_t saveHORIZ_BACK_PORCH_COUNT_REG;
|
||||
uint32_t saveHORIZ_FRONT_PORCH_COUNT_REG;
|
||||
uint32_t saveHORIZ_ACTIVE_AREA_COUNT_REG;
|
||||
uint32_t saveVERT_SYNC_PAD_COUNT_REG;
|
||||
uint32_t saveVERT_BACK_PORCH_COUNT_REG;
|
||||
uint32_t saveVERT_FRONT_PORCH_COUNT_REG;
|
||||
uint32_t saveHIGH_LOW_SWITCH_COUNT_REG;
|
||||
uint32_t saveINIT_COUNT_REG;
|
||||
uint32_t saveMAX_RET_PAK_REG;
|
||||
uint32_t saveVIDEO_FMT_REG;
|
||||
uint32_t saveEOT_DISABLE_REG;
|
||||
uint32_t saveLP_BYTECLK_REG;
|
||||
uint32_t saveHS_LS_DBI_ENABLE_REG;
|
||||
uint32_t saveTXCLKESC_REG;
|
||||
uint32_t saveDPHY_PARAM_REG;
|
||||
uint32_t saveMIPI_CONTROL_REG;
|
||||
uint32_t saveMIPI;
|
||||
uint32_t saveMIPI_C;
|
||||
|
||||
/* DPST register save */
|
||||
uint32_t saveHISTOGRAM_INT_CONTROL_REG;
|
||||
uint32_t saveHISTOGRAM_LOGIC_CONTROL_REG;
|
||||
uint32_t savePWM_CONTROL_LOGIC;
|
||||
|
||||
/*
|
||||
* DSI info.
|
||||
*/
|
||||
void * dbi_dsr_info;
|
||||
void * dbi_dpu_info;
|
||||
void * dsi_configs[2];
|
||||
/*
|
||||
* LID-Switch
|
||||
*/
|
||||
spinlock_t lid_lock;
|
||||
struct timer_list lid_timer;
|
||||
struct psb_intel_opregion opregion;
|
||||
u32 *lid_state;
|
||||
u32 lid_last_state;
|
||||
|
||||
/*
|
||||
* Watchdog
|
||||
*/
|
||||
|
||||
uint32_t apm_reg;
|
||||
uint16_t apm_base;
|
||||
|
||||
/*
|
||||
* Used for modifying backlight from
|
||||
* xrandr -- consider removing and using HAL instead
|
||||
*/
|
||||
struct backlight_device *backlight_device;
|
||||
struct drm_property *backlight_property;
|
||||
uint32_t blc_adj1;
|
||||
uint32_t blc_adj2;
|
||||
|
||||
void *fbdev;
|
||||
|
||||
/* 2D acceleration */
|
||||
struct mutex mutex_2d;
|
||||
};
|
||||
|
||||
|
||||
/*
|
||||
* Operations for each board type
|
||||
*/
|
||||
|
||||
struct psb_ops {
|
||||
const char *name;
|
||||
unsigned int accel_2d:1;
|
||||
int pipes; /* Number of output pipes */
|
||||
int crtcs; /* Number of CRTCs */
|
||||
int sgx_offset; /* Base offset of SGX device */
|
||||
|
||||
/* Sub functions */
|
||||
struct drm_crtc_helper_funcs const *crtc_helper;
|
||||
struct drm_crtc_funcs const *crtc_funcs;
|
||||
|
||||
/* Setup hooks */
|
||||
int (*chip_setup)(struct drm_device *dev);
|
||||
void (*chip_teardown)(struct drm_device *dev);
|
||||
|
||||
/* Display management hooks */
|
||||
int (*output_init)(struct drm_device *dev);
|
||||
/* Power management hooks */
|
||||
void (*init_pm)(struct drm_device *dev);
|
||||
int (*save_regs)(struct drm_device *dev);
|
||||
int (*restore_regs)(struct drm_device *dev);
|
||||
int (*power_up)(struct drm_device *dev);
|
||||
int (*power_down)(struct drm_device *dev);
|
||||
|
||||
void (*lvds_bl_power)(struct drm_device *dev, bool on);
|
||||
#ifdef CONFIG_BACKLIGHT_CLASS_DEVICE
|
||||
/* Backlight */
|
||||
int (*backlight_init)(struct drm_device *dev);
|
||||
#endif
|
||||
int i2c_bus; /* I2C bus identifier for Moorestown */
|
||||
};
|
||||
|
||||
|
||||
|
||||
struct psb_mmu_driver;
|
||||
|
||||
extern int drm_crtc_probe_output_modes(struct drm_device *dev, int, int);
|
||||
extern int drm_pick_crtcs(struct drm_device *dev);
|
||||
|
||||
static inline struct drm_psb_private *psb_priv(struct drm_device *dev)
|
||||
{
|
||||
return (struct drm_psb_private *) dev->dev_private;
|
||||
}
|
||||
|
||||
/*
|
||||
* MMU stuff.
|
||||
*/
|
||||
|
||||
extern struct psb_mmu_driver *psb_mmu_driver_init(uint8_t __iomem * registers,
|
||||
int trap_pagefaults,
|
||||
int invalid_type,
|
||||
struct drm_psb_private *dev_priv);
|
||||
extern void psb_mmu_driver_takedown(struct psb_mmu_driver *driver);
|
||||
extern struct psb_mmu_pd *psb_mmu_get_default_pd(struct psb_mmu_driver
|
||||
*driver);
|
||||
extern void psb_mmu_mirror_gtt(struct psb_mmu_pd *pd, uint32_t mmu_offset,
|
||||
uint32_t gtt_start, uint32_t gtt_pages);
|
||||
extern struct psb_mmu_pd *psb_mmu_alloc_pd(struct psb_mmu_driver *driver,
|
||||
int trap_pagefaults,
|
||||
int invalid_type);
|
||||
extern void psb_mmu_free_pagedir(struct psb_mmu_pd *pd);
|
||||
extern void psb_mmu_flush(struct psb_mmu_driver *driver, int rc_prot);
|
||||
extern void psb_mmu_remove_pfn_sequence(struct psb_mmu_pd *pd,
|
||||
unsigned long address,
|
||||
uint32_t num_pages);
|
||||
extern int psb_mmu_insert_pfn_sequence(struct psb_mmu_pd *pd,
|
||||
uint32_t start_pfn,
|
||||
unsigned long address,
|
||||
uint32_t num_pages, int type);
|
||||
extern int psb_mmu_virtual_to_pfn(struct psb_mmu_pd *pd, uint32_t virtual,
|
||||
unsigned long *pfn);
|
||||
|
||||
/*
|
||||
* Enable / disable MMU for different requestors.
|
||||
*/
|
||||
|
||||
|
||||
extern void psb_mmu_set_pd_context(struct psb_mmu_pd *pd, int hw_context);
|
||||
extern int psb_mmu_insert_pages(struct psb_mmu_pd *pd, struct page **pages,
|
||||
unsigned long address, uint32_t num_pages,
|
||||
uint32_t desired_tile_stride,
|
||||
uint32_t hw_tile_stride, int type);
|
||||
extern void psb_mmu_remove_pages(struct psb_mmu_pd *pd,
|
||||
unsigned long address, uint32_t num_pages,
|
||||
uint32_t desired_tile_stride,
|
||||
uint32_t hw_tile_stride);
|
||||
/*
|
||||
*psb_irq.c
|
||||
*/
|
||||
|
||||
extern irqreturn_t psb_irq_handler(DRM_IRQ_ARGS);
|
||||
extern int psb_irq_enable_dpst(struct drm_device *dev);
|
||||
extern int psb_irq_disable_dpst(struct drm_device *dev);
|
||||
extern void psb_irq_preinstall(struct drm_device *dev);
|
||||
extern int psb_irq_postinstall(struct drm_device *dev);
|
||||
extern void psb_irq_uninstall(struct drm_device *dev);
|
||||
extern void psb_irq_turn_on_dpst(struct drm_device *dev);
|
||||
extern void psb_irq_turn_off_dpst(struct drm_device *dev);
|
||||
|
||||
extern void psb_irq_uninstall_islands(struct drm_device *dev, int hw_islands);
|
||||
extern int psb_vblank_wait2(struct drm_device *dev, unsigned int *sequence);
|
||||
extern int psb_vblank_wait(struct drm_device *dev, unsigned int *sequence);
|
||||
extern int psb_enable_vblank(struct drm_device *dev, int crtc);
|
||||
extern void psb_disable_vblank(struct drm_device *dev, int crtc);
|
||||
void
|
||||
psb_enable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask);
|
||||
|
||||
void
|
||||
psb_disable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask);
|
||||
|
||||
extern u32 psb_get_vblank_counter(struct drm_device *dev, int crtc);
|
||||
|
||||
/*
|
||||
* intel_opregion.c
|
||||
*/
|
||||
extern int gma_intel_opregion_init(struct drm_device *dev);
|
||||
extern int gma_intel_opregion_exit(struct drm_device *dev);
|
||||
|
||||
/*
|
||||
* framebuffer.c
|
||||
*/
|
||||
extern int psbfb_probed(struct drm_device *dev);
|
||||
extern int psbfb_remove(struct drm_device *dev,
|
||||
struct drm_framebuffer *fb);
|
||||
/*
|
||||
* accel_2d.c
|
||||
*/
|
||||
extern void psbfb_copyarea(struct fb_info *info,
|
||||
const struct fb_copyarea *region);
|
||||
extern int psbfb_sync(struct fb_info *info);
|
||||
extern void psb_spank(struct drm_psb_private *dev_priv);
|
||||
|
||||
/*
|
||||
* psb_reset.c
|
||||
*/
|
||||
|
||||
extern void psb_lid_timer_init(struct drm_psb_private *dev_priv);
|
||||
extern void psb_lid_timer_takedown(struct drm_psb_private *dev_priv);
|
||||
extern void psb_print_pagefault(struct drm_psb_private *dev_priv);
|
||||
|
||||
/* modesetting */
|
||||
extern void psb_modeset_init(struct drm_device *dev);
|
||||
extern void psb_modeset_cleanup(struct drm_device *dev);
|
||||
extern int psb_fbdev_init(struct drm_device *dev);
|
||||
|
||||
/* backlight.c */
|
||||
int gma_backlight_init(struct drm_device *dev);
|
||||
void gma_backlight_exit(struct drm_device *dev);
|
||||
|
||||
/* oaktrail_crtc.c */
|
||||
extern const struct drm_crtc_helper_funcs oaktrail_helper_funcs;
|
||||
|
||||
/* oaktrail_lvds.c */
|
||||
extern void oaktrail_lvds_init(struct drm_device *dev,
|
||||
struct psb_intel_mode_device *mode_dev);
|
||||
|
||||
/* psb_intel_display.c */
|
||||
extern const struct drm_crtc_helper_funcs psb_intel_helper_funcs;
|
||||
extern const struct drm_crtc_funcs psb_intel_crtc_funcs;
|
||||
|
||||
/* psb_intel_lvds.c */
|
||||
extern const struct drm_connector_helper_funcs
|
||||
psb_intel_lvds_connector_helper_funcs;
|
||||
extern const struct drm_connector_funcs psb_intel_lvds_connector_funcs;
|
||||
|
||||
/* gem.c */
|
||||
extern int psb_gem_init_object(struct drm_gem_object *obj);
|
||||
extern void psb_gem_free_object(struct drm_gem_object *obj);
|
||||
extern int psb_gem_get_aperture(struct drm_device *dev, void *data,
|
||||
struct drm_file *file);
|
||||
extern int psb_gem_dumb_create(struct drm_file *file, struct drm_device *dev,
|
||||
struct drm_mode_create_dumb *args);
|
||||
extern int psb_gem_dumb_destroy(struct drm_file *file, struct drm_device *dev,
|
||||
uint32_t handle);
|
||||
extern int psb_gem_dumb_map_gtt(struct drm_file *file, struct drm_device *dev,
|
||||
uint32_t handle, uint64_t *offset);
|
||||
extern int psb_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
|
||||
extern int psb_gem_create_ioctl(struct drm_device *dev, void *data,
|
||||
struct drm_file *file);
|
||||
extern int psb_gem_mmap_ioctl(struct drm_device *dev, void *data,
|
||||
struct drm_file *file);
|
||||
|
||||
/* psb_device.c */
|
||||
extern const struct psb_ops psb_chip_ops;
|
||||
|
||||
/* oaktrail_device.c */
|
||||
extern const struct psb_ops oaktrail_chip_ops;
|
||||
|
||||
/* cdv_device.c */
|
||||
extern const struct psb_ops cdv_chip_ops;
|
||||
|
||||
/*
|
||||
* Debug print bits setting
|
||||
*/
|
||||
#define PSB_D_GENERAL (1 << 0)
|
||||
#define PSB_D_INIT (1 << 1)
|
||||
#define PSB_D_IRQ (1 << 2)
|
||||
#define PSB_D_ENTRY (1 << 3)
|
||||
/* debug the get H/V BP/FP count */
|
||||
#define PSB_D_HV (1 << 4)
|
||||
#define PSB_D_DBI_BF (1 << 5)
|
||||
#define PSB_D_PM (1 << 6)
|
||||
#define PSB_D_RENDER (1 << 7)
|
||||
#define PSB_D_REG (1 << 8)
|
||||
#define PSB_D_MSVDX (1 << 9)
|
||||
#define PSB_D_TOPAZ (1 << 10)
|
||||
|
||||
extern int drm_psb_no_fb;
|
||||
extern int drm_idle_check_interval;
|
||||
|
||||
/*
|
||||
* Utilities
|
||||
*/
|
||||
|
||||
static inline u32 MRST_MSG_READ32(uint port, uint offset)
|
||||
{
|
||||
int mcr = (0xD0<<24) | (port << 16) | (offset << 8);
|
||||
uint32_t ret_val = 0;
|
||||
struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
|
||||
pci_write_config_dword(pci_root, 0xD0, mcr);
|
||||
pci_read_config_dword(pci_root, 0xD4, &ret_val);
|
||||
pci_dev_put(pci_root);
|
||||
return ret_val;
|
||||
}
|
||||
static inline void MRST_MSG_WRITE32(uint port, uint offset, u32 value)
|
||||
{
|
||||
int mcr = (0xE0<<24) | (port << 16) | (offset << 8) | 0xF0;
|
||||
struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
|
||||
pci_write_config_dword(pci_root, 0xD4, value);
|
||||
pci_write_config_dword(pci_root, 0xD0, mcr);
|
||||
pci_dev_put(pci_root);
|
||||
}
|
||||
static inline u32 MDFLD_MSG_READ32(uint port, uint offset)
|
||||
{
|
||||
int mcr = (0x10<<24) | (port << 16) | (offset << 8);
|
||||
uint32_t ret_val = 0;
|
||||
struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
|
||||
pci_write_config_dword(pci_root, 0xD0, mcr);
|
||||
pci_read_config_dword(pci_root, 0xD4, &ret_val);
|
||||
pci_dev_put(pci_root);
|
||||
return ret_val;
|
||||
}
|
||||
static inline void MDFLD_MSG_WRITE32(uint port, uint offset, u32 value)
|
||||
{
|
||||
int mcr = (0x11<<24) | (port << 16) | (offset << 8) | 0xF0;
|
||||
struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
|
||||
pci_write_config_dword(pci_root, 0xD4, value);
|
||||
pci_write_config_dword(pci_root, 0xD0, mcr);
|
||||
pci_dev_put(pci_root);
|
||||
}
|
||||
|
||||
static inline uint32_t REGISTER_READ(struct drm_device *dev, uint32_t reg)
|
||||
{
|
||||
struct drm_psb_private *dev_priv = dev->dev_private;
|
||||
return ioread32(dev_priv->vdc_reg + reg);
|
||||
}
|
||||
|
||||
#define REG_READ(reg) REGISTER_READ(dev, (reg))
|
||||
|
||||
static inline void REGISTER_WRITE(struct drm_device *dev, uint32_t reg,
|
||||
uint32_t val)
|
||||
{
|
||||
struct drm_psb_private *dev_priv = dev->dev_private;
|
||||
iowrite32((val), dev_priv->vdc_reg + (reg));
|
||||
}
|
||||
|
||||
#define REG_WRITE(reg, val) REGISTER_WRITE(dev, (reg), (val))
|
||||
|
||||
static inline void REGISTER_WRITE16(struct drm_device *dev,
|
||||
uint32_t reg, uint32_t val)
|
||||
{
|
||||
struct drm_psb_private *dev_priv = dev->dev_private;
|
||||
iowrite16((val), dev_priv->vdc_reg + (reg));
|
||||
}
|
||||
|
||||
#define REG_WRITE16(reg, val) REGISTER_WRITE16(dev, (reg), (val))
|
||||
|
||||
static inline void REGISTER_WRITE8(struct drm_device *dev,
|
||||
uint32_t reg, uint32_t val)
|
||||
{
|
||||
struct drm_psb_private *dev_priv = dev->dev_private;
|
||||
iowrite8((val), dev_priv->vdc_reg + (reg));
|
||||
}
|
||||
|
||||
#define REG_WRITE8(reg, val) REGISTER_WRITE8(dev, (reg), (val))
|
||||
|
||||
#define PSB_WVDC32(_val, _offs) iowrite32(_val, dev_priv->vdc_reg + (_offs))
|
||||
#define PSB_RVDC32(_offs) ioread32(dev_priv->vdc_reg + (_offs))
|
||||
|
||||
/* #define TRAP_SGX_PM_FAULT 1 */
|
||||
#ifdef TRAP_SGX_PM_FAULT
|
||||
#define PSB_RSGX32(_offs) \
|
||||
({ \
|
||||
if (inl(dev_priv->apm_base + PSB_APM_STS) & 0x3) { \
|
||||
printk(KERN_ERR \
|
||||
"access sgx when it's off!! (READ) %s, %d\n", \
|
||||
__FILE__, __LINE__); \
|
||||
melay(1000); \
|
||||
} \
|
||||
ioread32(dev_priv->sgx_reg + (_offs)); \
|
||||
})
|
||||
#else
|
||||
#define PSB_RSGX32(_offs) ioread32(dev_priv->sgx_reg + (_offs))
|
||||
#endif
|
||||
#define PSB_WSGX32(_val, _offs) iowrite32(_val, dev_priv->sgx_reg + (_offs))
|
||||
|
||||
#define MSVDX_REG_DUMP 0
|
||||
|
||||
#define PSB_WMSVDX32(_val, _offs) iowrite32(_val, dev_priv->msvdx_reg + (_offs))
|
||||
#define PSB_RMSVDX32(_offs) ioread32(dev_priv->msvdx_reg + (_offs))
|
||||
|
||||
#endif
|
||||
553
drivers/gpu/drm/gma500/psb_irq.c
Normal file
553
drivers/gpu/drm/gma500/psb_irq.c
Normal file
@ -0,0 +1,553 @@
|
||||
/**************************************************************************
|
||||
* Copyright (c) 2007, Intel Corporation.
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*
|
||||
* Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
|
||||
* develop this driver.
|
||||
*
|
||||
**************************************************************************/
|
||||
/*
|
||||
*/
|
||||
|
||||
#include <drm/drmP.h>
|
||||
#include "psb_drv.h"
|
||||
#include "psb_reg.h"
|
||||
#include "psb_intel_reg.h"
|
||||
#include "power.h"
|
||||
|
||||
/*
|
||||
* inline functions
|
||||
*/
|
||||
|
||||
static inline u32
|
||||
psb_pipestat(int pipe)
|
||||
{
|
||||
if (pipe == 0)
|
||||
return PIPEASTAT;
|
||||
if (pipe == 1)
|
||||
return PIPEBSTAT;
|
||||
if (pipe == 2)
|
||||
return PIPECSTAT;
|
||||
BUG();
|
||||
}
|
||||
|
||||
static inline u32
|
||||
mid_pipe_event(int pipe)
|
||||
{
|
||||
if (pipe == 0)
|
||||
return _PSB_PIPEA_EVENT_FLAG;
|
||||
if (pipe == 1)
|
||||
return _MDFLD_PIPEB_EVENT_FLAG;
|
||||
if (pipe == 2)
|
||||
return _MDFLD_PIPEC_EVENT_FLAG;
|
||||
BUG();
|
||||
}
|
||||
|
||||
static inline u32
|
||||
mid_pipe_vsync(int pipe)
|
||||
{
|
||||
if (pipe == 0)
|
||||
return _PSB_VSYNC_PIPEA_FLAG;
|
||||
if (pipe == 1)
|
||||
return _PSB_VSYNC_PIPEB_FLAG;
|
||||
if (pipe == 2)
|
||||
return _MDFLD_PIPEC_VBLANK_FLAG;
|
||||
BUG();
|
||||
}
|
||||
|
||||
static inline u32
|
||||
mid_pipeconf(int pipe)
|
||||
{
|
||||
if (pipe == 0)
|
||||
return PIPEACONF;
|
||||
if (pipe == 1)
|
||||
return PIPEBCONF;
|
||||
if (pipe == 2)
|
||||
return PIPECCONF;
|
||||
BUG();
|
||||
}
|
||||
|
||||
void
|
||||
psb_enable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask)
|
||||
{
|
||||
if ((dev_priv->pipestat[pipe] & mask) != mask) {
|
||||
u32 reg = psb_pipestat(pipe);
|
||||
dev_priv->pipestat[pipe] |= mask;
|
||||
/* Enable the interrupt, clear any pending status */
|
||||
if (gma_power_begin(dev_priv->dev, false)) {
|
||||
u32 writeVal = PSB_RVDC32(reg);
|
||||
writeVal |= (mask | (mask >> 16));
|
||||
PSB_WVDC32(writeVal, reg);
|
||||
(void) PSB_RVDC32(reg);
|
||||
gma_power_end(dev_priv->dev);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void
|
||||
psb_disable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask)
|
||||
{
|
||||
if ((dev_priv->pipestat[pipe] & mask) != 0) {
|
||||
u32 reg = psb_pipestat(pipe);
|
||||
dev_priv->pipestat[pipe] &= ~mask;
|
||||
if (gma_power_begin(dev_priv->dev, false)) {
|
||||
u32 writeVal = PSB_RVDC32(reg);
|
||||
writeVal &= ~mask;
|
||||
PSB_WVDC32(writeVal, reg);
|
||||
(void) PSB_RVDC32(reg);
|
||||
gma_power_end(dev_priv->dev);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void mid_enable_pipe_event(struct drm_psb_private *dev_priv, int pipe)
|
||||
{
|
||||
if (gma_power_begin(dev_priv->dev, false)) {
|
||||
u32 pipe_event = mid_pipe_event(pipe);
|
||||
dev_priv->vdc_irq_mask |= pipe_event;
|
||||
PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R);
|
||||
PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R);
|
||||
gma_power_end(dev_priv->dev);
|
||||
}
|
||||
}
|
||||
|
||||
void mid_disable_pipe_event(struct drm_psb_private *dev_priv, int pipe)
|
||||
{
|
||||
if (dev_priv->pipestat[pipe] == 0) {
|
||||
if (gma_power_begin(dev_priv->dev, false)) {
|
||||
u32 pipe_event = mid_pipe_event(pipe);
|
||||
dev_priv->vdc_irq_mask &= ~pipe_event;
|
||||
PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R);
|
||||
PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R);
|
||||
gma_power_end(dev_priv->dev);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* Display controller interrupt handler for vsync/vblank.
|
||||
*
|
||||
*/
|
||||
static void mid_vblank_handler(struct drm_device *dev, uint32_t pipe)
|
||||
{
|
||||
drm_handle_vblank(dev, pipe);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* Display controller interrupt handler for pipe event.
|
||||
*
|
||||
*/
|
||||
#define WAIT_STATUS_CLEAR_LOOP_COUNT 0xffff
|
||||
static void mid_pipe_event_handler(struct drm_device *dev, uint32_t pipe)
|
||||
{
|
||||
struct drm_psb_private *dev_priv =
|
||||
(struct drm_psb_private *) dev->dev_private;
|
||||
|
||||
uint32_t pipe_stat_val = 0;
|
||||
uint32_t pipe_stat_reg = psb_pipestat(pipe);
|
||||
uint32_t pipe_enable = dev_priv->pipestat[pipe];
|
||||
uint32_t pipe_status = dev_priv->pipestat[pipe] >> 16;
|
||||
uint32_t i = 0;
|
||||
|
||||
spin_lock(&dev_priv->irqmask_lock);
|
||||
|
||||
pipe_stat_val = PSB_RVDC32(pipe_stat_reg);
|
||||
pipe_stat_val &= pipe_enable | pipe_status;
|
||||
pipe_stat_val &= pipe_stat_val >> 16;
|
||||
|
||||
spin_unlock(&dev_priv->irqmask_lock);
|
||||
|
||||
/* clear the 2nd level interrupt status bits */
|
||||
/**
|
||||
* FIXME: shouldn't use while loop here. However, the interrupt
|
||||
* status 'sticky' bits cannot be cleared by setting '1' to that
|
||||
* bit once...
|
||||
*/
|
||||
for (i = 0; i < WAIT_STATUS_CLEAR_LOOP_COUNT; i++) {
|
||||
PSB_WVDC32(PSB_RVDC32(pipe_stat_reg), pipe_stat_reg);
|
||||
(void) PSB_RVDC32(pipe_stat_reg);
|
||||
|
||||
if ((PSB_RVDC32(pipe_stat_reg) & pipe_status) == 0)
|
||||
break;
|
||||
}
|
||||
|
||||
if (i == WAIT_STATUS_CLEAR_LOOP_COUNT)
|
||||
dev_err(dev->dev,
|
||||
"%s, can't clear the status bits in pipe_stat_reg, its value = 0x%x.\n",
|
||||
__func__, PSB_RVDC32(pipe_stat_reg));
|
||||
|
||||
if (pipe_stat_val & PIPE_VBLANK_STATUS)
|
||||
mid_vblank_handler(dev, pipe);
|
||||
|
||||
if (pipe_stat_val & PIPE_TE_STATUS)
|
||||
drm_handle_vblank(dev, pipe);
|
||||
}
|
||||
|
||||
/*
|
||||
* Display controller interrupt handler.
|
||||
*/
|
||||
static void psb_vdc_interrupt(struct drm_device *dev, uint32_t vdc_stat)
|
||||
{
|
||||
if (vdc_stat & _PSB_PIPEA_EVENT_FLAG)
|
||||
mid_pipe_event_handler(dev, 0);
|
||||
}
|
||||
|
||||
irqreturn_t psb_irq_handler(DRM_IRQ_ARGS)
|
||||
{
|
||||
struct drm_device *dev = (struct drm_device *) arg;
|
||||
struct drm_psb_private *dev_priv =
|
||||
(struct drm_psb_private *) dev->dev_private;
|
||||
|
||||
uint32_t vdc_stat, dsp_int = 0, sgx_int = 0;
|
||||
int handled = 0;
|
||||
|
||||
spin_lock(&dev_priv->irqmask_lock);
|
||||
|
||||
vdc_stat = PSB_RVDC32(PSB_INT_IDENTITY_R);
|
||||
|
||||
if (vdc_stat & _MDFLD_DISP_ALL_IRQ_FLAG)
|
||||
dsp_int = 1;
|
||||
|
||||
if (vdc_stat & _PSB_IRQ_SGX_FLAG)
|
||||
sgx_int = 1;
|
||||
|
||||
vdc_stat &= dev_priv->vdc_irq_mask;
|
||||
spin_unlock(&dev_priv->irqmask_lock);
|
||||
|
||||
if (dsp_int && gma_power_is_on(dev)) {
|
||||
psb_vdc_interrupt(dev, vdc_stat);
|
||||
handled = 1;
|
||||
}
|
||||
|
||||
if (sgx_int) {
|
||||
/* Not expected - we have it masked, shut it up */
|
||||
u32 s, s2;
|
||||
s = PSB_RSGX32(PSB_CR_EVENT_STATUS);
|
||||
s2 = PSB_RSGX32(PSB_CR_EVENT_STATUS2);
|
||||
PSB_WSGX32(s, PSB_CR_EVENT_HOST_CLEAR);
|
||||
PSB_WSGX32(s2, PSB_CR_EVENT_HOST_CLEAR2);
|
||||
/* if s & _PSB_CE_TWOD_COMPLETE we have 2D done but
|
||||
we may as well poll even if we add that ! */
|
||||
handled = 1;
|
||||
}
|
||||
|
||||
PSB_WVDC32(vdc_stat, PSB_INT_IDENTITY_R);
|
||||
(void) PSB_RVDC32(PSB_INT_IDENTITY_R);
|
||||
DRM_READMEMORYBARRIER();
|
||||
|
||||
if (!handled)
|
||||
return IRQ_NONE;
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
void psb_irq_preinstall(struct drm_device *dev)
|
||||
{
|
||||
struct drm_psb_private *dev_priv =
|
||||
(struct drm_psb_private *) dev->dev_private;
|
||||
unsigned long irqflags;
|
||||
|
||||
spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
|
||||
|
||||
if (gma_power_is_on(dev))
|
||||
PSB_WVDC32(0xFFFFFFFF, PSB_HWSTAM);
|
||||
if (dev->vblank_enabled[0])
|
||||
dev_priv->vdc_irq_mask |= _PSB_PIPEA_EVENT_FLAG;
|
||||
if (dev->vblank_enabled[1])
|
||||
dev_priv->vdc_irq_mask |= _MDFLD_PIPEB_EVENT_FLAG;
|
||||
if (dev->vblank_enabled[2])
|
||||
dev_priv->vdc_irq_mask |= _MDFLD_PIPEC_EVENT_FLAG;
|
||||
|
||||
/*This register is safe even if display island is off*/
|
||||
PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R);
|
||||
spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
|
||||
}
|
||||
|
||||
int psb_irq_postinstall(struct drm_device *dev)
|
||||
{
|
||||
struct drm_psb_private *dev_priv =
|
||||
(struct drm_psb_private *) dev->dev_private;
|
||||
unsigned long irqflags;
|
||||
|
||||
spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
|
||||
|
||||
/* This register is safe even if display island is off */
|
||||
PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R);
|
||||
PSB_WVDC32(0xFFFFFFFF, PSB_HWSTAM);
|
||||
|
||||
if (dev->vblank_enabled[0])
|
||||
psb_enable_pipestat(dev_priv, 0, PIPE_VBLANK_INTERRUPT_ENABLE);
|
||||
else
|
||||
psb_disable_pipestat(dev_priv, 0, PIPE_VBLANK_INTERRUPT_ENABLE);
|
||||
|
||||
if (dev->vblank_enabled[1])
|
||||
psb_enable_pipestat(dev_priv, 1, PIPE_VBLANK_INTERRUPT_ENABLE);
|
||||
else
|
||||
psb_disable_pipestat(dev_priv, 1, PIPE_VBLANK_INTERRUPT_ENABLE);
|
||||
|
||||
if (dev->vblank_enabled[2])
|
||||
psb_enable_pipestat(dev_priv, 2, PIPE_VBLANK_INTERRUPT_ENABLE);
|
||||
else
|
||||
psb_disable_pipestat(dev_priv, 2, PIPE_VBLANK_INTERRUPT_ENABLE);
|
||||
|
||||
spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
|
||||
return 0;
|
||||
}
|
||||
|
||||
void psb_irq_uninstall(struct drm_device *dev)
|
||||
{
|
||||
struct drm_psb_private *dev_priv =
|
||||
(struct drm_psb_private *) dev->dev_private;
|
||||
unsigned long irqflags;
|
||||
|
||||
spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
|
||||
|
||||
PSB_WVDC32(0xFFFFFFFF, PSB_HWSTAM);
|
||||
|
||||
if (dev->vblank_enabled[0])
|
||||
psb_disable_pipestat(dev_priv, 0, PIPE_VBLANK_INTERRUPT_ENABLE);
|
||||
|
||||
if (dev->vblank_enabled[1])
|
||||
psb_disable_pipestat(dev_priv, 1, PIPE_VBLANK_INTERRUPT_ENABLE);
|
||||
|
||||
if (dev->vblank_enabled[2])
|
||||
psb_disable_pipestat(dev_priv, 2, PIPE_VBLANK_INTERRUPT_ENABLE);
|
||||
|
||||
dev_priv->vdc_irq_mask &= _PSB_IRQ_SGX_FLAG |
|
||||
_PSB_IRQ_MSVDX_FLAG |
|
||||
_LNC_IRQ_TOPAZ_FLAG;
|
||||
|
||||
/* These two registers are safe even if display island is off */
|
||||
PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R);
|
||||
PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R);
|
||||
|
||||
wmb();
|
||||
|
||||
/* This register is safe even if display island is off */
|
||||
PSB_WVDC32(PSB_RVDC32(PSB_INT_IDENTITY_R), PSB_INT_IDENTITY_R);
|
||||
spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
|
||||
}
|
||||
|
||||
void psb_irq_turn_on_dpst(struct drm_device *dev)
|
||||
{
|
||||
struct drm_psb_private *dev_priv =
|
||||
(struct drm_psb_private *) dev->dev_private;
|
||||
u32 hist_reg;
|
||||
u32 pwm_reg;
|
||||
|
||||
if (gma_power_begin(dev, false)) {
|
||||
PSB_WVDC32(1 << 31, HISTOGRAM_LOGIC_CONTROL);
|
||||
hist_reg = PSB_RVDC32(HISTOGRAM_LOGIC_CONTROL);
|
||||
PSB_WVDC32(1 << 31, HISTOGRAM_INT_CONTROL);
|
||||
hist_reg = PSB_RVDC32(HISTOGRAM_INT_CONTROL);
|
||||
|
||||
PSB_WVDC32(0x80010100, PWM_CONTROL_LOGIC);
|
||||
pwm_reg = PSB_RVDC32(PWM_CONTROL_LOGIC);
|
||||
PSB_WVDC32(pwm_reg | PWM_PHASEIN_ENABLE
|
||||
| PWM_PHASEIN_INT_ENABLE,
|
||||
PWM_CONTROL_LOGIC);
|
||||
pwm_reg = PSB_RVDC32(PWM_CONTROL_LOGIC);
|
||||
|
||||
psb_enable_pipestat(dev_priv, 0, PIPE_DPST_EVENT_ENABLE);
|
||||
|
||||
hist_reg = PSB_RVDC32(HISTOGRAM_INT_CONTROL);
|
||||
PSB_WVDC32(hist_reg | HISTOGRAM_INT_CTRL_CLEAR,
|
||||
HISTOGRAM_INT_CONTROL);
|
||||
pwm_reg = PSB_RVDC32(PWM_CONTROL_LOGIC);
|
||||
PSB_WVDC32(pwm_reg | 0x80010100 | PWM_PHASEIN_ENABLE,
|
||||
PWM_CONTROL_LOGIC);
|
||||
|
||||
gma_power_end(dev);
|
||||
}
|
||||
}
|
||||
|
||||
int psb_irq_enable_dpst(struct drm_device *dev)
|
||||
{
|
||||
struct drm_psb_private *dev_priv =
|
||||
(struct drm_psb_private *) dev->dev_private;
|
||||
unsigned long irqflags;
|
||||
|
||||
spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
|
||||
|
||||
/* enable DPST */
|
||||
mid_enable_pipe_event(dev_priv, 0);
|
||||
psb_irq_turn_on_dpst(dev);
|
||||
|
||||
spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
|
||||
return 0;
|
||||
}
|
||||
|
||||
void psb_irq_turn_off_dpst(struct drm_device *dev)
|
||||
{
|
||||
struct drm_psb_private *dev_priv =
|
||||
(struct drm_psb_private *) dev->dev_private;
|
||||
u32 hist_reg;
|
||||
u32 pwm_reg;
|
||||
|
||||
if (gma_power_begin(dev, false)) {
|
||||
PSB_WVDC32(0x00000000, HISTOGRAM_INT_CONTROL);
|
||||
hist_reg = PSB_RVDC32(HISTOGRAM_INT_CONTROL);
|
||||
|
||||
psb_disable_pipestat(dev_priv, 0, PIPE_DPST_EVENT_ENABLE);
|
||||
|
||||
pwm_reg = PSB_RVDC32(PWM_CONTROL_LOGIC);
|
||||
PSB_WVDC32(pwm_reg & !(PWM_PHASEIN_INT_ENABLE),
|
||||
PWM_CONTROL_LOGIC);
|
||||
pwm_reg = PSB_RVDC32(PWM_CONTROL_LOGIC);
|
||||
|
||||
gma_power_end(dev);
|
||||
}
|
||||
}
|
||||
|
||||
int psb_irq_disable_dpst(struct drm_device *dev)
|
||||
{
|
||||
struct drm_psb_private *dev_priv =
|
||||
(struct drm_psb_private *) dev->dev_private;
|
||||
unsigned long irqflags;
|
||||
|
||||
spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
|
||||
|
||||
mid_disable_pipe_event(dev_priv, 0);
|
||||
psb_irq_turn_off_dpst(dev);
|
||||
|
||||
spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef PSB_FIXME
|
||||
static int psb_vblank_do_wait(struct drm_device *dev,
|
||||
unsigned int *sequence, atomic_t *counter)
|
||||
{
|
||||
unsigned int cur_vblank;
|
||||
int ret = 0;
|
||||
DRM_WAIT_ON(ret, dev->vbl_queue, 3 * DRM_HZ,
|
||||
(((cur_vblank = atomic_read(counter))
|
||||
- *sequence) <= (1 << 23)));
|
||||
*sequence = cur_vblank;
|
||||
|
||||
return ret;
|
||||
}
|
||||
#endif
|
||||
|
||||
/*
|
||||
* It is used to enable VBLANK interrupt
|
||||
*/
|
||||
int psb_enable_vblank(struct drm_device *dev, int pipe)
|
||||
{
|
||||
struct drm_psb_private *dev_priv = dev->dev_private;
|
||||
unsigned long irqflags;
|
||||
uint32_t reg_val = 0;
|
||||
uint32_t pipeconf_reg = mid_pipeconf(pipe);
|
||||
|
||||
if (gma_power_begin(dev, false)) {
|
||||
reg_val = REG_READ(pipeconf_reg);
|
||||
gma_power_end(dev);
|
||||
}
|
||||
|
||||
if (!(reg_val & PIPEACONF_ENABLE))
|
||||
return -EINVAL;
|
||||
|
||||
spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
|
||||
|
||||
mid_enable_pipe_event(dev_priv, pipe);
|
||||
psb_enable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_ENABLE);
|
||||
|
||||
spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* It is used to disable VBLANK interrupt
|
||||
*/
|
||||
void psb_disable_vblank(struct drm_device *dev, int pipe)
|
||||
{
|
||||
struct drm_psb_private *dev_priv = dev->dev_private;
|
||||
unsigned long irqflags;
|
||||
|
||||
spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
|
||||
|
||||
mid_disable_pipe_event(dev_priv, pipe);
|
||||
psb_disable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_ENABLE);
|
||||
|
||||
spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
|
||||
}
|
||||
|
||||
/* Called from drm generic code, passed a 'crtc', which
|
||||
* we use as a pipe index
|
||||
*/
|
||||
u32 psb_get_vblank_counter(struct drm_device *dev, int pipe)
|
||||
{
|
||||
uint32_t high_frame = PIPEAFRAMEHIGH;
|
||||
uint32_t low_frame = PIPEAFRAMEPIXEL;
|
||||
uint32_t pipeconf_reg = PIPEACONF;
|
||||
uint32_t reg_val = 0;
|
||||
uint32_t high1 = 0, high2 = 0, low = 0, count = 0;
|
||||
|
||||
switch (pipe) {
|
||||
case 0:
|
||||
break;
|
||||
case 1:
|
||||
high_frame = PIPEBFRAMEHIGH;
|
||||
low_frame = PIPEBFRAMEPIXEL;
|
||||
pipeconf_reg = PIPEBCONF;
|
||||
break;
|
||||
case 2:
|
||||
high_frame = PIPECFRAMEHIGH;
|
||||
low_frame = PIPECFRAMEPIXEL;
|
||||
pipeconf_reg = PIPECCONF;
|
||||
break;
|
||||
default:
|
||||
dev_err(dev->dev, "%s, invalid pipe.\n", __func__);
|
||||
return 0;
|
||||
}
|
||||
|
||||
if (!gma_power_begin(dev, false))
|
||||
return 0;
|
||||
|
||||
reg_val = REG_READ(pipeconf_reg);
|
||||
|
||||
if (!(reg_val & PIPEACONF_ENABLE)) {
|
||||
dev_err(dev->dev, "trying to get vblank count for disabled pipe %d\n",
|
||||
pipe);
|
||||
goto psb_get_vblank_counter_exit;
|
||||
}
|
||||
|
||||
/*
|
||||
* High & low register fields aren't synchronized, so make sure
|
||||
* we get a low value that's stable across two reads of the high
|
||||
* register.
|
||||
*/
|
||||
do {
|
||||
high1 = ((REG_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
|
||||
PIPE_FRAME_HIGH_SHIFT);
|
||||
low = ((REG_READ(low_frame) & PIPE_FRAME_LOW_MASK) >>
|
||||
PIPE_FRAME_LOW_SHIFT);
|
||||
high2 = ((REG_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
|
||||
PIPE_FRAME_HIGH_SHIFT);
|
||||
} while (high1 != high2);
|
||||
|
||||
count = (high1 << 8) | low;
|
||||
|
||||
psb_get_vblank_counter_exit:
|
||||
|
||||
gma_power_end(dev);
|
||||
|
||||
return count;
|
||||
}
|
||||
|
||||
45
drivers/gpu/drm/gma500/psb_irq.h
Normal file
45
drivers/gpu/drm/gma500/psb_irq.h
Normal file
@ -0,0 +1,45 @@
|
||||
/**************************************************************************
|
||||
* Copyright (c) 2009-2011, Intel Corporation.
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*
|
||||
* Authors:
|
||||
* Benjamin Defnet <benjamin.r.defnet@intel.com>
|
||||
* Rajesh Poornachandran <rajesh.poornachandran@intel.com>
|
||||
*
|
||||
**************************************************************************/
|
||||
|
||||
#ifndef _SYSIRQ_H_
|
||||
#define _SYSIRQ_H_
|
||||
|
||||
#include <drm/drmP.h>
|
||||
|
||||
bool sysirq_init(struct drm_device *dev);
|
||||
void sysirq_uninit(struct drm_device *dev);
|
||||
|
||||
void psb_irq_preinstall(struct drm_device *dev);
|
||||
int psb_irq_postinstall(struct drm_device *dev);
|
||||
void psb_irq_uninstall(struct drm_device *dev);
|
||||
irqreturn_t psb_irq_handler(DRM_IRQ_ARGS);
|
||||
|
||||
int psb_irq_enable_dpst(struct drm_device *dev);
|
||||
int psb_irq_disable_dpst(struct drm_device *dev);
|
||||
void psb_irq_turn_on_dpst(struct drm_device *dev);
|
||||
void psb_irq_turn_off_dpst(struct drm_device *dev);
|
||||
int psb_enable_vblank(struct drm_device *dev, int pipe);
|
||||
void psb_disable_vblank(struct drm_device *dev, int pipe);
|
||||
u32 psb_get_vblank_counter(struct drm_device *dev, int pipe);
|
||||
|
||||
#endif /* _SYSIRQ_H_ */
|
||||
582
drivers/gpu/drm/gma500/psb_reg.h
Normal file
582
drivers/gpu/drm/gma500/psb_reg.h
Normal file
@ -0,0 +1,582 @@
|
||||
/**************************************************************************
|
||||
*
|
||||
* Copyright (c) (2005-2007) Imagination Technologies Limited.
|
||||
* Copyright (c) 2007, Intel Corporation.
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA..
|
||||
*
|
||||
**************************************************************************/
|
||||
|
||||
#ifndef _PSB_REG_H_
|
||||
#define _PSB_REG_H_
|
||||
|
||||
#define PSB_CR_CLKGATECTL 0x0000
|
||||
#define _PSB_C_CLKGATECTL_AUTO_MAN_REG (1 << 24)
|
||||
#define _PSB_C_CLKGATECTL_USE_CLKG_SHIFT (20)
|
||||
#define _PSB_C_CLKGATECTL_USE_CLKG_MASK (0x3 << 20)
|
||||
#define _PSB_C_CLKGATECTL_DPM_CLKG_SHIFT (16)
|
||||
#define _PSB_C_CLKGATECTL_DPM_CLKG_MASK (0x3 << 16)
|
||||
#define _PSB_C_CLKGATECTL_TA_CLKG_SHIFT (12)
|
||||
#define _PSB_C_CLKGATECTL_TA_CLKG_MASK (0x3 << 12)
|
||||
#define _PSB_C_CLKGATECTL_TSP_CLKG_SHIFT (8)
|
||||
#define _PSB_C_CLKGATECTL_TSP_CLKG_MASK (0x3 << 8)
|
||||
#define _PSB_C_CLKGATECTL_ISP_CLKG_SHIFT (4)
|
||||
#define _PSB_C_CLKGATECTL_ISP_CLKG_MASK (0x3 << 4)
|
||||
#define _PSB_C_CLKGATECTL_2D_CLKG_SHIFT (0)
|
||||
#define _PSB_C_CLKGATECTL_2D_CLKG_MASK (0x3 << 0)
|
||||
#define _PSB_C_CLKGATECTL_CLKG_ENABLED (0)
|
||||
#define _PSB_C_CLKGATECTL_CLKG_DISABLED (1)
|
||||
#define _PSB_C_CLKGATECTL_CLKG_AUTO (2)
|
||||
|
||||
#define PSB_CR_CORE_ID 0x0010
|
||||
#define _PSB_CC_ID_ID_SHIFT (16)
|
||||
#define _PSB_CC_ID_ID_MASK (0xFFFF << 16)
|
||||
#define _PSB_CC_ID_CONFIG_SHIFT (0)
|
||||
#define _PSB_CC_ID_CONFIG_MASK (0xFFFF << 0)
|
||||
|
||||
#define PSB_CR_CORE_REVISION 0x0014
|
||||
#define _PSB_CC_REVISION_DESIGNER_SHIFT (24)
|
||||
#define _PSB_CC_REVISION_DESIGNER_MASK (0xFF << 24)
|
||||
#define _PSB_CC_REVISION_MAJOR_SHIFT (16)
|
||||
#define _PSB_CC_REVISION_MAJOR_MASK (0xFF << 16)
|
||||
#define _PSB_CC_REVISION_MINOR_SHIFT (8)
|
||||
#define _PSB_CC_REVISION_MINOR_MASK (0xFF << 8)
|
||||
#define _PSB_CC_REVISION_MAINTENANCE_SHIFT (0)
|
||||
#define _PSB_CC_REVISION_MAINTENANCE_MASK (0xFF << 0)
|
||||
|
||||
#define PSB_CR_DESIGNER_REV_FIELD1 0x0018
|
||||
|
||||
#define PSB_CR_SOFT_RESET 0x0080
|
||||
#define _PSB_CS_RESET_TSP_RESET (1 << 6)
|
||||
#define _PSB_CS_RESET_ISP_RESET (1 << 5)
|
||||
#define _PSB_CS_RESET_USE_RESET (1 << 4)
|
||||
#define _PSB_CS_RESET_TA_RESET (1 << 3)
|
||||
#define _PSB_CS_RESET_DPM_RESET (1 << 2)
|
||||
#define _PSB_CS_RESET_TWOD_RESET (1 << 1)
|
||||
#define _PSB_CS_RESET_BIF_RESET (1 << 0)
|
||||
|
||||
#define PSB_CR_DESIGNER_REV_FIELD2 0x001C
|
||||
|
||||
#define PSB_CR_EVENT_HOST_ENABLE2 0x0110
|
||||
|
||||
#define PSB_CR_EVENT_STATUS2 0x0118
|
||||
|
||||
#define PSB_CR_EVENT_HOST_CLEAR2 0x0114
|
||||
#define _PSB_CE2_BIF_REQUESTER_FAULT (1 << 4)
|
||||
|
||||
#define PSB_CR_EVENT_STATUS 0x012C
|
||||
|
||||
#define PSB_CR_EVENT_HOST_ENABLE 0x0130
|
||||
|
||||
#define PSB_CR_EVENT_HOST_CLEAR 0x0134
|
||||
#define _PSB_CE_MASTER_INTERRUPT (1 << 31)
|
||||
#define _PSB_CE_TA_DPM_FAULT (1 << 28)
|
||||
#define _PSB_CE_TWOD_COMPLETE (1 << 27)
|
||||
#define _PSB_CE_DPM_OUT_OF_MEMORY_ZLS (1 << 25)
|
||||
#define _PSB_CE_DPM_TA_MEM_FREE (1 << 24)
|
||||
#define _PSB_CE_PIXELBE_END_RENDER (1 << 18)
|
||||
#define _PSB_CE_SW_EVENT (1 << 14)
|
||||
#define _PSB_CE_TA_FINISHED (1 << 13)
|
||||
#define _PSB_CE_TA_TERMINATE (1 << 12)
|
||||
#define _PSB_CE_DPM_REACHED_MEM_THRESH (1 << 3)
|
||||
#define _PSB_CE_DPM_OUT_OF_MEMORY_GBL (1 << 2)
|
||||
#define _PSB_CE_DPM_OUT_OF_MEMORY_MT (1 << 1)
|
||||
#define _PSB_CE_DPM_3D_MEM_FREE (1 << 0)
|
||||
|
||||
|
||||
#define PSB_USE_OFFSET_MASK 0x0007FFFF
|
||||
#define PSB_USE_OFFSET_SIZE (PSB_USE_OFFSET_MASK + 1)
|
||||
#define PSB_CR_USE_CODE_BASE0 0x0A0C
|
||||
#define PSB_CR_USE_CODE_BASE1 0x0A10
|
||||
#define PSB_CR_USE_CODE_BASE2 0x0A14
|
||||
#define PSB_CR_USE_CODE_BASE3 0x0A18
|
||||
#define PSB_CR_USE_CODE_BASE4 0x0A1C
|
||||
#define PSB_CR_USE_CODE_BASE5 0x0A20
|
||||
#define PSB_CR_USE_CODE_BASE6 0x0A24
|
||||
#define PSB_CR_USE_CODE_BASE7 0x0A28
|
||||
#define PSB_CR_USE_CODE_BASE8 0x0A2C
|
||||
#define PSB_CR_USE_CODE_BASE9 0x0A30
|
||||
#define PSB_CR_USE_CODE_BASE10 0x0A34
|
||||
#define PSB_CR_USE_CODE_BASE11 0x0A38
|
||||
#define PSB_CR_USE_CODE_BASE12 0x0A3C
|
||||
#define PSB_CR_USE_CODE_BASE13 0x0A40
|
||||
#define PSB_CR_USE_CODE_BASE14 0x0A44
|
||||
#define PSB_CR_USE_CODE_BASE15 0x0A48
|
||||
#define PSB_CR_USE_CODE_BASE(_i) (0x0A0C + ((_i) << 2))
|
||||
#define _PSB_CUC_BASE_DM_SHIFT (25)
|
||||
#define _PSB_CUC_BASE_DM_MASK (0x3 << 25)
|
||||
#define _PSB_CUC_BASE_ADDR_SHIFT (0) /* 1024-bit aligned address? */
|
||||
#define _PSB_CUC_BASE_ADDR_ALIGNSHIFT (7)
|
||||
#define _PSB_CUC_BASE_ADDR_MASK (0x1FFFFFF << 0)
|
||||
#define _PSB_CUC_DM_VERTEX (0)
|
||||
#define _PSB_CUC_DM_PIXEL (1)
|
||||
#define _PSB_CUC_DM_RESERVED (2)
|
||||
#define _PSB_CUC_DM_EDM (3)
|
||||
|
||||
#define PSB_CR_PDS_EXEC_BASE 0x0AB8
|
||||
#define _PSB_CR_PDS_EXEC_BASE_ADDR_SHIFT (20) /* 1MB aligned address */
|
||||
#define _PSB_CR_PDS_EXEC_BASE_ADDR_ALIGNSHIFT (20)
|
||||
|
||||
#define PSB_CR_EVENT_KICKER 0x0AC4
|
||||
#define _PSB_CE_KICKER_ADDRESS_SHIFT (4) /* 128-bit aligned address */
|
||||
|
||||
#define PSB_CR_EVENT_KICK 0x0AC8
|
||||
#define _PSB_CE_KICK_NOW (1 << 0)
|
||||
|
||||
#define PSB_CR_BIF_DIR_LIST_BASE1 0x0C38
|
||||
|
||||
#define PSB_CR_BIF_CTRL 0x0C00
|
||||
#define _PSB_CB_CTRL_CLEAR_FAULT (1 << 4)
|
||||
#define _PSB_CB_CTRL_INVALDC (1 << 3)
|
||||
#define _PSB_CB_CTRL_FLUSH (1 << 2)
|
||||
|
||||
#define PSB_CR_BIF_INT_STAT 0x0C04
|
||||
|
||||
#define PSB_CR_BIF_FAULT 0x0C08
|
||||
#define _PSB_CBI_STAT_PF_N_RW (1 << 14)
|
||||
#define _PSB_CBI_STAT_FAULT_SHIFT (0)
|
||||
#define _PSB_CBI_STAT_FAULT_MASK (0x3FFF << 0)
|
||||
#define _PSB_CBI_STAT_FAULT_CACHE (1 << 1)
|
||||
#define _PSB_CBI_STAT_FAULT_TA (1 << 2)
|
||||
#define _PSB_CBI_STAT_FAULT_VDM (1 << 3)
|
||||
#define _PSB_CBI_STAT_FAULT_2D (1 << 4)
|
||||
#define _PSB_CBI_STAT_FAULT_PBE (1 << 5)
|
||||
#define _PSB_CBI_STAT_FAULT_TSP (1 << 6)
|
||||
#define _PSB_CBI_STAT_FAULT_ISP (1 << 7)
|
||||
#define _PSB_CBI_STAT_FAULT_USSEPDS (1 << 8)
|
||||
#define _PSB_CBI_STAT_FAULT_HOST (1 << 9)
|
||||
|
||||
#define PSB_CR_BIF_BANK0 0x0C78
|
||||
#define PSB_CR_BIF_BANK1 0x0C7C
|
||||
#define PSB_CR_BIF_DIR_LIST_BASE0 0x0C84
|
||||
#define PSB_CR_BIF_TWOD_REQ_BASE 0x0C88
|
||||
#define PSB_CR_BIF_3D_REQ_BASE 0x0CAC
|
||||
|
||||
#define PSB_CR_2D_SOCIF 0x0E18
|
||||
#define _PSB_C2_SOCIF_FREESPACE_SHIFT (0)
|
||||
#define _PSB_C2_SOCIF_FREESPACE_MASK (0xFF << 0)
|
||||
#define _PSB_C2_SOCIF_EMPTY (0x80 << 0)
|
||||
|
||||
#define PSB_CR_2D_BLIT_STATUS 0x0E04
|
||||
#define _PSB_C2B_STATUS_BUSY (1 << 24)
|
||||
#define _PSB_C2B_STATUS_COMPLETE_SHIFT (0)
|
||||
#define _PSB_C2B_STATUS_COMPLETE_MASK (0xFFFFFF << 0)
|
||||
|
||||
/*
|
||||
* 2D defs.
|
||||
*/
|
||||
|
||||
/*
|
||||
* 2D Slave Port Data : Block Header's Object Type
|
||||
*/
|
||||
|
||||
#define PSB_2D_CLIP_BH (0x00000000)
|
||||
#define PSB_2D_PAT_BH (0x10000000)
|
||||
#define PSB_2D_CTRL_BH (0x20000000)
|
||||
#define PSB_2D_SRC_OFF_BH (0x30000000)
|
||||
#define PSB_2D_MASK_OFF_BH (0x40000000)
|
||||
#define PSB_2D_RESERVED1_BH (0x50000000)
|
||||
#define PSB_2D_RESERVED2_BH (0x60000000)
|
||||
#define PSB_2D_FENCE_BH (0x70000000)
|
||||
#define PSB_2D_BLIT_BH (0x80000000)
|
||||
#define PSB_2D_SRC_SURF_BH (0x90000000)
|
||||
#define PSB_2D_DST_SURF_BH (0xA0000000)
|
||||
#define PSB_2D_PAT_SURF_BH (0xB0000000)
|
||||
#define PSB_2D_SRC_PAL_BH (0xC0000000)
|
||||
#define PSB_2D_PAT_PAL_BH (0xD0000000)
|
||||
#define PSB_2D_MASK_SURF_BH (0xE0000000)
|
||||
#define PSB_2D_FLUSH_BH (0xF0000000)
|
||||
|
||||
/*
|
||||
* Clip Definition block (PSB_2D_CLIP_BH)
|
||||
*/
|
||||
#define PSB_2D_CLIPCOUNT_MAX (1)
|
||||
#define PSB_2D_CLIPCOUNT_MASK (0x00000000)
|
||||
#define PSB_2D_CLIPCOUNT_CLRMASK (0xFFFFFFFF)
|
||||
#define PSB_2D_CLIPCOUNT_SHIFT (0)
|
||||
/* clip rectangle min & max */
|
||||
#define PSB_2D_CLIP_XMAX_MASK (0x00FFF000)
|
||||
#define PSB_2D_CLIP_XMAX_CLRMASK (0xFF000FFF)
|
||||
#define PSB_2D_CLIP_XMAX_SHIFT (12)
|
||||
#define PSB_2D_CLIP_XMIN_MASK (0x00000FFF)
|
||||
#define PSB_2D_CLIP_XMIN_CLRMASK (0x00FFF000)
|
||||
#define PSB_2D_CLIP_XMIN_SHIFT (0)
|
||||
/* clip rectangle offset */
|
||||
#define PSB_2D_CLIP_YMAX_MASK (0x00FFF000)
|
||||
#define PSB_2D_CLIP_YMAX_CLRMASK (0xFF000FFF)
|
||||
#define PSB_2D_CLIP_YMAX_SHIFT (12)
|
||||
#define PSB_2D_CLIP_YMIN_MASK (0x00000FFF)
|
||||
#define PSB_2D_CLIP_YMIN_CLRMASK (0x00FFF000)
|
||||
#define PSB_2D_CLIP_YMIN_SHIFT (0)
|
||||
|
||||
/*
|
||||
* Pattern Control (PSB_2D_PAT_BH)
|
||||
*/
|
||||
#define PSB_2D_PAT_HEIGHT_MASK (0x0000001F)
|
||||
#define PSB_2D_PAT_HEIGHT_SHIFT (0)
|
||||
#define PSB_2D_PAT_WIDTH_MASK (0x000003E0)
|
||||
#define PSB_2D_PAT_WIDTH_SHIFT (5)
|
||||
#define PSB_2D_PAT_YSTART_MASK (0x00007C00)
|
||||
#define PSB_2D_PAT_YSTART_SHIFT (10)
|
||||
#define PSB_2D_PAT_XSTART_MASK (0x000F8000)
|
||||
#define PSB_2D_PAT_XSTART_SHIFT (15)
|
||||
|
||||
/*
|
||||
* 2D Control block (PSB_2D_CTRL_BH)
|
||||
*/
|
||||
/* Present Flags */
|
||||
#define PSB_2D_SRCCK_CTRL (0x00000001)
|
||||
#define PSB_2D_DSTCK_CTRL (0x00000002)
|
||||
#define PSB_2D_ALPHA_CTRL (0x00000004)
|
||||
/* Colour Key Colour (SRC/DST)*/
|
||||
#define PSB_2D_CK_COL_MASK (0xFFFFFFFF)
|
||||
#define PSB_2D_CK_COL_CLRMASK (0x00000000)
|
||||
#define PSB_2D_CK_COL_SHIFT (0)
|
||||
/* Colour Key Mask (SRC/DST)*/
|
||||
#define PSB_2D_CK_MASK_MASK (0xFFFFFFFF)
|
||||
#define PSB_2D_CK_MASK_CLRMASK (0x00000000)
|
||||
#define PSB_2D_CK_MASK_SHIFT (0)
|
||||
/* Alpha Control (Alpha/RGB)*/
|
||||
#define PSB_2D_GBLALPHA_MASK (0x000FF000)
|
||||
#define PSB_2D_GBLALPHA_CLRMASK (0xFFF00FFF)
|
||||
#define PSB_2D_GBLALPHA_SHIFT (12)
|
||||
#define PSB_2D_SRCALPHA_OP_MASK (0x00700000)
|
||||
#define PSB_2D_SRCALPHA_OP_CLRMASK (0xFF8FFFFF)
|
||||
#define PSB_2D_SRCALPHA_OP_SHIFT (20)
|
||||
#define PSB_2D_SRCALPHA_OP_ONE (0x00000000)
|
||||
#define PSB_2D_SRCALPHA_OP_SRC (0x00100000)
|
||||
#define PSB_2D_SRCALPHA_OP_DST (0x00200000)
|
||||
#define PSB_2D_SRCALPHA_OP_SG (0x00300000)
|
||||
#define PSB_2D_SRCALPHA_OP_DG (0x00400000)
|
||||
#define PSB_2D_SRCALPHA_OP_GBL (0x00500000)
|
||||
#define PSB_2D_SRCALPHA_OP_ZERO (0x00600000)
|
||||
#define PSB_2D_SRCALPHA_INVERT (0x00800000)
|
||||
#define PSB_2D_SRCALPHA_INVERT_CLR (0xFF7FFFFF)
|
||||
#define PSB_2D_DSTALPHA_OP_MASK (0x07000000)
|
||||
#define PSB_2D_DSTALPHA_OP_CLRMASK (0xF8FFFFFF)
|
||||
#define PSB_2D_DSTALPHA_OP_SHIFT (24)
|
||||
#define PSB_2D_DSTALPHA_OP_ONE (0x00000000)
|
||||
#define PSB_2D_DSTALPHA_OP_SRC (0x01000000)
|
||||
#define PSB_2D_DSTALPHA_OP_DST (0x02000000)
|
||||
#define PSB_2D_DSTALPHA_OP_SG (0x03000000)
|
||||
#define PSB_2D_DSTALPHA_OP_DG (0x04000000)
|
||||
#define PSB_2D_DSTALPHA_OP_GBL (0x05000000)
|
||||
#define PSB_2D_DSTALPHA_OP_ZERO (0x06000000)
|
||||
#define PSB_2D_DSTALPHA_INVERT (0x08000000)
|
||||
#define PSB_2D_DSTALPHA_INVERT_CLR (0xF7FFFFFF)
|
||||
|
||||
#define PSB_2D_PRE_MULTIPLICATION_ENABLE (0x10000000)
|
||||
#define PSB_2D_PRE_MULTIPLICATION_CLRMASK (0xEFFFFFFF)
|
||||
#define PSB_2D_ZERO_SOURCE_ALPHA_ENABLE (0x20000000)
|
||||
#define PSB_2D_ZERO_SOURCE_ALPHA_CLRMASK (0xDFFFFFFF)
|
||||
|
||||
/*
|
||||
*Source Offset (PSB_2D_SRC_OFF_BH)
|
||||
*/
|
||||
#define PSB_2D_SRCOFF_XSTART_MASK ((0x00000FFF) << 12)
|
||||
#define PSB_2D_SRCOFF_XSTART_SHIFT (12)
|
||||
#define PSB_2D_SRCOFF_YSTART_MASK (0x00000FFF)
|
||||
#define PSB_2D_SRCOFF_YSTART_SHIFT (0)
|
||||
|
||||
/*
|
||||
* Mask Offset (PSB_2D_MASK_OFF_BH)
|
||||
*/
|
||||
#define PSB_2D_MASKOFF_XSTART_MASK ((0x00000FFF) << 12)
|
||||
#define PSB_2D_MASKOFF_XSTART_SHIFT (12)
|
||||
#define PSB_2D_MASKOFF_YSTART_MASK (0x00000FFF)
|
||||
#define PSB_2D_MASKOFF_YSTART_SHIFT (0)
|
||||
|
||||
/*
|
||||
* 2D Fence (see PSB_2D_FENCE_BH): bits 0:27 are ignored
|
||||
*/
|
||||
|
||||
/*
|
||||
*Blit Rectangle (PSB_2D_BLIT_BH)
|
||||
*/
|
||||
|
||||
#define PSB_2D_ROT_MASK (3 << 25)
|
||||
#define PSB_2D_ROT_CLRMASK (~PSB_2D_ROT_MASK)
|
||||
#define PSB_2D_ROT_NONE (0 << 25)
|
||||
#define PSB_2D_ROT_90DEGS (1 << 25)
|
||||
#define PSB_2D_ROT_180DEGS (2 << 25)
|
||||
#define PSB_2D_ROT_270DEGS (3 << 25)
|
||||
|
||||
#define PSB_2D_COPYORDER_MASK (3 << 23)
|
||||
#define PSB_2D_COPYORDER_CLRMASK (~PSB_2D_COPYORDER_MASK)
|
||||
#define PSB_2D_COPYORDER_TL2BR (0 << 23)
|
||||
#define PSB_2D_COPYORDER_BR2TL (1 << 23)
|
||||
#define PSB_2D_COPYORDER_TR2BL (2 << 23)
|
||||
#define PSB_2D_COPYORDER_BL2TR (3 << 23)
|
||||
|
||||
#define PSB_2D_DSTCK_CLRMASK (0xFF9FFFFF)
|
||||
#define PSB_2D_DSTCK_DISABLE (0x00000000)
|
||||
#define PSB_2D_DSTCK_PASS (0x00200000)
|
||||
#define PSB_2D_DSTCK_REJECT (0x00400000)
|
||||
|
||||
#define PSB_2D_SRCCK_CLRMASK (0xFFE7FFFF)
|
||||
#define PSB_2D_SRCCK_DISABLE (0x00000000)
|
||||
#define PSB_2D_SRCCK_PASS (0x00080000)
|
||||
#define PSB_2D_SRCCK_REJECT (0x00100000)
|
||||
|
||||
#define PSB_2D_CLIP_ENABLE (0x00040000)
|
||||
|
||||
#define PSB_2D_ALPHA_ENABLE (0x00020000)
|
||||
|
||||
#define PSB_2D_PAT_CLRMASK (0xFFFEFFFF)
|
||||
#define PSB_2D_PAT_MASK (0x00010000)
|
||||
#define PSB_2D_USE_PAT (0x00010000)
|
||||
#define PSB_2D_USE_FILL (0x00000000)
|
||||
/*
|
||||
* Tungsten Graphics note on rop codes: If rop A and rop B are
|
||||
* identical, the mask surface will not be read and need not be
|
||||
* set up.
|
||||
*/
|
||||
|
||||
#define PSB_2D_ROP3B_MASK (0x0000FF00)
|
||||
#define PSB_2D_ROP3B_CLRMASK (0xFFFF00FF)
|
||||
#define PSB_2D_ROP3B_SHIFT (8)
|
||||
/* rop code A */
|
||||
#define PSB_2D_ROP3A_MASK (0x000000FF)
|
||||
#define PSB_2D_ROP3A_CLRMASK (0xFFFFFF00)
|
||||
#define PSB_2D_ROP3A_SHIFT (0)
|
||||
|
||||
#define PSB_2D_ROP4_MASK (0x0000FFFF)
|
||||
/*
|
||||
* DWORD0: (Only pass if Pattern control == Use Fill Colour)
|
||||
* Fill Colour RGBA8888
|
||||
*/
|
||||
#define PSB_2D_FILLCOLOUR_MASK (0xFFFFFFFF)
|
||||
#define PSB_2D_FILLCOLOUR_SHIFT (0)
|
||||
/*
|
||||
* DWORD1: (Always Present)
|
||||
* X Start (Dest)
|
||||
* Y Start (Dest)
|
||||
*/
|
||||
#define PSB_2D_DST_XSTART_MASK (0x00FFF000)
|
||||
#define PSB_2D_DST_XSTART_CLRMASK (0xFF000FFF)
|
||||
#define PSB_2D_DST_XSTART_SHIFT (12)
|
||||
#define PSB_2D_DST_YSTART_MASK (0x00000FFF)
|
||||
#define PSB_2D_DST_YSTART_CLRMASK (0xFFFFF000)
|
||||
#define PSB_2D_DST_YSTART_SHIFT (0)
|
||||
/*
|
||||
* DWORD2: (Always Present)
|
||||
* X Size (Dest)
|
||||
* Y Size (Dest)
|
||||
*/
|
||||
#define PSB_2D_DST_XSIZE_MASK (0x00FFF000)
|
||||
#define PSB_2D_DST_XSIZE_CLRMASK (0xFF000FFF)
|
||||
#define PSB_2D_DST_XSIZE_SHIFT (12)
|
||||
#define PSB_2D_DST_YSIZE_MASK (0x00000FFF)
|
||||
#define PSB_2D_DST_YSIZE_CLRMASK (0xFFFFF000)
|
||||
#define PSB_2D_DST_YSIZE_SHIFT (0)
|
||||
|
||||
/*
|
||||
* Source Surface (PSB_2D_SRC_SURF_BH)
|
||||
*/
|
||||
/*
|
||||
* WORD 0
|
||||
*/
|
||||
|
||||
#define PSB_2D_SRC_FORMAT_MASK (0x00078000)
|
||||
#define PSB_2D_SRC_1_PAL (0x00000000)
|
||||
#define PSB_2D_SRC_2_PAL (0x00008000)
|
||||
#define PSB_2D_SRC_4_PAL (0x00010000)
|
||||
#define PSB_2D_SRC_8_PAL (0x00018000)
|
||||
#define PSB_2D_SRC_8_ALPHA (0x00020000)
|
||||
#define PSB_2D_SRC_4_ALPHA (0x00028000)
|
||||
#define PSB_2D_SRC_332RGB (0x00030000)
|
||||
#define PSB_2D_SRC_4444ARGB (0x00038000)
|
||||
#define PSB_2D_SRC_555RGB (0x00040000)
|
||||
#define PSB_2D_SRC_1555ARGB (0x00048000)
|
||||
#define PSB_2D_SRC_565RGB (0x00050000)
|
||||
#define PSB_2D_SRC_0888ARGB (0x00058000)
|
||||
#define PSB_2D_SRC_8888ARGB (0x00060000)
|
||||
#define PSB_2D_SRC_8888UYVY (0x00068000)
|
||||
#define PSB_2D_SRC_RESERVED (0x00070000)
|
||||
#define PSB_2D_SRC_1555ARGB_LOOKUP (0x00078000)
|
||||
|
||||
|
||||
#define PSB_2D_SRC_STRIDE_MASK (0x00007FFF)
|
||||
#define PSB_2D_SRC_STRIDE_CLRMASK (0xFFFF8000)
|
||||
#define PSB_2D_SRC_STRIDE_SHIFT (0)
|
||||
/*
|
||||
* WORD 1 - Base Address
|
||||
*/
|
||||
#define PSB_2D_SRC_ADDR_MASK (0x0FFFFFFC)
|
||||
#define PSB_2D_SRC_ADDR_CLRMASK (0x00000003)
|
||||
#define PSB_2D_SRC_ADDR_SHIFT (2)
|
||||
#define PSB_2D_SRC_ADDR_ALIGNSHIFT (2)
|
||||
|
||||
/*
|
||||
* Pattern Surface (PSB_2D_PAT_SURF_BH)
|
||||
*/
|
||||
/*
|
||||
* WORD 0
|
||||
*/
|
||||
|
||||
#define PSB_2D_PAT_FORMAT_MASK (0x00078000)
|
||||
#define PSB_2D_PAT_1_PAL (0x00000000)
|
||||
#define PSB_2D_PAT_2_PAL (0x00008000)
|
||||
#define PSB_2D_PAT_4_PAL (0x00010000)
|
||||
#define PSB_2D_PAT_8_PAL (0x00018000)
|
||||
#define PSB_2D_PAT_8_ALPHA (0x00020000)
|
||||
#define PSB_2D_PAT_4_ALPHA (0x00028000)
|
||||
#define PSB_2D_PAT_332RGB (0x00030000)
|
||||
#define PSB_2D_PAT_4444ARGB (0x00038000)
|
||||
#define PSB_2D_PAT_555RGB (0x00040000)
|
||||
#define PSB_2D_PAT_1555ARGB (0x00048000)
|
||||
#define PSB_2D_PAT_565RGB (0x00050000)
|
||||
#define PSB_2D_PAT_0888ARGB (0x00058000)
|
||||
#define PSB_2D_PAT_8888ARGB (0x00060000)
|
||||
|
||||
#define PSB_2D_PAT_STRIDE_MASK (0x00007FFF)
|
||||
#define PSB_2D_PAT_STRIDE_CLRMASK (0xFFFF8000)
|
||||
#define PSB_2D_PAT_STRIDE_SHIFT (0)
|
||||
/*
|
||||
* WORD 1 - Base Address
|
||||
*/
|
||||
#define PSB_2D_PAT_ADDR_MASK (0x0FFFFFFC)
|
||||
#define PSB_2D_PAT_ADDR_CLRMASK (0x00000003)
|
||||
#define PSB_2D_PAT_ADDR_SHIFT (2)
|
||||
#define PSB_2D_PAT_ADDR_ALIGNSHIFT (2)
|
||||
|
||||
/*
|
||||
* Destination Surface (PSB_2D_DST_SURF_BH)
|
||||
*/
|
||||
/*
|
||||
* WORD 0
|
||||
*/
|
||||
|
||||
#define PSB_2D_DST_FORMAT_MASK (0x00078000)
|
||||
#define PSB_2D_DST_332RGB (0x00030000)
|
||||
#define PSB_2D_DST_4444ARGB (0x00038000)
|
||||
#define PSB_2D_DST_555RGB (0x00040000)
|
||||
#define PSB_2D_DST_1555ARGB (0x00048000)
|
||||
#define PSB_2D_DST_565RGB (0x00050000)
|
||||
#define PSB_2D_DST_0888ARGB (0x00058000)
|
||||
#define PSB_2D_DST_8888ARGB (0x00060000)
|
||||
#define PSB_2D_DST_8888AYUV (0x00070000)
|
||||
|
||||
#define PSB_2D_DST_STRIDE_MASK (0x00007FFF)
|
||||
#define PSB_2D_DST_STRIDE_CLRMASK (0xFFFF8000)
|
||||
#define PSB_2D_DST_STRIDE_SHIFT (0)
|
||||
/*
|
||||
* WORD 1 - Base Address
|
||||
*/
|
||||
#define PSB_2D_DST_ADDR_MASK (0x0FFFFFFC)
|
||||
#define PSB_2D_DST_ADDR_CLRMASK (0x00000003)
|
||||
#define PSB_2D_DST_ADDR_SHIFT (2)
|
||||
#define PSB_2D_DST_ADDR_ALIGNSHIFT (2)
|
||||
|
||||
/*
|
||||
* Mask Surface (PSB_2D_MASK_SURF_BH)
|
||||
*/
|
||||
/*
|
||||
* WORD 0
|
||||
*/
|
||||
#define PSB_2D_MASK_STRIDE_MASK (0x00007FFF)
|
||||
#define PSB_2D_MASK_STRIDE_CLRMASK (0xFFFF8000)
|
||||
#define PSB_2D_MASK_STRIDE_SHIFT (0)
|
||||
/*
|
||||
* WORD 1 - Base Address
|
||||
*/
|
||||
#define PSB_2D_MASK_ADDR_MASK (0x0FFFFFFC)
|
||||
#define PSB_2D_MASK_ADDR_CLRMASK (0x00000003)
|
||||
#define PSB_2D_MASK_ADDR_SHIFT (2)
|
||||
#define PSB_2D_MASK_ADDR_ALIGNSHIFT (2)
|
||||
|
||||
/*
|
||||
* Source Palette (PSB_2D_SRC_PAL_BH)
|
||||
*/
|
||||
|
||||
#define PSB_2D_SRCPAL_ADDR_SHIFT (0)
|
||||
#define PSB_2D_SRCPAL_ADDR_CLRMASK (0xF0000007)
|
||||
#define PSB_2D_SRCPAL_ADDR_MASK (0x0FFFFFF8)
|
||||
#define PSB_2D_SRCPAL_BYTEALIGN (1024)
|
||||
|
||||
/*
|
||||
* Pattern Palette (PSB_2D_PAT_PAL_BH)
|
||||
*/
|
||||
|
||||
#define PSB_2D_PATPAL_ADDR_SHIFT (0)
|
||||
#define PSB_2D_PATPAL_ADDR_CLRMASK (0xF0000007)
|
||||
#define PSB_2D_PATPAL_ADDR_MASK (0x0FFFFFF8)
|
||||
#define PSB_2D_PATPAL_BYTEALIGN (1024)
|
||||
|
||||
/*
|
||||
* Rop3 Codes (2 LS bytes)
|
||||
*/
|
||||
|
||||
#define PSB_2D_ROP3_SRCCOPY (0xCCCC)
|
||||
#define PSB_2D_ROP3_PATCOPY (0xF0F0)
|
||||
#define PSB_2D_ROP3_WHITENESS (0xFFFF)
|
||||
#define PSB_2D_ROP3_BLACKNESS (0x0000)
|
||||
#define PSB_2D_ROP3_SRC (0xCC)
|
||||
#define PSB_2D_ROP3_PAT (0xF0)
|
||||
#define PSB_2D_ROP3_DST (0xAA)
|
||||
|
||||
/*
|
||||
* Sizes.
|
||||
*/
|
||||
|
||||
#define PSB_SCENE_HW_COOKIE_SIZE 16
|
||||
#define PSB_TA_MEM_HW_COOKIE_SIZE 16
|
||||
|
||||
/*
|
||||
* Scene stuff.
|
||||
*/
|
||||
|
||||
#define PSB_NUM_HW_SCENES 2
|
||||
|
||||
/*
|
||||
* Scheduler completion actions.
|
||||
*/
|
||||
|
||||
#define PSB_RASTER_BLOCK 0
|
||||
#define PSB_RASTER 1
|
||||
#define PSB_RETURN 2
|
||||
#define PSB_TA 3
|
||||
|
||||
/* Power management */
|
||||
#define PSB_PUNIT_PORT 0x04
|
||||
#define PSB_OSPMBA 0x78
|
||||
#define PSB_APMBA 0x7a
|
||||
#define PSB_APM_CMD 0x0
|
||||
#define PSB_APM_STS 0x04
|
||||
#define PSB_PWRGT_VID_ENC_MASK 0x30
|
||||
#define PSB_PWRGT_VID_DEC_MASK 0xc
|
||||
#define PSB_PWRGT_GL3_MASK 0xc0
|
||||
|
||||
#define PSB_PM_SSC 0x20
|
||||
#define PSB_PM_SSS 0x30
|
||||
#define PSB_PWRGT_DISPLAY_MASK 0xc /*on a different BA than video/gfx*/
|
||||
#define MDFLD_PWRGT_DISPLAY_A_CNTR 0x0000000c
|
||||
#define MDFLD_PWRGT_DISPLAY_B_CNTR 0x0000c000
|
||||
#define MDFLD_PWRGT_DISPLAY_C_CNTR 0x00030000
|
||||
#define MDFLD_PWRGT_DISP_MIPI_CNTR 0x000c0000
|
||||
#define MDFLD_PWRGT_DISPLAY_CNTR (MDFLD_PWRGT_DISPLAY_A_CNTR | MDFLD_PWRGT_DISPLAY_B_CNTR | MDFLD_PWRGT_DISPLAY_C_CNTR | MDFLD_PWRGT_DISP_MIPI_CNTR) /* 0x000fc00c */
|
||||
/* Display SSS register bits are different in A0 vs. B0 */
|
||||
#define PSB_PWRGT_GFX_MASK 0x3
|
||||
#define MDFLD_PWRGT_DISPLAY_A_STS 0x000000c0
|
||||
#define MDFLD_PWRGT_DISPLAY_B_STS 0x00000300
|
||||
#define MDFLD_PWRGT_DISPLAY_C_STS 0x00000c00
|
||||
#define PSB_PWRGT_GFX_MASK_B0 0xc3
|
||||
#define MDFLD_PWRGT_DISPLAY_A_STS_B0 0x0000000c
|
||||
#define MDFLD_PWRGT_DISPLAY_B_STS_B0 0x0000c000
|
||||
#define MDFLD_PWRGT_DISPLAY_C_STS_B0 0x00030000
|
||||
#define MDFLD_PWRGT_DISP_MIPI_STS 0x000c0000
|
||||
#define MDFLD_PWRGT_DISPLAY_STS_A0 (MDFLD_PWRGT_DISPLAY_A_STS | MDFLD_PWRGT_DISPLAY_B_STS | MDFLD_PWRGT_DISPLAY_C_STS | MDFLD_PWRGT_DISP_MIPI_STS) /* 0x000fc00c */
|
||||
#define MDFLD_PWRGT_DISPLAY_STS_B0 (MDFLD_PWRGT_DISPLAY_A_STS_B0 | MDFLD_PWRGT_DISPLAY_B_STS_B0 | MDFLD_PWRGT_DISPLAY_C_STS_B0 | MDFLD_PWRGT_DISP_MIPI_STS) /* 0x000fc00c */
|
||||
#endif
|
||||
Loading…
Reference in New Issue
Block a user