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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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cxgb4: initialize hash-filter configuration
Add support for hash-filter configuration on T6. Also, do basic checks for the related initialization. Signed-off-by: Kumar Sanghvi <kumaras@chelsio.com> Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com> Signed-off-by: Ganesh Goudar <ganeshgr@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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0ba9a3b65c
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5c31254e35
@ -366,6 +366,7 @@ struct adapter_params {
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unsigned char crypto; /* HW capability for crypto */
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unsigned char bypass;
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unsigned char hash_filter;
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unsigned int ofldq_wr_cred;
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bool ulptx_memwrite_dsgl; /* use of T5 DSGL allowed */
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@ -1140,6 +1141,11 @@ static inline int is_offload(const struct adapter *adap)
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return adap->params.offload;
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}
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static inline int is_hashfilter(const struct adapter *adap)
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{
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return adap->params.hash_filter;
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}
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static inline int is_pci_uld(const struct adapter *adap)
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{
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return adap->params.crypto;
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@ -915,3 +915,25 @@ void filter_rpl(struct adapter *adap, const struct cpl_set_tcb_rpl *rpl)
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complete(&ctx->completion);
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}
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}
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int init_hash_filter(struct adapter *adap)
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{
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/* On T6, verify the necessary register configs and warn the user in
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* case of improper config
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*/
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if (is_t6(adap->params.chip)) {
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if (TCAM_ACTV_HIT_G(t4_read_reg(adap, LE_DB_RSP_CODE_0_A)) != 4)
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goto err;
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if (HASH_ACTV_HIT_G(t4_read_reg(adap, LE_DB_RSP_CODE_1_A)) != 4)
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goto err;
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} else {
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dev_err(adap->pdev_dev, "Hash filter supported only on T6\n");
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return -EINVAL;
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}
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adap->params.hash_filter = 1;
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return 0;
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err:
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dev_warn(adap->pdev_dev, "Invalid hash filter config!\n");
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return -EINVAL;
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}
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@ -45,4 +45,5 @@ int delete_filter(struct adapter *adapter, unsigned int fidx);
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int writable_filter(struct filter_entry *f);
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void clear_all_filters(struct adapter *adapter);
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int init_hash_filter(struct adapter *adap);
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#endif /* __CXGB4_FILTER_H */
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@ -3963,7 +3963,8 @@ static int adap_init0(struct adapter *adap)
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if (ret < 0)
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goto bye;
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if (caps_cmd.ofldcaps) {
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if (caps_cmd.ofldcaps ||
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(caps_cmd.niccaps & htons(FW_CAPS_CONFIG_NIC_HASHFILTER))) {
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/* query offload-related parameters */
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params[0] = FW_PARAM_DEV(NTID);
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params[1] = FW_PARAM_PFVF(SERVER_START);
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@ -4000,8 +4001,13 @@ static int adap_init0(struct adapter *adap)
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adap->vres.ddp.size = val[4] - val[3] + 1;
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adap->params.ofldq_wr_cred = val[5];
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adap->params.offload = 1;
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adap->num_ofld_uld += 1;
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if (caps_cmd.niccaps & htons(FW_CAPS_CONFIG_NIC_HASHFILTER)) {
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if (init_hash_filter(adap) < 0)
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goto bye;
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} else {
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adap->params.offload = 1;
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adap->num_ofld_uld += 1;
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}
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}
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if (caps_cmd.rdmacaps) {
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params[0] = FW_PARAM_PFVF(STAG_START);
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@ -5171,7 +5177,7 @@ static int init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
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cxgb4_init_tc_flower(adapter);
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}
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if (is_offload(adapter)) {
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if (is_offload(adapter) || is_hashfilter(adapter)) {
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if (t4_read_reg(adapter, LE_DB_CONFIG_A) & HASHEN_F) {
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u32 hash_base, hash_reg;
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@ -2933,6 +2933,20 @@
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#define SSRAMINTPERR_V(x) ((x) << SSRAMINTPERR_S)
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#define SSRAMINTPERR_F SSRAMINTPERR_V(1U)
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#define LE_DB_RSP_CODE_0_A 0x19c74
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#define TCAM_ACTV_HIT_S 0
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#define TCAM_ACTV_HIT_M 0x1fU
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#define TCAM_ACTV_HIT_V(x) ((x) << TCAM_ACTV_HIT_S)
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#define TCAM_ACTV_HIT_G(x) (((x) >> TCAM_ACTV_HIT_S) & TCAM_ACTV_HIT_M)
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#define LE_DB_RSP_CODE_1_A 0x19c78
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#define HASH_ACTV_HIT_S 25
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#define HASH_ACTV_HIT_M 0x1fU
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#define HASH_ACTV_HIT_V(x) ((x) << HASH_ACTV_HIT_S)
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#define HASH_ACTV_HIT_G(x) (((x) >> HASH_ACTV_HIT_S) & HASH_ACTV_HIT_M)
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#define LE_3_DB_HASH_MASK_GEN_IPV4_T6_A 0x19eac
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#define LE_4_DB_HASH_MASK_GEN_IPV4_T6_A 0x19eb0
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@ -1092,6 +1092,7 @@ enum fw_caps_config_switch {
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enum fw_caps_config_nic {
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FW_CAPS_CONFIG_NIC = 0x00000001,
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FW_CAPS_CONFIG_NIC_VM = 0x00000002,
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FW_CAPS_CONFIG_NIC_HASHFILTER = 0x00000020,
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};
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enum fw_caps_config_ofld {
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