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ARM: S3C24XX: Add clock-lookup entries required by s3c64xx-spi
Currently usable are busclk0 and busclk2. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
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@ -144,6 +144,7 @@ static struct clk_lookup s3c2416_clk_lookup[] = {
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CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.0", &hsmmc0_clk),
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CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &hsmmc_mux0.clk),
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CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &hsmmc_mux1.clk),
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CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk2", &hsspi_mux.clk),
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};
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void __init s3c2416_init_clocks(int xtal)
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@ -181,6 +181,7 @@ static struct clk *clks[] __initdata = {
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static struct clk_lookup s3c2443_clk_lookup[] = {
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CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_hsmmc),
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CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk2", &clk_hsspi.clk),
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};
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void __init s3c2443_init_clocks(int xtal)
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@ -423,11 +423,6 @@ static struct clk init_clocks_off[] = {
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.parent = &clk_p,
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.enable = s3c2443_clkcon_enable_p,
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.ctrlbit = S3C2443_PCLKCON_IIS,
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}, {
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.name = "hsspi",
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.parent = &clk_p,
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.enable = s3c2443_clkcon_enable_p,
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.ctrlbit = S3C2443_PCLKCON_HSSPI,
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}, {
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.name = "adc",
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.parent = &clk_p,
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@ -562,6 +557,14 @@ static struct clk hsmmc1_clk = {
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.ctrlbit = S3C2443_HCLKCON_HSMMC,
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};
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static struct clk hsspi_clk = {
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.name = "spi",
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.devname = "s3c64xx-spi.0",
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.parent = &clk_p,
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.enable = s3c2443_clkcon_enable_p,
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.ctrlbit = S3C2443_PCLKCON_HSSPI,
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};
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/* EPLLCON compatible enough to get on/off information */
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void __init_or_cpufreq s3c2443_common_setup_clocks(pll_fn get_mpll)
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@ -612,6 +615,7 @@ static struct clk *clks[] __initdata = {
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&clk_usb_bus,
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&clk_armdiv,
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&hsmmc1_clk,
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&hsspi_clk,
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};
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static struct clksrc_clk *clksrcs[] __initdata = {
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@ -629,6 +633,7 @@ static struct clk_lookup s3c2443_clk_lookup[] = {
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CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p),
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CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_esys_uart.clk),
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CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.0", &hsmmc1_clk),
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CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk0", &hsspi_clk),
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};
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void __init s3c2443_common_init_clocks(int xtal, pll_fn get_mpll,
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