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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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arm64: add explicit symbols to ESR_EL1 decoding
The ESR_EL1 decoding process is a bit cryptic, and KVM has also a need for the same constants. Add a new esr.h file containing the appropriate exception classes constants, and change entry.S to use it. Fix a small bug in the EL1 breakpoint check while we're at it. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
This commit is contained in:
Marc Zyngier
Catalin Marinas
parent
d4784be3b2
commit
5c1ce6f7c2
55
arch/arm64/include/asm/esr.h
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55
arch/arm64/include/asm/esr.h
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@ -0,0 +1,55 @@
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/*
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* Copyright (C) 2013 - ARM Ltd
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* Author: Marc Zyngier <marc.zyngier@arm.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __ASM_ESR_H
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#define __ASM_ESR_H
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#define ESR_EL1_EC_SHIFT (26)
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#define ESR_EL1_IL (1U << 25)
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#define ESR_EL1_EC_UNKNOWN (0x00)
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#define ESR_EL1_EC_WFI (0x01)
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#define ESR_EL1_EC_CP15_32 (0x03)
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#define ESR_EL1_EC_CP15_64 (0x04)
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#define ESR_EL1_EC_CP14_MR (0x05)
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#define ESR_EL1_EC_CP14_LS (0x06)
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#define ESR_EL1_EC_FP_ASIMD (0x07)
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#define ESR_EL1_EC_CP10_ID (0x08)
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#define ESR_EL1_EC_CP14_64 (0x0C)
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#define ESR_EL1_EC_ILL_ISS (0x0E)
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#define ESR_EL1_EC_SVC32 (0x11)
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#define ESR_EL1_EC_SVC64 (0x15)
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#define ESR_EL1_EC_SYS64 (0x18)
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#define ESR_EL1_EC_IABT_EL0 (0x20)
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#define ESR_EL1_EC_IABT_EL1 (0x21)
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#define ESR_EL1_EC_PC_ALIGN (0x22)
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#define ESR_EL1_EC_DABT_EL0 (0x24)
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#define ESR_EL1_EC_DABT_EL1 (0x25)
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#define ESR_EL1_EC_SP_ALIGN (0x26)
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#define ESR_EL1_EC_FP_EXC32 (0x28)
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#define ESR_EL1_EC_FP_EXC64 (0x2C)
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#define ESR_EL1_EC_SERRROR (0x2F)
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#define ESR_EL1_EC_BREAKPT_EL0 (0x30)
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#define ESR_EL1_EC_BREAKPT_EL1 (0x31)
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#define ESR_EL1_EC_SOFTSTP_EL0 (0x32)
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#define ESR_EL1_EC_SOFTSTP_EL1 (0x33)
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#define ESR_EL1_EC_WATCHPT_EL0 (0x34)
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#define ESR_EL1_EC_WATCHPT_EL1 (0x35)
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#define ESR_EL1_EC_BKPT32 (0x38)
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#define ESR_EL1_EC_BRK64 (0x3C)
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#endif /* __ASM_ESR_H */
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@ -24,6 +24,7 @@
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#include <asm/assembler.h>
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#include <asm/asm-offsets.h>
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#include <asm/errno.h>
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#include <asm/esr.h>
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#include <asm/thread_info.h>
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#include <asm/unistd.h>
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#include <asm/unistd32.h>
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@ -239,18 +240,18 @@ ENDPROC(el1_error_invalid)
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el1_sync:
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kernel_entry 1
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mrs x1, esr_el1 // read the syndrome register
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lsr x24, x1, #26 // exception class
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cmp x24, #0x25 // data abort in EL1
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lsr x24, x1, #ESR_EL1_EC_SHIFT // exception class
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cmp x24, #ESR_EL1_EC_DABT_EL1 // data abort in EL1
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b.eq el1_da
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cmp x24, #0x18 // configurable trap
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cmp x24, #ESR_EL1_EC_SYS64 // configurable trap
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b.eq el1_undef
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cmp x24, #0x26 // stack alignment exception
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cmp x24, #ESR_EL1_EC_SP_ALIGN // stack alignment exception
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b.eq el1_sp_pc
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cmp x24, #0x22 // pc alignment exception
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cmp x24, #ESR_EL1_EC_PC_ALIGN // pc alignment exception
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b.eq el1_sp_pc
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cmp x24, #0x00 // unknown exception in EL1
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cmp x24, #ESR_EL1_EC_UNKNOWN // unknown exception in EL1
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b.eq el1_undef
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cmp x24, #0x30 // debug exception in EL1
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cmp x24, #ESR_EL1_EC_BREAKPT_EL1 // debug exception in EL1
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b.ge el1_dbg
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b el1_inv
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el1_da:
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@ -346,27 +347,27 @@ el1_preempt:
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el0_sync:
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kernel_entry 0
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mrs x25, esr_el1 // read the syndrome register
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lsr x24, x25, #26 // exception class
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cmp x24, #0x15 // SVC in 64-bit state
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lsr x24, x25, #ESR_EL1_EC_SHIFT // exception class
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cmp x24, #ESR_EL1_EC_SVC64 // SVC in 64-bit state
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b.eq el0_svc
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adr lr, ret_from_exception
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cmp x24, #0x24 // data abort in EL0
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cmp x24, #ESR_EL1_EC_DABT_EL0 // data abort in EL0
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b.eq el0_da
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cmp x24, #0x20 // instruction abort in EL0
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cmp x24, #ESR_EL1_EC_IABT_EL0 // instruction abort in EL0
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b.eq el0_ia
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cmp x24, #0x07 // FP/ASIMD access
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cmp x24, #ESR_EL1_EC_FP_ASIMD // FP/ASIMD access
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b.eq el0_fpsimd_acc
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cmp x24, #0x2c // FP/ASIMD exception
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cmp x24, #ESR_EL1_EC_FP_EXC64 // FP/ASIMD exception
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b.eq el0_fpsimd_exc
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cmp x24, #0x18 // configurable trap
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cmp x24, #ESR_EL1_EC_SYS64 // configurable trap
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b.eq el0_undef
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cmp x24, #0x26 // stack alignment exception
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cmp x24, #ESR_EL1_EC_SP_ALIGN // stack alignment exception
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b.eq el0_sp_pc
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cmp x24, #0x22 // pc alignment exception
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cmp x24, #ESR_EL1_EC_PC_ALIGN // pc alignment exception
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b.eq el0_sp_pc
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cmp x24, #0x00 // unknown exception in EL0
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cmp x24, #ESR_EL1_EC_UNKNOWN // unknown exception in EL0
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b.eq el0_undef
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cmp x24, #0x30 // debug exception in EL0
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cmp x24, #ESR_EL1_EC_BREAKPT_EL0 // debug exception in EL0
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b.ge el0_dbg
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b el0_inv
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@ -375,21 +376,21 @@ el0_sync:
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el0_sync_compat:
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kernel_entry 0, 32
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mrs x25, esr_el1 // read the syndrome register
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lsr x24, x25, #26 // exception class
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cmp x24, #0x11 // SVC in 32-bit state
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lsr x24, x25, #ESR_EL1_EC_SHIFT // exception class
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cmp x24, #ESR_EL1_EC_SVC32 // SVC in 32-bit state
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b.eq el0_svc_compat
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adr lr, ret_from_exception
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cmp x24, #0x24 // data abort in EL0
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cmp x24, #ESR_EL1_EC_DABT_EL0 // data abort in EL0
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b.eq el0_da
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cmp x24, #0x20 // instruction abort in EL0
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cmp x24, #ESR_EL1_EC_IABT_EL0 // instruction abort in EL0
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b.eq el0_ia
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cmp x24, #0x07 // FP/ASIMD access
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cmp x24, #ESR_EL1_EC_FP_ASIMD // FP/ASIMD access
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b.eq el0_fpsimd_acc
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cmp x24, #0x28 // FP/ASIMD exception
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cmp x24, #ESR_EL1_EC_FP_EXC32 // FP/ASIMD exception
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b.eq el0_fpsimd_exc
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cmp x24, #0x00 // unknown exception in EL0
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cmp x24, #ESR_EL1_EC_UNKNOWN // unknown exception in EL0
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b.eq el0_undef
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cmp x24, #0x30 // debug exception in EL0
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cmp x24, #ESR_EL1_EC_BREAKPT_EL0 // debug exception in EL0
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b.ge el0_dbg
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b el0_inv
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el0_svc_compat:
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