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Merge branch 'drm-fixes-4.17' of git://people.freedesktop.org/~agd5f/linux into drm-fixes

Browse Source 
A little bigger than normal since this is two weeks of fixes.
- Atom firmware table updates for vega12
- Fix fallout from huge page support
- Fix up smu7 power profile interface to be consistent with vega
- Misc other fixes

* 'drm-fixes-4.17' of git://people.freedesktop.org/~agd5f/linux:
  drm/amd/pp: Refine the output of pp_power_profile_mode on VI
  drm/amdgpu: Switch to interruptable wait to recover from ring hang.
  drm/ttm: Use GFP_TRANSHUGE_LIGHT for allocating huge pages
  drm/amd/display: Use kvzalloc for potentially large allocations
  drm/amd/display: Don't return ddc result and read_bytes in same return value
  drm/amd/display: Add get_firmware_info_v3_2 for VG12
  drm/amd: Add BIOS smu_info v3_3 required struct def.
  drm/amd/display: Add VG12 ASIC IDs
This commit is contained in:
Dave Airlie 2018-05-10 11:28:46 +10:00
commit 5c0e0b45c4
13 changed files with 364 additions and 95 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
View File

@ -419,9 +419,11 @@ int amdgpu_ctx_wait_prev_fence(struct amdgpu_ctx *ctx, unsigned ring_id)
if (other) {
signed long r;
r = dma_fence_wait_timeout(other, false, MAX_SCHEDULE_TIMEOUT);
r = dma_fence_wait(other, true);
if (r < 0) {
DRM_ERROR("Error (%ld) waiting for fence!\n", r);
if (r != -ERESTARTSYS)
DRM_ERROR("Error (%ld) waiting for fence!\n", r);
return r;
}
}

20
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
View File

@ -83,21 +83,22 @@ static ssize_t dm_dp_aux_transfer(struct drm_dp_aux *aux,
enum i2c_mot_mode mot = (msg->request & DP_AUX_I2C_MOT) ?
I2C_MOT_TRUE : I2C_MOT_FALSE;
enum ddc_result res;
ssize_t read_bytes;
uint32_t read_bytes = msg->size;
if (WARN_ON(msg->size > 16))
return -E2BIG;
switch (msg->request & ~DP_AUX_I2C_MOT) {
case DP_AUX_NATIVE_READ:
read_bytes = dal_ddc_service_read_dpcd_data(
res = dal_ddc_service_read_dpcd_data(
TO_DM_AUX(aux)->ddc_service,
false,
I2C_MOT_UNDEF,
msg->address,
msg->buffer,
msg->size);
return read_bytes;
msg->size,
&read_bytes);
break;
case DP_AUX_NATIVE_WRITE:
res = dal_ddc_service_write_dpcd_data(
TO_DM_AUX(aux)->ddc_service,
@ -108,14 +109,15 @@ static ssize_t dm_dp_aux_transfer(struct drm_dp_aux *aux,
msg->size);
break;
case DP_AUX_I2C_READ:
read_bytes = dal_ddc_service_read_dpcd_data(
res = dal_ddc_service_read_dpcd_data(
TO_DM_AUX(aux)->ddc_service,
true,
mot,
msg->address,
msg->buffer,
msg->size);
return read_bytes;
msg->size,
&read_bytes);
break;
case DP_AUX_I2C_WRITE:
res = dal_ddc_service_write_dpcd_data(
TO_DM_AUX(aux)->ddc_service,
@ -137,7 +139,9 @@ static ssize_t dm_dp_aux_transfer(struct drm_dp_aux *aux,
r == DDC_RESULT_SUCESSFULL);
#endif
return msg->size;
if (res != DDC_RESULT_SUCESSFULL)
return -EIO;
return read_bytes;
}
static enum drm_connector_status

86
drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
View File

@ -70,6 +70,10 @@ static enum bp_result get_firmware_info_v3_1(
struct bios_parser *bp,
struct dc_firmware_info *info);
static enum bp_result get_firmware_info_v3_2(
struct bios_parser *bp,
struct dc_firmware_info *info);
static struct atom_hpd_int_record *get_hpd_record(struct bios_parser *bp,
struct atom_display_object_path_v2 *object);
@ -1321,9 +1325,11 @@ static enum bp_result bios_parser_get_firmware_info(
case 3:
switch (revision.minor) {
case 1:
case 2:
result = get_firmware_info_v3_1(bp, info);
break;
case 2:
result = get_firmware_info_v3_2(bp, info);
break;
default:
break;
}
@ -1383,6 +1389,84 @@ static enum bp_result get_firmware_info_v3_1(
return BP_RESULT_OK;
}
static enum bp_result get_firmware_info_v3_2(
struct bios_parser *bp,
struct dc_firmware_info *info)
{
struct atom_firmware_info_v3_2 *firmware_info;
struct atom_display_controller_info_v4_1 *dce_info = NULL;
struct atom_common_table_header *header;
struct atom_data_revision revision;
struct atom_smu_info_v3_2 *smu_info_v3_2 = NULL;
struct atom_smu_info_v3_3 *smu_info_v3_3 = NULL;
if (!info)
return BP_RESULT_BADINPUT;
firmware_info = GET_IMAGE(struct atom_firmware_info_v3_2,
DATA_TABLES(firmwareinfo));
dce_info = GET_IMAGE(struct atom_display_controller_info_v4_1,
DATA_TABLES(dce_info));
if (!firmware_info || !dce_info)
return BP_RESULT_BADBIOSTABLE;
memset(info, 0, sizeof(*info));
header = GET_IMAGE(struct atom_common_table_header,
DATA_TABLES(smu_info));
get_atom_data_table_revision(header, &revision);
if (revision.minor == 2) {
/* Vega12 */
smu_info_v3_2 = GET_IMAGE(struct atom_smu_info_v3_2,
DATA_TABLES(smu_info));
if (!smu_info_v3_2)
return BP_RESULT_BADBIOSTABLE;
info->default_engine_clk = smu_info_v3_2->bootup_dcefclk_10khz * 10;
} else if (revision.minor == 3) {
/* Vega20 */
smu_info_v3_3 = GET_IMAGE(struct atom_smu_info_v3_3,
DATA_TABLES(smu_info));
if (!smu_info_v3_3)
return BP_RESULT_BADBIOSTABLE;
info->default_engine_clk = smu_info_v3_3->bootup_dcefclk_10khz * 10;
}
// We need to convert from 10KHz units into KHz units.
info->default_memory_clk = firmware_info->bootup_mclk_in10khz * 10;
/* 27MHz for Vega10 & Vega12; 100MHz for Vega20 */
info->pll_info.crystal_frequency = dce_info->dce_refclk_10khz * 10;
/* Hardcode frequency if BIOS gives no DCE Ref Clk */
if (info->pll_info.crystal_frequency == 0) {
if (revision.minor == 2)
info->pll_info.crystal_frequency = 27000;
else if (revision.minor == 3)
info->pll_info.crystal_frequency = 100000;
}
/*dp_phy_ref_clk is not correct for atom_display_controller_info_v4_2, but we don't use it*/
info->dp_phy_ref_clk = dce_info->dpphy_refclk_10khz * 10;
info->i2c_engine_ref_clk = dce_info->i2c_engine_refclk_10khz * 10;
/* Get GPU PLL VCO Clock */
if (bp->cmd_tbl.get_smu_clock_info != NULL) {
if (revision.minor == 2)
info->smu_gpu_pll_output_freq =
bp->cmd_tbl.get_smu_clock_info(bp, SMU9_SYSPLL0_ID) * 10;
else if (revision.minor == 3)
info->smu_gpu_pll_output_freq =
bp->cmd_tbl.get_smu_clock_info(bp, SMU11_SYSPLL3_0_ID) * 10;
}
return BP_RESULT_OK;
}
static enum bp_result bios_parser_get_encoder_cap_info(
struct dc_bios *dcb,
struct graphics_object_id object_id,

10
drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
View File

@ -629,13 +629,14 @@ bool dal_ddc_service_query_ddc_data(
return ret;
}
ssize_t dal_ddc_service_read_dpcd_data(
enum ddc_result dal_ddc_service_read_dpcd_data(
struct ddc_service *ddc,
bool i2c,
enum i2c_mot_mode mot,
uint32_t address,
uint8_t *data,
uint32_t len)
uint32_t len,
uint32_t *read)
{
struct aux_payload read_payload = {
.i2c_over_aux = i2c,
@ -652,6 +653,8 @@ ssize_t dal_ddc_service_read_dpcd_data(
.mot = mot
};
*read = 0;
if (len > DEFAULT_AUX_MAX_DATA_SIZE) {
BREAK_TO_DEBUGGER();
return DDC_RESULT_FAILED_INVALID_OPERATION;
@ -661,7 +664,8 @@ ssize_t dal_ddc_service_read_dpcd_data(
ddc->ctx->i2caux,
ddc->ddc_pin,
&command)) {
return (ssize_t)command.payloads->length;
*read = command.payloads->length;
return DDC_RESULT_SUCESSFULL;
}
return DDC_RESULT_FAILED_OPERATION;

14
drivers/gpu/drm/amd/display/dc/core/dc_surface.c
View File

@ -66,8 +66,8 @@ struct dc_plane_state *dc_create_plane_state(struct dc *dc)
{
struct dc *core_dc = dc;
struct dc_plane_state *plane_state = kzalloc(sizeof(*plane_state),
GFP_KERNEL);
struct dc_plane_state *plane_state = kvzalloc(sizeof(*plane_state),
GFP_KERNEL);
if (NULL == plane_state)
return NULL;
@ -120,7 +120,7 @@ static void dc_plane_state_free(struct kref *kref)
{
struct dc_plane_state *plane_state = container_of(kref, struct dc_plane_state, refcount);
destruct(plane_state);
kfree(plane_state);
kvfree(plane_state);
}
void dc_plane_state_release(struct dc_plane_state *plane_state)
@ -136,7 +136,7 @@ void dc_gamma_retain(struct dc_gamma *gamma)
static void dc_gamma_free(struct kref *kref)
{
struct dc_gamma *gamma = container_of(kref, struct dc_gamma, refcount);
kfree(gamma);
kvfree(gamma);
}
void dc_gamma_release(struct dc_gamma **gamma)
@ -147,7 +147,7 @@ void dc_gamma_release(struct dc_gamma **gamma)
struct dc_gamma *dc_create_gamma(void)
{
struct dc_gamma *gamma = kzalloc(sizeof(*gamma), GFP_KERNEL);
struct dc_gamma *gamma = kvzalloc(sizeof(*gamma), GFP_KERNEL);
if (gamma == NULL)
goto alloc_fail;
@ -167,7 +167,7 @@ void dc_transfer_func_retain(struct dc_transfer_func *tf)
static void dc_transfer_func_free(struct kref *kref)
{
struct dc_transfer_func *tf = container_of(kref, struct dc_transfer_func, refcount);
kfree(tf);
kvfree(tf);
}
void dc_transfer_func_release(struct dc_transfer_func *tf)
@ -177,7 +177,7 @@ void dc_transfer_func_release(struct dc_transfer_func *tf)
struct dc_transfer_func *dc_create_transfer_func(void)
{
struct dc_transfer_func *tf = kzalloc(sizeof(*tf), GFP_KERNEL);
struct dc_transfer_func *tf = kvzalloc(sizeof(*tf), GFP_KERNEL);
if (tf == NULL)
goto alloc_fail;

5
drivers/gpu/drm/amd/display/dc/inc/dc_link_ddc.h
View File

@ -102,13 +102,14 @@ bool dal_ddc_service_query_ddc_data(
uint8_t *read_buf,
uint32_t read_size);
ssize_t dal_ddc_service_read_dpcd_data(
enum ddc_result dal_ddc_service_read_dpcd_data(
struct ddc_service *ddc,
bool i2c,
enum i2c_mot_mode mot,
uint32_t address,
uint8_t *data,
uint32_t len);
uint32_t len,
uint32_t *read);
enum ddc_result dal_ddc_service_write_dpcd_data(
struct ddc_service *ddc,

9
drivers/gpu/drm/amd/display/include/dal_asic_id.h
View File

@ -113,9 +113,14 @@
#define AI_GREENLAND_P_A0 1
#define AI_GREENLAND_P_A1 2
#define AI_UNKNOWN 0xFF
#define ASICREV_IS_GREENLAND_M(eChipRev) (eChipRev < AI_UNKNOWN)
#define ASICREV_IS_GREENLAND_P(eChipRev) (eChipRev < AI_UNKNOWN)
#define AI_VEGA12_P_A0 20
#define ASICREV_IS_GREENLAND_M(eChipRev) (eChipRev < AI_VEGA12_P_A0)
#define ASICREV_IS_GREENLAND_P(eChipRev) (eChipRev < AI_VEGA12_P_A0)
#define ASICREV_IS_VEGA12_P(eChipRev) ((eChipRev >= AI_VEGA12_P_A0) && (eChipRev < AI_UNKNOWN))
#define ASICREV_IS_VEGA12_p(eChipRev) ((eChipRev >= AI_VEGA12_P_A0) && (eChipRev < AI_UNKNOWN))
/* DCN1_0 */
#define INTERNAL_REV_RAVEN_A0 0x00 /* First spin of Raven */

72
drivers/gpu/drm/amd/display/modules/color/color_gamma.c
View File

@ -1093,19 +1093,19 @@ bool mod_color_calculate_regamma_params(struct dc_transfer_func *output_tf,
output_tf->type = TF_TYPE_DISTRIBUTED_POINTS;
rgb_user = kzalloc(sizeof(*rgb_user) * (ramp->num_entries + _EXTRA_POINTS),
GFP_KERNEL);
rgb_user = kvzalloc(sizeof(*rgb_user) * (ramp->num_entries + _EXTRA_POINTS),
GFP_KERNEL);
if (!rgb_user)
goto rgb_user_alloc_fail;
rgb_regamma = kzalloc(sizeof(*rgb_regamma) * (MAX_HW_POINTS + _EXTRA_POINTS),
GFP_KERNEL);
rgb_regamma = kvzalloc(sizeof(*rgb_regamma) * (MAX_HW_POINTS + _EXTRA_POINTS),
GFP_KERNEL);
if (!rgb_regamma)
goto rgb_regamma_alloc_fail;
axix_x = kzalloc(sizeof(*axix_x) * (ramp->num_entries + 3),
GFP_KERNEL);
axix_x = kvzalloc(sizeof(*axix_x) * (ramp->num_entries + 3),
GFP_KERNEL);
if (!axix_x)
goto axix_x_alloc_fail;
coeff = kzalloc(sizeof(*coeff) * (MAX_HW_POINTS + _EXTRA_POINTS), GFP_KERNEL);
coeff = kvzalloc(sizeof(*coeff) * (MAX_HW_POINTS + _EXTRA_POINTS), GFP_KERNEL);
if (!coeff)
goto coeff_alloc_fail;
@ -1157,13 +1157,13 @@ bool mod_color_calculate_regamma_params(struct dc_transfer_func *output_tf,
ret = true;
kfree(coeff);
kvfree(coeff);
coeff_alloc_fail:
kfree(axix_x);
kvfree(axix_x);
axix_x_alloc_fail:
kfree(rgb_regamma);
kvfree(rgb_regamma);
rgb_regamma_alloc_fail:
kfree(rgb_user);
kvfree(rgb_user);
rgb_user_alloc_fail:
return ret;
}
@ -1192,19 +1192,19 @@ bool mod_color_calculate_degamma_params(struct dc_transfer_func *input_tf,
input_tf->type = TF_TYPE_DISTRIBUTED_POINTS;
rgb_user = kzalloc(sizeof(*rgb_user) * (ramp->num_entries + _EXTRA_POINTS),
GFP_KERNEL);
rgb_user = kvzalloc(sizeof(*rgb_user) * (ramp->num_entries + _EXTRA_POINTS),
GFP_KERNEL);
if (!rgb_user)
goto rgb_user_alloc_fail;
curve = kzalloc(sizeof(*curve) * (MAX_HW_POINTS + _EXTRA_POINTS),
GFP_KERNEL);
curve = kvzalloc(sizeof(*curve) * (MAX_HW_POINTS + _EXTRA_POINTS),
GFP_KERNEL);
if (!curve)
goto curve_alloc_fail;
axix_x = kzalloc(sizeof(*axix_x) * (ramp->num_entries + _EXTRA_POINTS),
GFP_KERNEL);
axix_x = kvzalloc(sizeof(*axix_x) * (ramp->num_entries + _EXTRA_POINTS),
GFP_KERNEL);
if (!axix_x)
goto axix_x_alloc_fail;
coeff = kzalloc(sizeof(*coeff) * (MAX_HW_POINTS + _EXTRA_POINTS), GFP_KERNEL);
coeff = kvzalloc(sizeof(*coeff) * (MAX_HW_POINTS + _EXTRA_POINTS), GFP_KERNEL);
if (!coeff)
goto coeff_alloc_fail;
@ -1246,13 +1246,13 @@ bool mod_color_calculate_degamma_params(struct dc_transfer_func *input_tf,
ret = true;
kfree(coeff);
kvfree(coeff);
coeff_alloc_fail:
kfree(axix_x);
kvfree(axix_x);
axix_x_alloc_fail:
kfree(curve);
kvfree(curve);
curve_alloc_fail:
kfree(rgb_user);
kvfree(rgb_user);
rgb_user_alloc_fail:
return ret;
@ -1281,8 +1281,9 @@ bool mod_color_calculate_curve(enum dc_transfer_func_predefined trans,
}
ret = true;
} else if (trans == TRANSFER_FUNCTION_PQ) {
rgb_regamma = kzalloc(sizeof(*rgb_regamma) * (MAX_HW_POINTS +
_EXTRA_POINTS), GFP_KERNEL);
rgb_regamma = kvzalloc(sizeof(*rgb_regamma) *
(MAX_HW_POINTS + _EXTRA_POINTS),
GFP_KERNEL);
if (!rgb_regamma)
goto rgb_regamma_alloc_fail;
points->end_exponent = 7;
@ -1302,11 +1303,12 @@ bool mod_color_calculate_curve(enum dc_transfer_func_predefined trans,
}
ret = true;
kfree(rgb_regamma);
kvfree(rgb_regamma);
} else if (trans == TRANSFER_FUNCTION_SRGB ||
trans == TRANSFER_FUNCTION_BT709) {
rgb_regamma = kzalloc(sizeof(*rgb_regamma) * (MAX_HW_POINTS +
_EXTRA_POINTS), GFP_KERNEL);
rgb_regamma = kvzalloc(sizeof(*rgb_regamma) *
(MAX_HW_POINTS + _EXTRA_POINTS),
GFP_KERNEL);
if (!rgb_regamma)
goto rgb_regamma_alloc_fail;
points->end_exponent = 0;
@ -1324,7 +1326,7 @@ bool mod_color_calculate_curve(enum dc_transfer_func_predefined trans,
}
ret = true;
kfree(rgb_regamma);
kvfree(rgb_regamma);
}
rgb_regamma_alloc_fail:
return ret;
@ -1348,8 +1350,9 @@ bool mod_color_calculate_degamma_curve(enum dc_transfer_func_predefined trans,
}
ret = true;
} else if (trans == TRANSFER_FUNCTION_PQ) {
rgb_degamma = kzalloc(sizeof(*rgb_degamma) * (MAX_HW_POINTS +
_EXTRA_POINTS), GFP_KERNEL);
rgb_degamma = kvzalloc(sizeof(*rgb_degamma) *
(MAX_HW_POINTS + _EXTRA_POINTS),
GFP_KERNEL);
if (!rgb_degamma)
goto rgb_degamma_alloc_fail;
@ -1364,11 +1367,12 @@ bool mod_color_calculate_degamma_curve(enum dc_transfer_func_predefined trans,
}
ret = true;
kfree(rgb_degamma);
kvfree(rgb_degamma);
} else if (trans == TRANSFER_FUNCTION_SRGB ||
trans == TRANSFER_FUNCTION_BT709) {
rgb_degamma = kzalloc(sizeof(*rgb_degamma) * (MAX_HW_POINTS +
_EXTRA_POINTS), GFP_KERNEL);
rgb_degamma = kvzalloc(sizeof(*rgb_degamma) *
(MAX_HW_POINTS + _EXTRA_POINTS),
GFP_KERNEL);
if (!rgb_degamma)
goto rgb_degamma_alloc_fail;
@ -1382,7 +1386,7 @@ bool mod_color_calculate_degamma_curve(enum dc_transfer_func_predefined trans,
}
ret = true;
kfree(rgb_degamma);
kvfree(rgb_degamma);
}
points->end_exponent = 0;
points->x_point_at_y1_red = 1;

170
drivers/gpu/drm/amd/include/atomfirmware.h
View File

@ -501,6 +501,32 @@ enum atom_cooling_solution_id{
LIQUID_COOLING = 0x01
};
struct atom_firmware_info_v3_2 {
struct atom_common_table_header table_header;
uint32_t firmware_revision;
uint32_t bootup_sclk_in10khz;
uint32_t bootup_mclk_in10khz;
uint32_t firmware_capability; // enum atombios_firmware_capability
uint32_t main_call_parser_entry; /* direct address of main parser call in VBIOS binary. */
uint32_t bios_scratch_reg_startaddr; // 1st bios scratch register dword address
uint16_t bootup_vddc_mv;
uint16_t bootup_vddci_mv;
uint16_t bootup_mvddc_mv;
uint16_t bootup_vddgfx_mv;
uint8_t mem_module_id;
uint8_t coolingsolution_id; /*0: Air cooling; 1: Liquid cooling ... */
uint8_t reserved1[2];
uint32_t mc_baseaddr_high;
uint32_t mc_baseaddr_low;
uint8_t board_i2c_feature_id; // enum of atom_board_i2c_feature_id_def
uint8_t board_i2c_feature_gpio_id; // i2c id find in gpio_lut data table gpio_id
uint8_t board_i2c_feature_slave_addr;
uint8_t reserved3;
uint16_t bootup_mvddq_mv;
uint16_t bootup_mvpp_mv;
uint32_t zfbstartaddrin16mb;
uint32_t reserved2[3];
};
/*
***************************************************************************
@ -1169,7 +1195,29 @@ struct atom_gfx_info_v2_2
uint32_t rlc_gpu_timer_refclk;
};
struct atom_gfx_info_v2_3 {
struct atom_common_table_header table_header;
uint8_t gfxip_min_ver;
uint8_t gfxip_max_ver;
uint8_t max_shader_engines;
uint8_t max_tile_pipes;
uint8_t max_cu_per_sh;
uint8_t max_sh_per_se;
uint8_t max_backends_per_se;
uint8_t max_texture_channel_caches;
uint32_t regaddr_cp_dma_src_addr;
uint32_t regaddr_cp_dma_src_addr_hi;
uint32_t regaddr_cp_dma_dst_addr;
uint32_t regaddr_cp_dma_dst_addr_hi;
uint32_t regaddr_cp_dma_command;
uint32_t regaddr_cp_status;
uint32_t regaddr_rlc_gpu_clock_32;
uint32_t rlc_gpu_timer_refclk;
uint8_t active_cu_per_sh;
uint8_t active_rb_per_se;
uint16_t gcgoldenoffset;
uint32_t rm21_sram_vmin_value;
};
/*
***************************************************************************
@ -1198,6 +1246,76 @@ struct atom_smu_info_v3_1
uint8_t fw_ctf_polarity; // GPIO polarity for CTF
};
struct atom_smu_info_v3_2 {
struct atom_common_table_header table_header;
uint8_t smuip_min_ver;
uint8_t smuip_max_ver;
uint8_t smu_rsd1;
uint8_t gpuclk_ss_mode;
uint16_t sclk_ss_percentage;
uint16_t sclk_ss_rate_10hz;
uint16_t gpuclk_ss_percentage; // in unit of 0.001%
uint16_t gpuclk_ss_rate_10hz;
uint32_t core_refclk_10khz;
uint8_t ac_dc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for AC/DC switching, =0xff means invalid
uint8_t ac_dc_polarity; // GPIO polarity for AC/DC switching
uint8_t vr0hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR0 HOT event, =0xff means invalid
uint8_t vr0hot_polarity; // GPIO polarity for VR0 HOT event
uint8_t vr1hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR1 HOT event , =0xff means invalid
uint8_t vr1hot_polarity; // GPIO polarity for VR1 HOT event
uint8_t fw_ctf_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for CTF, =0xff means invalid
uint8_t fw_ctf_polarity; // GPIO polarity for CTF
uint8_t pcc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for PCC, =0xff means invalid
uint8_t pcc_gpio_polarity; // GPIO polarity for CTF
uint16_t smugoldenoffset;
uint32_t gpupll_vco_freq_10khz;
uint32_t bootup_smnclk_10khz;
uint32_t bootup_socclk_10khz;
uint32_t bootup_mp0clk_10khz;
uint32_t bootup_mp1clk_10khz;
uint32_t bootup_lclk_10khz;
uint32_t bootup_dcefclk_10khz;
uint32_t ctf_threshold_override_value;
uint32_t reserved[5];
};
struct atom_smu_info_v3_3 {
struct atom_common_table_header table_header;
uint8_t smuip_min_ver;
uint8_t smuip_max_ver;
uint8_t smu_rsd1;
uint8_t gpuclk_ss_mode;
uint16_t sclk_ss_percentage;
uint16_t sclk_ss_rate_10hz;
uint16_t gpuclk_ss_percentage; // in unit of 0.001%
uint16_t gpuclk_ss_rate_10hz;
uint32_t core_refclk_10khz;
uint8_t ac_dc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for AC/DC switching, =0xff means invalid
uint8_t ac_dc_polarity; // GPIO polarity for AC/DC switching
uint8_t vr0hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR0 HOT event, =0xff means invalid
uint8_t vr0hot_polarity; // GPIO polarity for VR0 HOT event
uint8_t vr1hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR1 HOT event , =0xff means invalid
uint8_t vr1hot_polarity; // GPIO polarity for VR1 HOT event
uint8_t fw_ctf_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for CTF, =0xff means invalid
uint8_t fw_ctf_polarity; // GPIO polarity for CTF
uint8_t pcc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for PCC, =0xff means invalid
uint8_t pcc_gpio_polarity; // GPIO polarity for CTF
uint16_t smugoldenoffset;
uint32_t gpupll_vco_freq_10khz;
uint32_t bootup_smnclk_10khz;
uint32_t bootup_socclk_10khz;
uint32_t bootup_mp0clk_10khz;
uint32_t bootup_mp1clk_10khz;
uint32_t bootup_lclk_10khz;
uint32_t bootup_dcefclk_10khz;
uint32_t ctf_threshold_override_value;
uint32_t syspll3_0_vco_freq_10khz;
uint32_t syspll3_1_vco_freq_10khz;
uint32_t bootup_fclk_10khz;
uint32_t bootup_waflclk_10khz;
uint32_t reserved[3];
};
/*
***************************************************************************
Data Table smc_dpm_info structure
@ -1283,7 +1401,6 @@ struct atom_smc_dpm_info_v4_1
uint32_t boardreserved[10];
};
/*
***************************************************************************
Data Table asic_profiling_info structure
@ -1864,6 +1981,55 @@ enum atom_smu9_syspll0_clock_id
SMU9_SYSPLL0_DISPCLK_ID = 11, // DISPCLK
};
enum atom_smu11_syspll_id {
SMU11_SYSPLL0_ID = 0,
SMU11_SYSPLL1_0_ID = 1,
SMU11_SYSPLL1_1_ID = 2,
SMU11_SYSPLL1_2_ID = 3,
SMU11_SYSPLL2_ID = 4,
SMU11_SYSPLL3_0_ID = 5,
SMU11_SYSPLL3_1_ID = 6,
};
enum atom_smu11_syspll0_clock_id {
SMU11_SYSPLL0_SOCCLK_ID = 0, // SOCCLK
SMU11_SYSPLL0_MP0CLK_ID = 1, // MP0CLK
SMU11_SYSPLL0_DCLK_ID = 2, // DCLK
SMU11_SYSPLL0_VCLK_ID = 3, // VCLK
SMU11_SYSPLL0_ECLK_ID = 4, // ECLK
SMU11_SYSPLL0_DCEFCLK_ID = 5, // DCEFCLK
};
enum atom_smu11_syspll1_0_clock_id {
SMU11_SYSPLL1_0_UCLKA_ID = 0, // UCLK_a
};
enum atom_smu11_syspll1_1_clock_id {
SMU11_SYSPLL1_0_UCLKB_ID = 0, // UCLK_b
};
enum atom_smu11_syspll1_2_clock_id {
SMU11_SYSPLL1_0_FCLK_ID = 0, // FCLK
};
enum atom_smu11_syspll2_clock_id {
SMU11_SYSPLL2_GFXCLK_ID = 0, // GFXCLK
};
enum atom_smu11_syspll3_0_clock_id {
SMU11_SYSPLL3_0_WAFCLK_ID = 0, // WAFCLK
SMU11_SYSPLL3_0_DISPCLK_ID = 1, // DISPCLK
SMU11_SYSPLL3_0_DPREFCLK_ID = 2, // DPREFCLK
};
enum atom_smu11_syspll3_1_clock_id {
SMU11_SYSPLL3_1_MP1CLK_ID = 0, // MP1CLK
SMU11_SYSPLL3_1_SMNCLK_ID = 1, // SMNCLK
SMU11_SYSPLL3_1_LCLK_ID = 2, // LCLK
};
struct atom_get_smu_clock_info_output_parameters_v3_1
{
union {

52
drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
View File

@ -79,12 +79,13 @@
#define PCIE_BUS_CLK 10000
#define TCLK (PCIE_BUS_CLK / 10)
static const struct profile_mode_setting smu7_profiling[5] =
static const struct profile_mode_setting smu7_profiling[6] =
{{1, 0, 100, 30, 1, 0, 100, 10},
{1, 10, 0, 30, 0, 0, 0, 0},
{0, 0, 0, 0, 1, 10, 16, 31},
{1, 0, 11, 50, 1, 0, 100, 10},
{1, 0, 5, 30, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
};
/** Values for the CG_THERMAL_CTRL::DPM_EVENT_SRC field. */
@ -4864,6 +4865,17 @@ static int smu7_get_power_profile_mode(struct pp_hwmgr *hwmgr, char *buf)
len = sizeof(smu7_profiling) / sizeof(struct profile_mode_setting);
for (i = 0; i < len; i++) {
if (i == hwmgr->power_profile_mode) {
size += sprintf(buf + size, "%3d %14s %s: %8d %16d %16d %16d %16d %16d\n",
i, profile_name[i], "*",
data->current_profile_setting.sclk_up_hyst,
data->current_profile_setting.sclk_down_hyst,
data->current_profile_setting.sclk_activity,
data->current_profile_setting.mclk_up_hyst,
data->current_profile_setting.mclk_down_hyst,
data->current_profile_setting.mclk_activity);
continue;
}
if (smu7_profiling[i].bupdate_sclk)
size += sprintf(buf + size, "%3d %16s: %8d %16d %16d ",
i, profile_name[i], smu7_profiling[i].sclk_up_hyst,
@ -4883,24 +4895,6 @@ static int smu7_get_power_profile_mode(struct pp_hwmgr *hwmgr, char *buf)
"-", "-", "-");
}
size += sprintf(buf + size, "%3d %16s: %8d %16d %16d %16d %16d %16d\n",
i, profile_name[i],
data->custom_profile_setting.sclk_up_hyst,
data->custom_profile_setting.sclk_down_hyst,
data->custom_profile_setting.sclk_activity,
data->custom_profile_setting.mclk_up_hyst,
data->custom_profile_setting.mclk_down_hyst,
data->custom_profile_setting.mclk_activity);
size += sprintf(buf + size, "%3s %16s: %8d %16d %16d %16d %16d %16d\n",
"*", "CURRENT",
data->current_profile_setting.sclk_up_hyst,
data->current_profile_setting.sclk_down_hyst,
data->current_profile_setting.sclk_activity,
data->current_profile_setting.mclk_up_hyst,
data->current_profile_setting.mclk_down_hyst,
data->current_profile_setting.mclk_activity);
return size;
}
@ -4939,16 +4933,16 @@ static int smu7_set_power_profile_mode(struct pp_hwmgr *hwmgr, long *input, uint
if (size < 8)
return -EINVAL;
data->custom_profile_setting.bupdate_sclk = input[0];
data->custom_profile_setting.sclk_up_hyst = input[1];
data->custom_profile_setting.sclk_down_hyst = input[2];
data->custom_profile_setting.sclk_activity = input[3];
data->custom_profile_setting.bupdate_mclk = input[4];
data->custom_profile_setting.mclk_up_hyst = input[5];
data->custom_profile_setting.mclk_down_hyst = input[6];
data->custom_profile_setting.mclk_activity = input[7];
if (!smum_update_dpm_settings(hwmgr, &data->custom_profile_setting)) {
memcpy(&data->current_profile_setting, &data->custom_profile_setting, sizeof(struct profile_mode_setting));
tmp.bupdate_sclk = input[0];
tmp.sclk_up_hyst = input[1];
tmp.sclk_down_hyst = input[2];
tmp.sclk_activity = input[3];
tmp.bupdate_mclk = input[4];
tmp.mclk_up_hyst = input[5];
tmp.mclk_down_hyst = input[6];
tmp.mclk_activity = input[7];
if (!smum_update_dpm_settings(hwmgr, &tmp)) {
memcpy(&data->current_profile_setting, &tmp, sizeof(struct profile_mode_setting));
hwmgr->power_profile_mode = mode;
}
break;

1
drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h
View File

@ -325,7 +325,6 @@ struct smu7_hwmgr {
uint16_t mem_latency_high;
uint16_t mem_latency_low;
uint32_t vr_config;
struct profile_mode_setting custom_profile_setting;
struct profile_mode_setting current_profile_setting;
};

11
drivers/gpu/drm/ttm/ttm_page_alloc.c
View File

@ -910,7 +910,8 @@ static int ttm_get_pages(struct page **pages, unsigned npages, int flags,
while (npages >= HPAGE_PMD_NR) {
gfp_t huge_flags = gfp_flags;
huge_flags |= GFP_TRANSHUGE;
huge_flags |= GFP_TRANSHUGE_LIGHT | __GFP_NORETRY |
__GFP_KSWAPD_RECLAIM;
huge_flags &= ~__GFP_MOVABLE;
huge_flags &= ~__GFP_COMP;
p = alloc_pages(huge_flags, HPAGE_PMD_ORDER);
@ -1027,11 +1028,15 @@ int ttm_page_alloc_init(struct ttm_mem_global *glob, unsigned max_pages)
GFP_USER | GFP_DMA32, "uc dma", 0);
ttm_page_pool_init_locked(&_manager->wc_pool_huge,
GFP_TRANSHUGE & ~(__GFP_MOVABLE | __GFP_COMP),
(GFP_TRANSHUGE_LIGHT | __GFP_NORETRY |
__GFP_KSWAPD_RECLAIM) &
~(__GFP_MOVABLE | __GFP_COMP),
"wc huge", order);
ttm_page_pool_init_locked(&_manager->uc_pool_huge,
GFP_TRANSHUGE & ~(__GFP_MOVABLE | __GFP_COMP)
(GFP_TRANSHUGE_LIGHT | __GFP_NORETRY |
__GFP_KSWAPD_RECLAIM) &
~(__GFP_MOVABLE | __GFP_COMP)
, "uc huge", order);
_manager->options.max_size = max_pages;

3
drivers/gpu/drm/ttm/ttm_page_alloc_dma.c
View File

@ -910,7 +910,8 @@ static gfp_t ttm_dma_pool_gfp_flags(struct ttm_dma_tt *ttm_dma, bool huge)
gfp_flags |= __GFP_ZERO;
if (huge) {
gfp_flags |= GFP_TRANSHUGE;
gfp_flags |= GFP_TRANSHUGE_LIGHT | __GFP_NORETRY |
__GFP_KSWAPD_RECLAIM;
gfp_flags &= ~__GFP_MOVABLE;
gfp_flags &= ~__GFP_COMP;
}