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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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ARM: shmobile: r8a7779: move r8a7779_init_irq_xxx() to setup
This patch moves r8a7779_init_irq_xxx() to setup code, and remove intc-r8a7779. Now, r8a7779_init_irq_extpin() uses platform_device_register_resndata() instead of platform_device_register() Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This commit is contained in:
Kuninori Morimoto
Simon Horman
parent
70e3f3d4f4
commit
5b3859d7b2
@ -11,7 +11,7 @@ obj-$(CONFIG_ARCH_SH73A0) += setup-sh73a0.o clock-sh73a0.o intc-sh73a0.o
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obj-$(CONFIG_ARCH_R8A73A4) += setup-r8a73a4.o clock-r8a73a4.o
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obj-$(CONFIG_ARCH_R8A7740) += setup-r8a7740.o clock-r8a7740.o
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obj-$(CONFIG_ARCH_R8A7778) += setup-r8a7778.o clock-r8a7778.o
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obj-$(CONFIG_ARCH_R8A7779) += setup-r8a7779.o clock-r8a7779.o intc-r8a7779.o
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obj-$(CONFIG_ARCH_R8A7779) += setup-r8a7779.o clock-r8a7779.o
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obj-$(CONFIG_ARCH_R8A7790) += setup-r8a7790.o clock-r8a7790.o
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obj-$(CONFIG_ARCH_EMEV2) += setup-emev2.o clock-emev2.o
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@ -1,116 +0,0 @@
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/*
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* r8a7779 processor support - INTC hardware block
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*
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* Copyright (C) 2011 Renesas Solutions Corp.
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* Copyright (C) 2011 Magnus Damm
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/platform_device.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/io.h>
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#include <linux/irqchip/arm-gic.h>
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#include <linux/platform_data/irq-renesas-intc-irqpin.h>
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#include <linux/irqchip.h>
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#include <mach/common.h>
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#include <mach/irqs.h>
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#include <mach/r8a7779.h>
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#include <asm/mach-types.h>
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#include <asm/mach/arch.h>
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#define INT2SMSKCR0 IOMEM(0xfe7822a0)
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#define INT2SMSKCR1 IOMEM(0xfe7822a4)
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#define INT2SMSKCR2 IOMEM(0xfe7822a8)
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#define INT2SMSKCR3 IOMEM(0xfe7822ac)
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#define INT2SMSKCR4 IOMEM(0xfe7822b0)
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#define INT2NTSR0 IOMEM(0xfe700060)
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#define INT2NTSR1 IOMEM(0xfe700064)
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static struct renesas_intc_irqpin_config irqpin0_platform_data = {
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.irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */
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.sense_bitfield_width = 2,
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};
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static struct resource irqpin0_resources[] = {
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DEFINE_RES_MEM(0xfe78001c, 4), /* ICR1 */
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DEFINE_RES_MEM(0xfe780010, 4), /* INTPRI */
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DEFINE_RES_MEM(0xfe780024, 4), /* INTREQ */
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DEFINE_RES_MEM(0xfe780044, 4), /* INTMSK0 */
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DEFINE_RES_MEM(0xfe780064, 4), /* INTMSKCLR0 */
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DEFINE_RES_IRQ(gic_spi(27)), /* IRQ0 */
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DEFINE_RES_IRQ(gic_spi(28)), /* IRQ1 */
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DEFINE_RES_IRQ(gic_spi(29)), /* IRQ2 */
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DEFINE_RES_IRQ(gic_spi(30)), /* IRQ3 */
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};
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static struct platform_device irqpin0_device = {
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.name = "renesas_intc_irqpin",
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.id = 0,
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.resource = irqpin0_resources,
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.num_resources = ARRAY_SIZE(irqpin0_resources),
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.dev = {
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.platform_data = &irqpin0_platform_data,
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},
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};
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void __init r8a7779_init_irq_extpin(int irlm)
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{
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void __iomem *icr0 = ioremap_nocache(0xfe780000, PAGE_SIZE);
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unsigned long tmp;
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if (icr0) {
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tmp = ioread32(icr0);
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if (irlm)
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tmp |= 1 << 23; /* IRQ0 -> IRQ3 as individual pins */
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else
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tmp &= ~(1 << 23); /* IRL mode - not supported */
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tmp |= (1 << 21); /* LVLMODE = 1 */
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iowrite32(tmp, icr0);
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iounmap(icr0);
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if (irlm)
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platform_device_register(&irqpin0_device);
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} else
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pr_warn("r8a7779: unable to setup external irq pin mode\n");
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}
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#ifdef CONFIG_OF
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static int r8a7779_set_wake(struct irq_data *data, unsigned int on)
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{
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return 0; /* always allow wakeup */
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}
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void __init r8a7779_init_irq_dt(void)
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{
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gic_arch_extn.irq_set_wake = r8a7779_set_wake;
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irqchip_init();
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/* route all interrupts to ARM */
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__raw_writel(0xffffffff, INT2NTSR0);
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__raw_writel(0x3fffffff, INT2NTSR1);
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/* unmask all known interrupts in INTCS2 */
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__raw_writel(0xfffffff0, INT2SMSKCR0);
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__raw_writel(0xfff7ffff, INT2SMSKCR1);
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__raw_writel(0xfffbffdf, INT2SMSKCR2);
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__raw_writel(0xbffffffc, INT2SMSKCR3);
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__raw_writel(0x003fee3f, INT2SMSKCR4);
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}
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#endif
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@ -22,8 +22,11 @@
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/irqchip.h>
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#include <linux/irqchip/arm-gic.h>
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#include <linux/of_platform.h>
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#include <linux/platform_data/gpio-rcar.h>
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#include <linux/platform_data/irq-renesas-intc-irqpin.h>
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#include <linux/platform_device.h>
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#include <linux/delay.h>
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#include <linux/input.h>
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@ -67,6 +70,60 @@ void __init r8a7779_map_io(void)
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iotable_init(r8a7779_io_desc, ARRAY_SIZE(r8a7779_io_desc));
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}
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/* IRQ */
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#define INT2SMSKCR0 IOMEM(0xfe7822a0)
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#define INT2SMSKCR1 IOMEM(0xfe7822a4)
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#define INT2SMSKCR2 IOMEM(0xfe7822a8)
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#define INT2SMSKCR3 IOMEM(0xfe7822ac)
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#define INT2SMSKCR4 IOMEM(0xfe7822b0)
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#define INT2NTSR0 IOMEM(0xfe700060)
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#define INT2NTSR1 IOMEM(0xfe700064)
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static struct renesas_intc_irqpin_config irqpin0_platform_data __initdata = {
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.irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */
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.sense_bitfield_width = 2,
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};
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static struct resource irqpin0_resources[] __initdata = {
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DEFINE_RES_MEM(0xfe78001c, 4), /* ICR1 */
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DEFINE_RES_MEM(0xfe780010, 4), /* INTPRI */
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DEFINE_RES_MEM(0xfe780024, 4), /* INTREQ */
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DEFINE_RES_MEM(0xfe780044, 4), /* INTMSK0 */
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DEFINE_RES_MEM(0xfe780064, 4), /* INTMSKCLR0 */
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DEFINE_RES_IRQ(gic_spi(27)), /* IRQ0 */
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DEFINE_RES_IRQ(gic_spi(28)), /* IRQ1 */
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DEFINE_RES_IRQ(gic_spi(29)), /* IRQ2 */
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DEFINE_RES_IRQ(gic_spi(30)), /* IRQ3 */
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};
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void __init r8a7779_init_irq_extpin(int irlm)
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{
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void __iomem *icr0 = ioremap_nocache(0xfe780000, PAGE_SIZE);
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u32 tmp;
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if (!icr0) {
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pr_warn("r8a7779: unable to setup external irq pin mode\n");
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return;
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}
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tmp = ioread32(icr0);
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if (irlm)
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tmp |= 1 << 23; /* IRQ0 -> IRQ3 as individual pins */
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else
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tmp &= ~(1 << 23); /* IRL mode - not supported */
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tmp |= (1 << 21); /* LVLMODE = 1 */
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iowrite32(tmp, icr0);
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iounmap(icr0);
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if (irlm)
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platform_device_register_resndata(
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&platform_bus, "renesas_intc_irqpin", -1,
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irqpin0_resources, ARRAY_SIZE(irqpin0_resources),
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&irqpin0_platform_data, sizeof(irqpin0_platform_data));
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}
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/* PFC/GPIO */
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static struct resource r8a7779_pfc_resources[] = {
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DEFINE_RES_MEM(0xfffc0000, 0x023c),
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};
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@ -641,6 +698,29 @@ void __init r8a7779_init_late(void)
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}
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#ifdef CONFIG_USE_OF
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static int r8a7779_set_wake(struct irq_data *data, unsigned int on)
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{
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return 0; /* always allow wakeup */
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}
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void __init r8a7779_init_irq_dt(void)
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{
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gic_arch_extn.irq_set_wake = r8a7779_set_wake;
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irqchip_init();
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/* route all interrupts to ARM */
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__raw_writel(0xffffffff, INT2NTSR0);
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__raw_writel(0x3fffffff, INT2NTSR1);
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/* unmask all known interrupts in INTCS2 */
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__raw_writel(0xfffffff0, INT2SMSKCR0);
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__raw_writel(0xfff7ffff, INT2SMSKCR1);
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__raw_writel(0xfffbffdf, INT2SMSKCR2);
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__raw_writel(0xbffffffc, INT2SMSKCR3);
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__raw_writel(0x003fee3f, INT2SMSKCR4);
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}
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void __init r8a7779_init_delay(void)
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{
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shmobile_setup_delay(1000, 2, 4); /* Cortex-A9 @ 1000MHz */
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