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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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drm/amd/display: Implement input gamma LUT
1. Implemented dcn10_ipp_program_input_lut(), following the existing interface. 2. Added missing registers as needed 3. Change to REG_GET for *ram_select() funcs. 4. Removed gamma table init from DiagsDM::make_surface() for resolving CRC errors. Reason: Legacy LUT will be deprecated soon for Raven in favor of degamma/regamma. Signed-off-by: Leo (Sunpeng) Li <sunpeng.li@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Leo (Sunpeng) Li
Alex Deucher
parent
98489c026e
commit
5aff86c1b3
@ -29,9 +29,9 @@
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#include "core_types.h"
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#include "core_status.h"
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#include "resource.h"
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#include "hw_sequencer.h"
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#include "dcn10_hw_sequencer.h"
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#include "dce110/dce110_hw_sequencer.h"
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#include "dce/dce_hwseq.h"
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#include "abm.h"
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#include "dcn10/dcn10_transform.h"
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@ -952,6 +952,10 @@ static bool dcn10_set_input_transfer_func(
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if (surface->public.in_transfer_func)
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tf = DC_TRANSFER_FUNC_TO_CORE(surface->public.in_transfer_func);
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if (surface->public.gamma_correction && dce_use_lut(surface))
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ipp->funcs->ipp_program_input_lut(ipp,
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surface->public.gamma_correction);
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if (tf == NULL)
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ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_BYPASS);
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else if (tf->public.type == TF_TYPE_PREDEFINED) {
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@ -814,7 +814,9 @@ static bool dcn10_degamma_ram_inuse(struct input_pixel_processor *ipp,
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uint32_t status_reg = 0;
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struct dcn10_ipp *ippn10 = TO_DCN10_IPP(ipp);
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status_reg = (REG_READ(CM_IGAM_LUT_RW_CONTROL) & 0x0F00) >>16;
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REG_GET(CM_IGAM_LUT_RW_CONTROL, CM_IGAM_DGAM_CONFIG_STATUS,
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&status_reg);
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if (status_reg == 9) {
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*ram_a_inuse = true;
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ret = true;
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@ -825,6 +827,28 @@ static bool dcn10_degamma_ram_inuse(struct input_pixel_processor *ipp,
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return ret;
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}
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static bool dcn10_ingamma_ram_inuse(struct input_pixel_processor *ipp,
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bool *ram_a_inuse)
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{
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bool in_use = false;
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uint32_t status_reg = 0;
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struct dcn10_ipp *ippn10 = TO_DCN10_IPP(ipp);
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REG_GET(CM_IGAM_LUT_RW_CONTROL, CM_IGAM_DGAM_CONFIG_STATUS,
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&status_reg);
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// 1 => IGAM_RAMA, 3 => IGAM_RAMA & DGAM_ROMA, 4 => IGAM_RAMA & DGAM_ROMB
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if (status_reg == 1 || status_reg == 3 || status_reg == 4) {
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*ram_a_inuse = true;
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in_use = true;
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// 2 => IGAM_RAMB, 5 => IGAM_RAMB & DGAM_ROMA, 6 => IGAM_RAMB & DGAM_ROMB
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} else if (status_reg == 2 || status_reg == 5 || status_reg == 6) {
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*ram_a_inuse = false;
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in_use = true;
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}
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return in_use;
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}
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static void dcn10_degamma_ram_select(struct input_pixel_processor *ipp,
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bool use_ram_a)
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{
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@ -855,6 +879,61 @@ static void dcn10_ipp_set_degamma_pwl(struct input_pixel_processor *ipp,
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dcn10_degamma_ram_select(ipp, !is_ram_a);
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}
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/*
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* Input gamma LUT currently supports 256 values only. This means input color
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* can have a maximum of 8 bits per channel (= 256 possible values) in order to
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* have a one-to-one mapping with the LUT. Truncation will occur with color
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* values greater than 8 bits.
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*
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* In the future, this function should support additional input gamma methods,
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* such as piecewise linear mapping, and input gamma bypass.
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*/
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void dcn10_ipp_program_input_lut(
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struct input_pixel_processor *ipp,
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const struct dc_gamma *gamma)
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{
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int i;
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struct dcn10_ipp *ippn10 = TO_DCN10_IPP(ipp);
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bool rama_occupied = false;
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uint32_t ram_num;
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// Power on LUT memory.
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REG_SET(CM_MEM_PWR_CTRL, 0, SHARED_MEM_PWR_DIS, 1);
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dcn10_ipp_enable_cm_block(ipp);
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// Determine whether to use RAM A or RAM B
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dcn10_ingamma_ram_inuse(ipp, &rama_occupied);
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if (!rama_occupied)
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REG_UPDATE(CM_IGAM_LUT_RW_CONTROL, CM_IGAM_LUT_SEL, 0);
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else
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REG_UPDATE(CM_IGAM_LUT_RW_CONTROL, CM_IGAM_LUT_SEL, 1);
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// RW mode is 256-entry LUT
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REG_UPDATE(CM_IGAM_LUT_RW_CONTROL, CM_IGAM_LUT_RW_MODE, 0);
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// IGAM Input format should be 8 bits per channel.
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REG_UPDATE(CM_IGAM_CONTROL, CM_IGAM_INPUT_FORMAT, 0);
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// Do not mask any R,G,B values
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REG_UPDATE(CM_IGAM_LUT_RW_CONTROL, CM_IGAM_LUT_WRITE_EN_MASK, 7);
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// LUT-256, unsigned, integer, new u0.12 format
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REG_UPDATE_3(
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CM_IGAM_CONTROL,
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CM_IGAM_LUT_FORMAT_R, 3,
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CM_IGAM_LUT_FORMAT_G, 3,
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CM_IGAM_LUT_FORMAT_B, 3);
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// Start at index 0 of IGAM LUT
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REG_UPDATE(CM_IGAM_LUT_RW_INDEX, CM_IGAM_LUT_RW_INDEX, 0);
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for (i = 0; i < INPUT_LUT_ENTRIES; i++) {
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REG_SET(CM_IGAM_LUT_SEQ_COLOR, 0, CM_IGAM_LUT_SEQ_COLOR,
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gamma->red[i]);
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REG_SET(CM_IGAM_LUT_SEQ_COLOR, 0, CM_IGAM_LUT_SEQ_COLOR,
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gamma->green[i]);
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REG_SET(CM_IGAM_LUT_SEQ_COLOR, 0, CM_IGAM_LUT_SEQ_COLOR,
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gamma->blue[i]);
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}
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// Power off LUT memory
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REG_SET(CM_MEM_PWR_CTRL, 0, SHARED_MEM_PWR_DIS, 0);
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// Enable IGAM LUT on ram we just wrote to. 2 => RAMA, 3 => RAMB
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REG_UPDATE(CM_IGAM_CONTROL, CM_IGAM_LUT_MODE, rama_occupied ? 3 : 2);
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REG_GET(CM_IGAM_CONTROL, CM_IGAM_LUT_MODE, &ram_num);
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}
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/*****************************************/
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/* Constructor, Destructor */
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/*****************************************/
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@ -869,6 +948,7 @@ static const struct ipp_funcs dcn10_ipp_funcs = {
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.ipp_cursor_set_attributes = dcn10_cursor_set_attributes,
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.ipp_cursor_set_position = dcn10_cursor_set_position,
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.ipp_set_degamma = dcn10_ipp_set_degamma,
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.ipp_program_input_lut = dcn10_ipp_program_input_lut,
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.ipp_full_bypass = dcn10_ipp_full_bypass,
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.ipp_setup = dcn10_ipp_cnv_setup,
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.ipp_program_degamma_pwl = dcn10_ipp_set_degamma_pwl,
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@ -87,6 +87,8 @@
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SRI(CM_DGAM_RAMA_REGION_14_15, CM, id), \
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SRI(CM_MEM_PWR_CTRL, CM, id), \
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SRI(CM_IGAM_LUT_RW_CONTROL, CM, id), \
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SRI(CM_IGAM_LUT_RW_INDEX, CM, id), \
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SRI(CM_IGAM_LUT_SEQ_COLOR, CM, id), \
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SRI(CM_DGAM_LUT_WRITE_EN_MASK, CM, id), \
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SRI(CM_DGAM_LUT_INDEX, CM, id), \
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SRI(CM_DGAM_LUT_DATA, CM, id), \
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@ -238,7 +240,13 @@
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IPP_SF(CM0_CM_DGAM_RAMA_REGION_14_15, CM_DGAM_RAMA_EXP_REGION15_LUT_OFFSET, mask_sh), \
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IPP_SF(CM0_CM_DGAM_RAMA_REGION_14_15, CM_DGAM_RAMA_EXP_REGION15_NUM_SEGMENTS, mask_sh), \
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IPP_SF(CM0_CM_MEM_PWR_CTRL, SHARED_MEM_PWR_DIS, mask_sh), \
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IPP_SF(CM0_CM_IGAM_LUT_RW_CONTROL, CM_IGAM_DGAM_CONFIG_STATUS, mask_sh), \
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IPP_SF(CM0_CM_IGAM_LUT_RW_CONTROL, CM_IGAM_LUT_HOST_EN, mask_sh), \
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IPP_SF(CM0_CM_IGAM_LUT_RW_CONTROL, CM_IGAM_LUT_RW_MODE, mask_sh), \
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IPP_SF(CM0_CM_IGAM_LUT_RW_CONTROL, CM_IGAM_LUT_SEL, mask_sh), \
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IPP_SF(CM0_CM_IGAM_LUT_RW_CONTROL, CM_IGAM_LUT_WRITE_EN_MASK, mask_sh), \
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IPP_SF(CM0_CM_IGAM_LUT_RW_INDEX, CM_IGAM_LUT_RW_INDEX, mask_sh), \
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IPP_SF(CM0_CM_IGAM_LUT_SEQ_COLOR, CM_IGAM_LUT_SEQ_COLOR, mask_sh), \
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IPP_SF(CM0_CM_DGAM_LUT_WRITE_EN_MASK, CM_DGAM_LUT_WRITE_EN_MASK, mask_sh), \
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IPP_SF(CM0_CM_DGAM_LUT_WRITE_EN_MASK, CM_DGAM_LUT_WRITE_SEL, mask_sh), \
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IPP_SF(CM0_CM_DGAM_LUT_INDEX, CM_DGAM_LUT_INDEX, mask_sh), \
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@ -251,6 +259,9 @@
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IPP_SF(CNVC_CFG0_FORMAT_CONTROL, FORMAT_EXPANSION_MODE, mask_sh), \
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IPP_SF(CM0_CM_DGAM_CONTROL, CM_DGAM_LUT_MODE, mask_sh), \
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IPP_SF(CM0_CM_IGAM_CONTROL, CM_IGAM_LUT_MODE, mask_sh), \
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IPP_SF(CM0_CM_IGAM_CONTROL, CM_IGAM_LUT_FORMAT_R, mask_sh), \
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IPP_SF(CM0_CM_IGAM_CONTROL, CM_IGAM_LUT_FORMAT_G, mask_sh), \
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IPP_SF(CM0_CM_IGAM_CONTROL, CM_IGAM_LUT_FORMAT_B, mask_sh), \
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IPP_SF(HUBPREQ0_CURSOR_SETTINS, CURSOR0_DST_Y_OFFSET, mask_sh), \
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IPP_SF(HUBPREQ0_CURSOR_SETTINS, CURSOR0_CHUNK_HDL_ADJUST, mask_sh), \
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IPP_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_MODE, mask_sh), \
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@ -404,7 +415,16 @@
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type CM_DGAM_RAMA_EXP_REGION15_LUT_OFFSET; \
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type CM_DGAM_RAMA_EXP_REGION15_NUM_SEGMENTS; \
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type SHARED_MEM_PWR_DIS; \
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type CM_IGAM_LUT_FORMAT_R; \
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type CM_IGAM_LUT_FORMAT_G; \
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type CM_IGAM_LUT_FORMAT_B; \
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type CM_IGAM_LUT_HOST_EN; \
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type CM_IGAM_LUT_RW_INDEX; \
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type CM_IGAM_LUT_RW_MODE; \
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type CM_IGAM_LUT_WRITE_EN_MASK; \
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type CM_IGAM_LUT_SEL; \
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type CM_IGAM_LUT_SEQ_COLOR; \
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type CM_IGAM_DGAM_CONFIG_STATUS; \
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type CM_DGAM_LUT_WRITE_EN_MASK; \
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type CM_DGAM_LUT_WRITE_SEL; \
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type CM_DGAM_LUT_INDEX; \
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@ -507,6 +527,8 @@ struct dcn10_ipp_registers {
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uint32_t CM_DGAM_RAMA_REGION_14_15;
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uint32_t CM_MEM_PWR_CTRL;
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uint32_t CM_IGAM_LUT_RW_CONTROL;
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uint32_t CM_IGAM_LUT_RW_INDEX;
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uint32_t CM_IGAM_LUT_SEQ_COLOR;
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uint32_t CM_DGAM_LUT_WRITE_EN_MASK;
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uint32_t CM_DGAM_LUT_INDEX;
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uint32_t CM_DGAM_LUT_DATA;
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