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drm/i915: align vlv forcewake with common lore
For some odd reasons, the vlv forcewake code is rather different from all other platforms, with no clear justification. Adjust things: - Don't check whether the gt is awake already (and bail out early), we need to grab a forcewake anyway. Otherwise the chip might go to sleep too early. And this would also screw up our forcewake accounting. - Like all other platforms, check whether the gt has cleared the forcewake bit in the _ACK register before setting it again. - Use _MASKED_BIT_ENABLE/DISABLE macros - Only use bit0 of the forcewake reg, not all 16 bits. - check the gtfifodb reg like on all other platforms in _put. - Drop the POSTING_READs for consistency. v2: Failure to git add ... again. v3: Fixup the spelling fail a bit. Tested-by: "Purushothaman, Vijay A" <vijay.a.purushothaman@intel.com> Tested-by: "Widawsky, Benjamin" <benjamin.widawsky@intel.com> Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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@ -4069,12 +4069,10 @@ int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
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static void vlv_force_wake_get(struct drm_i915_private *dev_priv)
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{
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/* Already awake? */
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if ((I915_READ(0x130094) & 0xa1) == 0xa1)
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return;
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if (wait_for_atomic_us((I915_READ_NOTRACE(FORCEWAKE_ACK_VLV) & 1) == 0, 500))
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DRM_ERROR("Force wake wait timed out\n");
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I915_WRITE_NOTRACE(FORCEWAKE_VLV, 0xffffffff);
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POSTING_READ(FORCEWAKE_VLV);
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I915_WRITE_NOTRACE(FORCEWAKE_VLV, _MASKED_BIT_ENABLE(1));
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if (wait_for_atomic_us((I915_READ_NOTRACE(FORCEWAKE_ACK_VLV) & 1), 500))
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DRM_ERROR("Force wake wait timed out\n");
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@ -4084,9 +4082,9 @@ static void vlv_force_wake_get(struct drm_i915_private *dev_priv)
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static void vlv_force_wake_put(struct drm_i915_private *dev_priv)
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{
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I915_WRITE_NOTRACE(FORCEWAKE_VLV, 0xffff0000);
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/* FIXME: confirm VLV behavior with Punit folks */
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POSTING_READ(FORCEWAKE_VLV);
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I915_WRITE_NOTRACE(FORCEWAKE_VLV, _MASKED_BIT_DISABLE(1));
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/* The below doubles as a POSTING_READ */
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gen6_gt_check_fifodbg(dev_priv);
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}
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void intel_gt_init(struct drm_device *dev)
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