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Merge tag 'drm-intel-fixes-2015-07-09' of git://anongit.freedesktop.org/drm-intel into drm-fixes

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Pile of fixes for either 4.2 issues or cc: stable. This should fix the 2nd
kind of WARNING Linus's been seeing, please ask him to scream if that's
not the case.

* tag 'drm-intel-fixes-2015-07-09' of git://anongit.freedesktop.org/drm-intel:
  Revert "drm/i915: Allocate context objects from stolen"
  drm/i915: Declare the swizzling unknown for L-shaped configurations
  drm/i915: Use crtc_state->active in primary check_plane func
  drm/i915: Check crtc->active in intel_crtc_disable_planes
  drm/i915: Restore all GGTT VMAs on resume
  drm/i915/chv: fix HW readout of the port PLL fractional divider
This commit is contained in:
Dave Airlie 2015-07-10 15:58:43 +10:00
commit 59e7a16d60
4 changed files with 37 additions and 14 deletions
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4
drivers/gpu/drm/i915/i915_gem_context.c
View File

@ -157,9 +157,7 @@ i915_gem_alloc_context_obj(struct drm_device *dev, size_t size)
struct drm_i915_gem_object *obj;
int ret;
obj = i915_gem_object_create_stolen(dev, size);
if (obj == NULL)
obj = i915_gem_alloc_object(dev, size);
obj = i915_gem_alloc_object(dev, size);
if (obj == NULL)
return ERR_PTR(-ENOMEM);

23
drivers/gpu/drm/i915/i915_gem_gtt.c
View File

@ -2546,6 +2546,8 @@ void i915_gem_restore_gtt_mappings(struct drm_device *dev)
struct drm_i915_private *dev_priv = dev->dev_private;
struct drm_i915_gem_object *obj;
struct i915_address_space *vm;
struct i915_vma *vma;
bool flush;
i915_check_and_clear_faults(dev);
@ -2555,17 +2557,24 @@ void i915_gem_restore_gtt_mappings(struct drm_device *dev)
dev_priv->gtt.base.total,
true);
/* Cache flush objects bound into GGTT and rebind them. */
vm = &dev_priv->gtt.base;
list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
struct i915_vma *vma = i915_gem_obj_to_vma(obj,
&dev_priv->gtt.base);
if (!vma)
continue;
flush = false;
list_for_each_entry(vma, &obj->vma_list, vma_link) {
if (vma->vm != vm)
continue;
i915_gem_clflush_object(obj, obj->pin_display);
WARN_ON(i915_vma_bind(vma, obj->cache_level, PIN_UPDATE));
WARN_ON(i915_vma_bind(vma, obj->cache_level,
PIN_UPDATE));
flush = true;
}
if (flush)
i915_gem_clflush_object(obj, obj->pin_display);
}
if (INTEL_INFO(dev)->gen >= 8) {
if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev))
chv_setup_private_ppat(dev_priv);

12
drivers/gpu/drm/i915/i915_gem_tiling.c
View File

@ -183,8 +183,18 @@ i915_gem_detect_bit_6_swizzle(struct drm_device *dev)
if (IS_GEN4(dev)) {
uint32_t ddc2 = I915_READ(DCC2);
if (!(ddc2 & DCC2_MODIFIED_ENHANCED_DISABLE))
if (!(ddc2 & DCC2_MODIFIED_ENHANCED_DISABLE)) {
/* Since the swizzling may vary within an
* object, we have no idea what the swizzling
* is for any page in particular. Thus we
* cannot migrate tiled pages using the GPU,
* nor can we tell userspace what the exact
* swizzling is for any object.
*/
dev_priv->quirks |= QUIRK_PIN_SWIZZLED_PAGES;
swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
}
}
if (dcc == 0xffffffff) {

12
drivers/gpu/drm/i915/intel_display.c
View File

@ -4854,6 +4854,9 @@ static void intel_crtc_disable_planes(struct drm_crtc *crtc)
struct intel_plane *intel_plane;
int pipe = intel_crtc->pipe;
if (!intel_crtc->active)
return;
intel_crtc_wait_for_pending_flips(crtc);
intel_pre_disable_primary(crtc);
@ -7887,7 +7890,7 @@ static void chv_crtc_clock_get(struct intel_crtc *crtc,
int pipe = pipe_config->cpu_transcoder;
enum dpio_channel port = vlv_pipe_to_channel(pipe);
intel_clock_t clock;
u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
int refclk = 100000;
mutex_lock(&dev_priv->sb_lock);
@ -7895,10 +7898,13 @@ static void chv_crtc_clock_get(struct intel_crtc *crtc,
pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
mutex_unlock(&dev_priv->sb_lock);
clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
clock.m2 = (pll_dw0 & 0xff) << 22;
if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
clock.m2 |= pll_dw2 & 0x3fffff;
clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
@ -13270,7 +13276,7 @@ intel_check_primary_plane(struct drm_plane *plane,
if (ret)
return ret;
if (intel_crtc->active) {
if (crtc_state->base.active) {
struct intel_plane_state *old_state =
to_intel_plane_state(plane->state);