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sh: Update SH-X3 subtype for clkdev lookups.
Rewrite the SH-X3 proto CPU clock framework for clkdev. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This commit is contained in:
Paul Mundt
parent
68a1aed703
commit
5924ad0d86
@ -570,7 +570,7 @@ config SH_CLK_CPG
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config SH_CLK_CPG_LEGACY
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depends on SH_CLK_CPG
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def_bool y if !CPU_SUBTYPE_SH7785 && !ARCH_SHMOBILE && \
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!CPU_SUBTYPE_SH7786 && !CPU_SUBTYPE_SH7757
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!CPU_SHX3 && !CPU_SUBTYPE_SH7757
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config SH_CLK_MD
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int "CPU Mode Pin Setting"
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@ -56,7 +56,9 @@
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#define FRQCR1 0xffc40004
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#define FRQMR1 0xffc40014
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#elif defined(CONFIG_CPU_SUBTYPE_SHX3)
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#define FRQCR 0xffc00014
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#define FRQCR0 0xffc00000
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#define FRQCR1 0xffc00004
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#define FRQMR1 0xffc00014
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#else
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#define FRQCR 0xffc00000
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#define FRQCR_PSTBY 0x0200
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@ -5,7 +5,7 @@
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*
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* Copyright (C) 2006-2007 Renesas Technology Corp.
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* Copyright (C) 2006-2007 Renesas Solutions Corp.
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* Copyright (C) 2006-2007 Paul Mundt
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* Copyright (C) 2006-2010 Paul Mundt
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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@ -18,120 +18,179 @@
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#include <asm/clock.h>
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#include <asm/freq.h>
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static int ifc_divisors[] = { 1, 2, 4 ,6 };
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static int bfc_divisors[] = { 1, 1, 1, 1, 1, 12, 16, 18, 24, 32, 36, 48 };
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static int pfc_divisors[] = { 1, 1, 1, 1, 1, 1, 1, 18, 24, 32, 36, 48 };
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static int cfc_divisors[] = { 1, 1, 4, 6 };
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#define IFC_POS 28
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#define IFC_MSK 0x0003
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#define BFC_MSK 0x000f
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#define PFC_MSK 0x000f
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#define CFC_MSK 0x0003
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#define BFC_POS 16
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#define PFC_POS 0
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#define CFC_POS 20
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static void master_clk_init(struct clk *clk)
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{
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clk->rate *= pfc_divisors[(__raw_readl(FRQCR) >> PFC_POS) & PFC_MSK];
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}
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static struct clk_ops shx3_master_clk_ops = {
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.init = master_clk_init,
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};
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static unsigned long module_clk_recalc(struct clk *clk)
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{
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int idx = ((__raw_readl(FRQCR) >> PFC_POS) & PFC_MSK);
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return clk->parent->rate / pfc_divisors[idx];
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}
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static struct clk_ops shx3_module_clk_ops = {
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.recalc = module_clk_recalc,
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};
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static unsigned long bus_clk_recalc(struct clk *clk)
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{
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int idx = ((__raw_readl(FRQCR) >> BFC_POS) & BFC_MSK);
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return clk->parent->rate / bfc_divisors[idx];
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}
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static struct clk_ops shx3_bus_clk_ops = {
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.recalc = bus_clk_recalc,
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};
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static unsigned long cpu_clk_recalc(struct clk *clk)
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{
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int idx = ((__raw_readl(FRQCR) >> IFC_POS) & IFC_MSK);
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return clk->parent->rate / ifc_divisors[idx];
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}
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static struct clk_ops shx3_cpu_clk_ops = {
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.recalc = cpu_clk_recalc,
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};
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static struct clk_ops *shx3_clk_ops[] = {
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&shx3_master_clk_ops,
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&shx3_module_clk_ops,
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&shx3_bus_clk_ops,
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&shx3_cpu_clk_ops,
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};
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void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
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{
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if (idx < ARRAY_SIZE(shx3_clk_ops))
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*ops = shx3_clk_ops[idx];
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}
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static unsigned long shyway_clk_recalc(struct clk *clk)
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{
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int idx = ((__raw_readl(FRQCR) >> CFC_POS) & CFC_MSK);
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return clk->parent->rate / cfc_divisors[idx];
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}
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static struct clk_ops shx3_shyway_clk_ops = {
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.recalc = shyway_clk_recalc,
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};
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static struct clk shx3_shyway_clk = {
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.flags = CLK_ENABLE_ON_INIT,
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.ops = &shx3_shyway_clk_ops,
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};
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/*
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* Additional SHx3-specific on-chip clocks that aren't already part of the
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* clock framework
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* Default rate for the root input clock, reset this with clk_set_rate()
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* from the platform code.
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*/
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static struct clk *shx3_onchip_clocks[] = {
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&shx3_shyway_clk,
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static struct clk extal_clk = {
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.rate = 16666666,
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};
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static unsigned long pll_recalc(struct clk *clk)
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{
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/* PLL1 has a fixed x72 multiplier. */
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return clk->parent->rate * 72;
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}
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static struct clk_ops pll_clk_ops = {
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.recalc = pll_recalc,
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};
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static struct clk pll_clk = {
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.ops = &pll_clk_ops,
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.parent = &extal_clk,
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.flags = CLK_ENABLE_ON_INIT,
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};
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static struct clk *clks[] = {
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&extal_clk,
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&pll_clk,
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};
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static unsigned int div2[] = { 1, 2, 4, 6, 8, 12, 16, 18,
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24, 32, 36, 48 };
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static struct clk_div_mult_table div4_div_mult_table = {
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.divisors = div2,
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.nr_divisors = ARRAY_SIZE(div2),
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};
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static struct clk_div4_table div4_table = {
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.div_mult_table = &div4_div_mult_table,
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};
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enum { DIV4_I, DIV4_SH, DIV4_B, DIV4_DDR, DIV4_SHA, DIV4_P, DIV4_NR };
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#define DIV4(_bit, _mask, _flags) \
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SH_CLK_DIV4(&pll_clk, FRQMR1, _bit, _mask, _flags)
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struct clk div4_clks[DIV4_NR] = {
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[DIV4_P] = DIV4(0, 0x0f80, 0),
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[DIV4_SHA] = DIV4(4, 0x0ff0, 0),
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[DIV4_DDR] = DIV4(12, 0x000c, CLK_ENABLE_ON_INIT),
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[DIV4_B] = DIV4(16, 0x0fe0, CLK_ENABLE_ON_INIT),
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[DIV4_SH] = DIV4(20, 0x000c, CLK_ENABLE_ON_INIT),
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[DIV4_I] = DIV4(28, 0x000e, CLK_ENABLE_ON_INIT),
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};
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#define MSTPCR0 0xffc00030
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#define MSTPCR1 0xffc00034
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enum { MSTP027, MSTP026, MSTP025, MSTP024,
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MSTP009, MSTP008, MSTP003, MSTP002,
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MSTP001, MSTP000, MSTP119, MSTP105,
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MSTP104, MSTP_NR };
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static struct clk mstp_clks[MSTP_NR] = {
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/* MSTPCR0 */
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[MSTP027] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 27, 0),
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[MSTP026] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 26, 0),
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[MSTP025] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 25, 0),
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[MSTP024] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 24, 0),
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[MSTP009] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 9, 0),
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[MSTP008] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 8, 0),
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[MSTP003] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 3, 0),
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[MSTP002] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 2, 0),
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[MSTP001] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 1, 0),
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[MSTP000] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 0, 0),
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/* MSTPCR1 */
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[MSTP119] = SH_CLK_MSTP32(NULL, MSTPCR1, 19, 0),
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[MSTP105] = SH_CLK_MSTP32(NULL, MSTPCR1, 5, 0),
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[MSTP104] = SH_CLK_MSTP32(NULL, MSTPCR1, 4, 0),
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};
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#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
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static struct clk_lookup lookups[] = {
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/* main clocks */
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CLKDEV_CON_ID("shyway_clk", &shx3_shyway_clk),
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CLKDEV_CON_ID("extal", &extal_clk),
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CLKDEV_CON_ID("pll_clk", &pll_clk),
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/* DIV4 clocks */
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CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
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CLKDEV_CON_ID("shywaya_clk", &div4_clks[DIV4_SHA]),
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CLKDEV_CON_ID("ddr_clk", &div4_clks[DIV4_DDR]),
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CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]),
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CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
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CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
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/* MSTP32 clocks */
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{
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/* SCIF3 */
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.dev_id = "sh-sci.3",
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.con_id = "sci_fck",
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.clk = &mstp_clks[MSTP027],
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}, {
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/* SCIF2 */
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.dev_id = "sh-sci.2",
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.con_id = "sci_fck",
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.clk = &mstp_clks[MSTP026],
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}, {
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/* SCIF1 */
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.dev_id = "sh-sci.1",
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.con_id = "sci_fck",
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.clk = &mstp_clks[MSTP025],
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}, {
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/* SCIF0 */
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.dev_id = "sh-sci.0",
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.con_id = "sci_fck",
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.clk = &mstp_clks[MSTP024],
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},
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CLKDEV_CON_ID("h8ex_fck", &mstp_clks[MSTP003]),
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CLKDEV_CON_ID("csm_fck", &mstp_clks[MSTP002]),
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CLKDEV_CON_ID("fe1_fck", &mstp_clks[MSTP001]),
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CLKDEV_CON_ID("fe0_fck", &mstp_clks[MSTP000]),
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{
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/* TMU0 */
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.dev_id = "sh_tmu.0",
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.con_id = "tmu_fck",
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.clk = &mstp_clks[MSTP008],
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}, {
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/* TMU1 */
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.dev_id = "sh_tmu.1",
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.con_id = "tmu_fck",
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.clk = &mstp_clks[MSTP008],
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}, {
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/* TMU2 */
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.dev_id = "sh_tmu.2",
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.con_id = "tmu_fck",
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.clk = &mstp_clks[MSTP008],
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}, {
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/* TMU3 */
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.dev_id = "sh_tmu.3",
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.con_id = "tmu_fck",
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.clk = &mstp_clks[MSTP009],
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}, {
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/* TMU4 */
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.dev_id = "sh_tmu.4",
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.con_id = "tmu_fck",
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.clk = &mstp_clks[MSTP009],
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}, {
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/* TMU5 */
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.dev_id = "sh_tmu.5",
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.con_id = "tmu_fck",
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.clk = &mstp_clks[MSTP009],
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},
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CLKDEV_CON_ID("hudi_fck", &mstp_clks[MSTP119]),
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CLKDEV_CON_ID("dmac_11_6_fck", &mstp_clks[MSTP105]),
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CLKDEV_CON_ID("dmac_5_0_fck", &mstp_clks[MSTP104]),
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};
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int __init arch_clk_init(void)
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{
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struct clk *clk;
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int i, ret = 0;
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cpg_clk_init();
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for (i = 0; i < ARRAY_SIZE(clks); i++)
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ret |= clk_register(clks[i]);
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for (i = 0; i < ARRAY_SIZE(lookups); i++)
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clkdev_add(&lookups[i]);
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clk = clk_get(NULL, "master_clk");
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for (i = 0; i < ARRAY_SIZE(shx3_onchip_clocks); i++) {
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struct clk *clkp = shx3_onchip_clocks[i];
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clkp->parent = clk;
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ret |= clk_register(clkp);
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}
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clk_put(clk);
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clkdev_add_table(lookups, ARRAY_SIZE(lookups));
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if (!ret)
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ret = sh_clk_div4_register(div4_clks, ARRAY_SIZE(div4_clks),
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&div4_table);
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if (!ret)
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ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR);
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return ret;
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}
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