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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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rtw88: 8821c: add set channel support
8821c is capable of 2.4G and 5G. Implement rtw_chip_ops::set_channel() to set 2G and 5G channels. This includes MAC, BB and RF related settings. Reviewed-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de> Signed-off-by: Tzu-En Huang <tehuang@realtek.com> Signed-off-by: Yan-Hsuan Chuang <yhchuang@realtek.com> Signed-off-by: Kalle Valo <kvalo@codeaurora.org> Link: https://lore.kernel.org/r/20200616091625.26489-5-yhchuang@realtek.com
This commit is contained in:
Tzu-En Huang
Kalle Valo
parent
6cf2086fd0
commit
58eb40c921
@ -1326,6 +1326,10 @@ static int rtw_chip_efuse_info_setup(struct rtw_dev *rtwdev)
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efuse->share_ant = true;
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if (efuse->regd == 0xff)
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efuse->regd = 0;
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if (efuse->tx_bb_swing_setting_2g == 0xff)
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efuse->tx_bb_swing_setting_2g = 0;
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if (efuse->tx_bb_swing_setting_5g == 0xff)
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efuse->tx_bb_swing_setting_5g = 0;
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efuse->btcoex = (efuse->rf_board_option & 0xe0) == 0x20;
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efuse->ext_pa_2g = efuse->pa_type_2g & BIT(4) ? 1 : 0;
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@ -1148,6 +1148,9 @@ struct rtw_chip_info {
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const struct wiphy_wowlan_support *wowlan_stub;
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const u8 max_sched_scan_ssids;
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/* for 8821c set channel */
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u32 ch_param[3];
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/* coex paras */
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u32 coex_para_ver;
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u8 bt_desired_ver;
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@ -1527,6 +1530,8 @@ struct rtw_efuse {
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u8 apa_type;
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bool ext_pa_2g;
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bool ext_pa_5g;
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u8 tx_bb_swing_setting_2g;
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u8 tx_bb_swing_setting_5g;
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bool btcoex;
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/* bt share antenna with wifi */
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@ -97,6 +97,9 @@ static void rtw8821c_phy_set_param(struct rtw_dev *rtwdev)
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/* post init after header files config */
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rtw_write32_set(rtwdev, REG_RXPSEL, BIT_RX_PSEL_RST);
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rtwdev->chip->ch_param[0] = rtw_read32_mask(rtwdev, REG_TXSF2, MASKDWORD);
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rtwdev->chip->ch_param[1] = rtw_read32_mask(rtwdev, REG_TXSF6, MASKDWORD);
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rtwdev->chip->ch_param[2] = rtw_read32_mask(rtwdev, REG_TXFILTER, MASKDWORD);
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rtw_phy_init(rtwdev);
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}
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@ -169,6 +172,207 @@ static void rtw8821c_cfg_ldo25(struct rtw_dev *rtwdev, bool enable)
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rtw_write8(rtwdev, REG_LDO_EFUSE_CTRL + 3, ldo_pwr);
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}
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static void rtw8821c_set_channel_rf(struct rtw_dev *rtwdev, u8 channel, u8 bw)
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{
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u32 rf_reg18;
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rf_reg18 = rtw_read_rf(rtwdev, RF_PATH_A, 0x18, RFREG_MASK);
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rf_reg18 &= ~(RF18_BAND_MASK | RF18_CHANNEL_MASK | RF18_RFSI_MASK |
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RF18_BW_MASK);
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rf_reg18 |= (channel <= 14 ? RF18_BAND_2G : RF18_BAND_5G);
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rf_reg18 |= (channel & RF18_CHANNEL_MASK);
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if (channel >= 100 && channel <= 140)
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rf_reg18 |= RF18_RFSI_GE;
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else if (channel > 140)
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rf_reg18 |= RF18_RFSI_GT;
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switch (bw) {
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case RTW_CHANNEL_WIDTH_5:
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case RTW_CHANNEL_WIDTH_10:
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case RTW_CHANNEL_WIDTH_20:
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default:
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rf_reg18 |= RF18_BW_20M;
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break;
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case RTW_CHANNEL_WIDTH_40:
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rf_reg18 |= RF18_BW_40M;
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break;
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case RTW_CHANNEL_WIDTH_80:
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rf_reg18 |= RF18_BW_80M;
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break;
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}
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if (channel <= 14) {
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rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTDBG, BIT(6), 0x1);
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rtw_write_rf(rtwdev, RF_PATH_A, 0x64, 0xf, 0xf);
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} else {
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rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTDBG, BIT(6), 0x0);
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}
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rtw_write_rf(rtwdev, RF_PATH_A, 0x18, RFREG_MASK, rf_reg18);
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rtw_write_rf(rtwdev, RF_PATH_A, RF_XTALX2, BIT(19), 0);
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rtw_write_rf(rtwdev, RF_PATH_A, RF_XTALX2, BIT(19), 1);
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}
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static void rtw8821c_set_channel_rxdfir(struct rtw_dev *rtwdev, u8 bw)
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{
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if (bw == RTW_CHANNEL_WIDTH_40) {
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/* RX DFIR for BW40 */
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rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x2);
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rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x2);
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rtw_write32_mask(rtwdev, REG_TXDFIR, BIT(31), 0x0);
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rtw_write32_mask(rtwdev, REG_CHFIR, BIT(31), 0x0);
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} else if (bw == RTW_CHANNEL_WIDTH_80) {
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/* RX DFIR for BW80 */
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rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x2);
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rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x1);
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rtw_write32_mask(rtwdev, REG_TXDFIR, BIT(31), 0x0);
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rtw_write32_mask(rtwdev, REG_CHFIR, BIT(31), 0x1);
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} else {
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/* RX DFIR for BW20, BW10 and BW5 */
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rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x2);
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rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x2);
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rtw_write32_mask(rtwdev, REG_TXDFIR, BIT(31), 0x1);
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rtw_write32_mask(rtwdev, REG_CHFIR, BIT(31), 0x0);
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}
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}
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static void rtw8821c_set_channel_bb(struct rtw_dev *rtwdev, u8 channel, u8 bw,
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u8 primary_ch_idx)
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{
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u32 val32;
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if (channel <= 14) {
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rtw_write32_mask(rtwdev, REG_RXPSEL, BIT(28), 0x1);
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rtw_write32_mask(rtwdev, REG_CCK_CHECK, BIT(7), 0x0);
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rtw_write32_mask(rtwdev, REG_ENTXCCK, BIT(18), 0x0);
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rtw_write32_mask(rtwdev, REG_RXCCAMSK, 0x0000FC00, 15);
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rtw_write32_mask(rtwdev, REG_TXSCALE_A, 0xf00, 0x0);
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rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x96a);
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if (channel == 14) {
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rtw_write32_mask(rtwdev, REG_TXSF2, MASKDWORD, 0x0000b81c);
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rtw_write32_mask(rtwdev, REG_TXSF6, MASKLWORD, 0x0000);
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rtw_write32_mask(rtwdev, REG_TXFILTER, MASKDWORD, 0x00003667);
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} else {
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rtw_write32_mask(rtwdev, REG_TXSF2, MASKDWORD,
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rtwdev->chip->ch_param[0]);
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rtw_write32_mask(rtwdev, REG_TXSF6, MASKLWORD,
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rtwdev->chip->ch_param[1] & MASKLWORD);
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rtw_write32_mask(rtwdev, REG_TXFILTER, MASKDWORD,
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rtwdev->chip->ch_param[2]);
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}
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} else if (channel > 35) {
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rtw_write32_mask(rtwdev, REG_ENTXCCK, BIT(18), 0x1);
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rtw_write32_mask(rtwdev, REG_CCK_CHECK, BIT(7), 0x1);
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rtw_write32_mask(rtwdev, REG_RXPSEL, BIT(28), 0x0);
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rtw_write32_mask(rtwdev, REG_RXCCAMSK, 0x0000FC00, 15);
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if (channel >= 36 && channel <= 64)
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rtw_write32_mask(rtwdev, REG_TXSCALE_A, 0xf00, 0x1);
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else if (channel >= 100 && channel <= 144)
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rtw_write32_mask(rtwdev, REG_TXSCALE_A, 0xf00, 0x2);
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else if (channel >= 149)
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rtw_write32_mask(rtwdev, REG_TXSCALE_A, 0xf00, 0x3);
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if (channel >= 36 && channel <= 48)
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rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x494);
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else if (channel >= 52 && channel <= 64)
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rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x453);
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else if (channel >= 100 && channel <= 116)
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rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x452);
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else if (channel >= 118 && channel <= 177)
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rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x412);
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}
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switch (bw) {
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case RTW_CHANNEL_WIDTH_20:
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default:
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val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD);
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val32 &= 0xffcffc00;
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val32 |= 0x10010000;
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rtw_write32_mask(rtwdev, REG_ADCCLK, MASKDWORD, val32);
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rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x1);
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break;
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case RTW_CHANNEL_WIDTH_40:
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if (primary_ch_idx == 1)
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rtw_write32_set(rtwdev, REG_RXSB, BIT(4));
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else
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rtw_write32_clr(rtwdev, REG_RXSB, BIT(4));
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val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD);
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val32 &= 0xff3ff300;
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val32 |= 0x20020000 | ((primary_ch_idx & 0xf) << 2) |
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RTW_CHANNEL_WIDTH_40;
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rtw_write32_mask(rtwdev, REG_ADCCLK, MASKDWORD, val32);
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rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x1);
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break;
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case RTW_CHANNEL_WIDTH_80:
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val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD);
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val32 &= 0xfcffcf00;
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val32 |= 0x40040000 | ((primary_ch_idx & 0xf) << 2) |
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RTW_CHANNEL_WIDTH_80;
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rtw_write32_mask(rtwdev, REG_ADCCLK, MASKDWORD, val32);
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rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x1);
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break;
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case RTW_CHANNEL_WIDTH_5:
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val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD);
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val32 &= 0xefcefc00;
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val32 |= 0x200240;
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rtw_write32_mask(rtwdev, REG_ADCCLK, MASKDWORD, val32);
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rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x0);
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rtw_write32_mask(rtwdev, REG_ADC40, BIT(31), 0x1);
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break;
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case RTW_CHANNEL_WIDTH_10:
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val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD);
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val32 &= 0xefcefc00;
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val32 |= 0x300380;
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rtw_write32_mask(rtwdev, REG_ADCCLK, MASKDWORD, val32);
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rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x0);
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rtw_write32_mask(rtwdev, REG_ADC40, BIT(31), 0x1);
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break;
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}
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}
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static u32 rtw8821c_get_bb_swing(struct rtw_dev *rtwdev, u8 channel)
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{
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struct rtw_efuse efuse = rtwdev->efuse;
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u8 tx_bb_swing;
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u32 swing2setting[4] = {0x200, 0x16a, 0x101, 0x0b6};
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tx_bb_swing = channel <= 14 ? efuse.tx_bb_swing_setting_2g :
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efuse.tx_bb_swing_setting_5g;
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if (tx_bb_swing > 9)
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tx_bb_swing = 0;
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return swing2setting[(tx_bb_swing / 3)];
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}
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static void rtw8821c_set_channel_bb_swing(struct rtw_dev *rtwdev, u8 channel,
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u8 bw, u8 primary_ch_idx)
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{
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rtw_write32_mask(rtwdev, REG_TXSCALE_A, GENMASK(31, 21),
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rtw8821c_get_bb_swing(rtwdev, channel));
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}
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static void rtw8821c_set_channel(struct rtw_dev *rtwdev, u8 channel, u8 bw,
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u8 primary_chan_idx)
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{
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rtw8821c_set_channel_bb(rtwdev, channel, bw, primary_chan_idx);
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rtw8821c_set_channel_bb_swing(rtwdev, channel, bw, primary_chan_idx);
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rtw_set_channel_mac(rtwdev, channel, bw, primary_chan_idx);
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rtw8821c_set_channel_rf(rtwdev, channel, bw);
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rtw8821c_set_channel_rxdfir(rtwdev, bw);
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}
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static void
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rtw8821c_set_tx_power_index_by_rate(struct rtw_dev *rtwdev, u8 path, u8 rs)
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{
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@ -636,6 +840,7 @@ static struct rtw_prioq_addrs prioq_addrs_8821c = {
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static struct rtw_chip_ops rtw8821c_ops = {
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.phy_set_param = rtw8821c_phy_set_param,
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.read_efuse = rtw8821c_read_efuse,
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.set_channel = rtw8821c_set_channel,
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.mac_init = rtw8821c_mac_init,
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.read_rf = rtw_phy_read_rf,
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.write_rf = rtw_phy_write_rf_reg_sipi,
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@ -161,6 +161,7 @@ _rtw_write32s_mask(struct rtw_dev *rtwdev, u32 addr, u32 mask, u32 data)
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#define REG_ADCCLK 0x8ac
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#define REG_ADC160 0x8c4
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#define REG_ADC40 0x8c8
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#define REG_CHFIR 0x8f0
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#define REG_CDDTXP 0x93c
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#define REG_TXPSEL1 0x940
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#define REG_ACBB0 0x948
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@ -172,7 +173,9 @@ _rtw_write32s_mask(struct rtw_dev *rtwdev, u32 addr, u32 mask, u32 data)
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#define REG_TXSF6 0xa28
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#define REG_RXDESC 0xa2c
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#define REG_ENTXCCK 0xa80
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#define REG_TXFILTER 0xaac
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#define REG_AGCTR_A 0xc08
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#define REG_TXSCALE_A 0xc1c
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#define REG_TXDFIR 0xc20
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#define REG_RXIGI_A 0xc50
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#define REG_TRSW 0xca0
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@ -185,4 +188,16 @@ _rtw_write32s_mask(struct rtw_dev *rtwdev, u32 addr, u32 mask, u32 data)
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#define REG_ANTWT 0x1904
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#define REG_IQKFAILMSK 0x1bf0
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#define RF18_BAND_MASK (BIT(16) | BIT(9) | BIT(8))
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#define RF18_BAND_2G (0)
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#define RF18_BAND_5G (BIT(16) | BIT(8))
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#define RF18_CHANNEL_MASK (MASKBYTE0)
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#define RF18_RFSI_MASK (BIT(18) | BIT(17))
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#define RF18_RFSI_GE (BIT(17))
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#define RF18_RFSI_GT (BIT(18))
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#define RF18_BW_MASK (BIT(11) | BIT(10))
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#define RF18_BW_20M (BIT(11) | BIT(10))
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#define RF18_BW_40M (BIT(11))
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#define RF18_BW_80M (BIT(10))
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#endif
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