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ath9k_hw: ASPM interoperability fix for AR9380/AR9382

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There is an interoperability with AR9382/AR9380 in L1 state with a
few root complexes which can cause a hang. This is fixed by
setting some work around bits on the PCIE PHY. We fix by using
a new ini array to modify these bits when the radio is idle.

Cc: stable@kernel.org
Cc: Jack Lee <jack.lee@atheros.com>
Cc: Carl Huang <carl.huang@atheros.com>
Cc: David Quan <david.quan@atheros.com>
Cc: Nael Atallah <nael.atallah@atheros.com>
Cc: Sarvesh Shrivastava <sarvesh.shrivastava@atheros.com>
Signed-off-by: Luis R. Rodriguez <lrodriguez@atheros.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
This commit is contained in:
Luis R. Rodriguez 2011-01-13 18:19:29 -08:00 committed by John W. Linville
parent 82694f764d
commit 58c5296991
2 changed files with 3 additions and 3 deletions
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2
drivers/net/wireless/ath/ath9k/ar9003_2p2_initvals.h
View File

@ -1842,7 +1842,7 @@ static const u32 ar9300_2p2_soc_preamble[][2] = {
static const u32 ar9300PciePhy_pll_on_clkreq_disable_L1_2p2[][2] = { static const u32 ar9300PciePhy_pll_on_clkreq_disable_L1_2p2[][2] = {
/* Addr allmodes */ /* Addr allmodes */
{0x00004040, 0x08212e5e}, {0x00004040, 0x0821265e},
{0x00004040, 0x0008003b}, {0x00004040, 0x0008003b},
{0x00004044, 0x00000000}, {0x00004044, 0x00000000},
}; };

4
drivers/net/wireless/ath/ath9k/ar9003_hw.c
View File

@ -146,8 +146,8 @@ static void ar9003_hw_init_mode_regs(struct ath_hw *ah)
/* Sleep Setting */ /* Sleep Setting */
INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower, INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
ar9300PciePhy_clkreq_enable_L1_2p2, ar9300PciePhy_pll_on_clkreq_disable_L1_2p2,
ARRAY_SIZE(ar9300PciePhy_clkreq_enable_L1_2p2), ARRAY_SIZE(ar9300PciePhy_pll_on_clkreq_disable_L1_2p2),
2); 2);
/* Fast clock modal settings */ /* Fast clock modal settings */