mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-11-26 06:50:53 +07:00
This is the multi-platform support for AT91:
- reworked arch/arm/mach-at91/Kconfig and arch/arm/Kconfig to switch to multi-platform - updated at91_dt_defconfig - continue the cleanup of unneeded files and code chunks -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) iQEcBAABAgAGBQJVCv+EAAoJEAf03oE53VmQRgQIALCEppiZCt7xzH8bbGToyiSh A1lWqDFm5kvkUW9igaks1XenxcDmKg7TwLfjolyqny20CL6/rt1oap07Yt7eAIW1 6KdCKk7RML0vduX3F/wl+ZQe6ykob0vWzaeeUNI1RgBkD7hsZCb60Re1fj44pR99 dgj08EAme1yBvvFN2iA7IWUXJMPIuQ+uFzFUMiPVahgR49AbTG/TLfGHWM8i/H15 HF/ETeShV4k02lqipm4E8te0VAiDjYcrpc12NbQ0M1jFgD+1V+tY0IvrrtTcxHEe 53CCwN09nKJTRBZrPyCdKK7r4xrpPb64ZydBWXOHkVizS24jG1fc4aXG74qBooI= =uyvg -----END PGP SIGNATURE----- Merge tag 'at91-multiplatform' of git://git.kernel.org/pub/scm/linux/kernel/git/nferre/linux-at91 into next/multiplatform Merge "at91: multiplatform for 4.1 #1" from Nicolas Ferre: This is the multi-platform support for AT91: - reworked arch/arm/mach-at91/Kconfig and arch/arm/Kconfig to switch to multi-platform - updated at91_dt_defconfig - continue the cleanup of unneeded files and code chunks * tag 'at91-multiplatform' of git://git.kernel.org/pub/scm/linux/kernel/git/nferre/linux-at91: (61 commits) ARM: at91: drop AT91_TIMER_HZ ARM: at91: remove hardware.h ARM: at91: remove SoC headers ARM: at91: remove useless mach/cpu.h ARM: at91: remove unused headers ARM: at91: switch at91_dt_defconfig to multiplatform ARM: at91: switch to multiplatform ARM: at91: remove useless include clocksource: atmel-st: remove mach/hardware dependency clocksource: atmel-st: use syscon/regmap ARM: at91: time: move the system timer driver to drivers/clocksource ARM: at91: properly initialize timer ARM: at91: at91rm9200: remove deprecated arm_pm_restart watchdog: at91rm9200: implement restart handler watchdog: at91rm9200: use the system timer syscon mfd: syscon: Add atmel system timer registers definition ARM: at91/dt: declare atmel,at91rm9200-st as a syscon ARM: at91: remove old setup ARM: at91: sama5d4: remove useless map_io ARM: at91: sama5 use SoC detection infrastructure ... Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
commit
58bc2d9b16
@ -46,10 +46,12 @@ PIT Timer required properties:
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shared across all System Controller members.
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System Timer (ST) required properties:
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- compatible: Should be "atmel,at91rm9200-st"
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- compatible: Should be "atmel,at91rm9200-st", "syscon", "simple-mfd"
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- reg: Should contain registers location and length
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- interrupts: Should contain interrupt for the ST which is the IRQ line
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shared across all System Controller members.
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Its subnodes can be:
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- watchdog: compatible should be "atmel,at91rm9200-wdt"
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TC/TCLIB Timer required properties:
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- compatible: Should be "atmel,<chip>-tcb".
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@ -1,9 +1,10 @@
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* Atmel Universal Synchronous Asynchronous Receiver/Transmitter (USART)
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Required properties:
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- compatible: Should be "atmel,<chip>-usart"
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- compatible: Should be "atmel,<chip>-usart" or "atmel,<chip>-dbgu"
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The compatible <chip> indicated will be the first SoC to support an
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additional mode or an USART new feature.
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For the dbgu UART, use "atmel,<chip>-dbgu", "atmel,<chip>-usart"
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- reg: Should contain registers location and length
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- interrupts: Should contain interrupt
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- clock-names: tuple listing input clock names.
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@ -26,6 +26,11 @@ Optional properties:
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- atmel,disable : Should be present if you want to disable the watchdog.
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- atmel,idle-halt : Should be present if you want to stop the watchdog when
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entering idle state.
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CAUTION: This property should be used with care, it actually makes the
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watchdog not counting when the CPU is in idle state, therefore the
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watchdog reset time depends on mean CPU usage and will not reset at all
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if the CPU stop working while it is in idle state, which is probably
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not what you want.
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- atmel,dbg-halt : Should be present if you want to stop the watchdog when
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entering debug state.
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@ -356,19 +356,6 @@ config ARCH_VERSATILE
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help
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This enables support for ARM Ltd Versatile board.
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config ARCH_AT91
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bool "Atmel AT91"
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select ARCH_REQUIRE_GPIOLIB
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select CLKDEV_LOOKUP
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select IRQ_DOMAIN
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select NEED_MACH_IO_H if PCCARD
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select PINCTRL
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select PINCTRL_AT91
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select USE_OF
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help
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This enables support for systems based on Atmel
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AT91RM9200, AT91SAM9 and SAMA5 processors.
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config ARCH_CLPS711X
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bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
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select ARCH_REQUIRE_GPIOLIB
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@ -1514,7 +1501,7 @@ config HZ_FIXED
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int
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default 200 if ARCH_EBSA110 || ARCH_S3C24XX || \
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ARCH_S5PV210 || ARCH_EXYNOS4
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default AT91_TIMER_HZ if ARCH_AT91
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default 128 if SOC_AT91RM9200
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default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE_LEGACY
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default 0
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@ -356,9 +356,13 @@ macb0_clk: macb0_clk {
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};
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st: timer@fffffd00 {
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compatible = "atmel,at91rm9200-st";
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compatible = "atmel,at91rm9200-st", "syscon", "simple-mfd";
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reg = <0xfffffd00 0x100>;
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interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
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watchdog {
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compatible = "atmel,at91rm9200-wdt";
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};
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};
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rtc: rtc@fffffe00 {
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@ -830,7 +834,7 @@ pioD: gpio@fffffa00 {
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};
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dbgu: serial@fffff200 {
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compatible = "atmel,at91rm9200-usart";
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compatible = "atmel,at91rm9200-dbgu", "atmel,at91rm9200-usart";
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reg = <0xfffff200 0x200>;
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interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
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pinctrl-names = "default";
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@ -494,12 +494,12 @@ pinctrl_usart3: usart3-0 {
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pinctrl_usart3_rts: usart3_rts-0 {
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atmel,pins =
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<AT91_PIOB 8 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC8 periph B */
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<AT91_PIOC 8 AT91_PERIPH_B AT91_PINCTRL_NONE>;
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};
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pinctrl_usart3_cts: usart3_cts-0 {
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atmel,pins =
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<AT91_PIOB 10 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC10 periph B */
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<AT91_PIOC 10 AT91_PERIPH_B AT91_PINCTRL_NONE>;
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};
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};
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@ -753,7 +753,7 @@ pioC: gpio@fffff800 {
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};
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dbgu: serial@fffff200 {
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compatible = "atmel,at91sam9260-usart";
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compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
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reg = <0xfffff200 0x200>;
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interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
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pinctrl-names = "default";
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@ -853,7 +853,7 @@ macb0: ethernet@fffc4000 {
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};
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usb1: gadget@fffa4000 {
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compatible = "atmel,at91rm9200-udc";
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compatible = "atmel,at91sam9260-udc";
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reg = <0xfffa4000 0x4000>;
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interrupts = <10 IRQ_TYPE_LEVEL_HIGH 2>;
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clocks = <&udc_clk>, <&udpck>;
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@ -976,7 +976,6 @@ watchdog@fffffd40 {
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atmel,watchdog-type = "hardware";
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atmel,reset-type = "all";
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atmel,dbg-halt;
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atmel,idle-halt;
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status = "disabled";
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};
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@ -124,11 +124,12 @@ tcb0: timer@fffa0000 {
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};
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usb1: gadget@fffa4000 {
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compatible = "atmel,at91rm9200-udc";
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compatible = "atmel,at91sam9261-udc";
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reg = <0xfffa4000 0x4000>;
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interrupts = <10 IRQ_TYPE_LEVEL_HIGH 2>;
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clocks = <&usb>, <&udc_clk>, <&udpck>;
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clock-names = "usb_clk", "udc_clk", "udpck";
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clocks = <&udc_clk>, <&udpck>;
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clock-names = "pclk", "hclk";
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atmel,matrix = <&matrix>;
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status = "disabled";
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};
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@ -262,7 +263,7 @@ ramc: ramc@ffffea00 {
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};
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matrix: matrix@ffffee00 {
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compatible = "atmel,at91sam9260-bus-matrix";
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compatible = "atmel,at91sam9260-bus-matrix", "syscon";
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reg = <0xffffee00 0x200>;
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};
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@ -275,7 +276,7 @@ aic: interrupt-controller@fffff000 {
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};
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dbgu: serial@fffff200 {
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compatible = "atmel,at91sam9260-usart";
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compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
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reg = <0xfffff200 0x200>;
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interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
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pinctrl-names = "default";
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@ -69,7 +69,7 @@ sram0: sram@00300000 {
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sram1: sram@00500000 {
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compatible = "mmio-sram";
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reg = <0x00300000 0x4000>;
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reg = <0x00500000 0x4000>;
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};
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ahb {
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@ -762,7 +762,7 @@ pioE: gpio@fffffa00 {
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};
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dbgu: serial@ffffee00 {
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compatible = "atmel,at91sam9260-usart";
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compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
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reg = <0xffffee00 0x200>;
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interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
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pinctrl-names = "default";
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@ -856,7 +856,7 @@ macb0: ethernet@fffbc000 {
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};
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usb1: gadget@fff78000 {
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compatible = "atmel,at91rm9200-udc";
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compatible = "atmel,at91sam9263-udc";
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reg = <0xfff78000 0x4000>;
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interrupts = <24 IRQ_TYPE_LEVEL_HIGH 2>;
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clocks = <&udc_clk>, <&udpck>;
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@ -905,7 +905,6 @@ watchdog@fffffd40 {
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atmel,watchdog-type = "hardware";
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atmel,reset-type = "all";
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atmel,dbg-halt;
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atmel,idle-halt;
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status = "disabled";
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};
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@ -893,7 +893,7 @@ pioE: gpio@fffffa00 {
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};
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dbgu: serial@ffffee00 {
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compatible = "atmel,at91sam9260-usart";
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compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
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reg = <0xffffee00 0x200>;
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interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
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pinctrl-names = "default";
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@ -1116,7 +1116,6 @@ watchdog@fffffd40 {
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atmel,watchdog-type = "hardware";
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atmel,reset-type = "all";
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atmel,dbg-halt;
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atmel,idle-halt;
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status = "disabled";
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};
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@ -1301,7 +1300,7 @@ usb1: ehci@00800000 {
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compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
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reg = <0x00800000 0x100000>;
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interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
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clocks = <&usb>, <&uhphs_clk>, <&uhphs_clk>, <&uhpck>;
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clocks = <&utmi>, <&uhphs_clk>, <&uhphs_clk>, <&uhpck>;
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clock-names = "usb_clk", "ehci_clk", "hclk", "uhpck";
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status = "disabled";
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};
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@ -757,7 +757,7 @@ pioD: gpio@fffffa00 {
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};
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dbgu: serial@fffff200 {
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compatible = "atmel,at91sam9260-usart";
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compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
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reg = <0xfffff200 0x200>;
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interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
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pinctrl-names = "default";
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@ -894,7 +894,6 @@ watchdog@fffffe40 {
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atmel,watchdog-type = "hardware";
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atmel,reset-type = "all";
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atmel,dbg-halt;
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atmel,idle-halt;
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status = "disabled";
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};
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@ -377,7 +377,7 @@ aic: interrupt-controller@fffff000 {
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};
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dbgu: serial@fffff200 {
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compatible = "atmel,at91sam9260-usart";
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compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
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reg = <0xfffff200 0x200>;
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interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
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pinctrl-names = "default";
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@ -860,7 +860,7 @@ mmc1: mmc@f000c000 {
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};
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dbgu: serial@fffff200 {
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compatible = "atmel,at91sam9260-usart";
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compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
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reg = <0xfffff200 0x200>;
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interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
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pinctrl-names = "default";
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@ -1066,7 +1066,7 @@ usb2: gadget@f803c000 {
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reg = <0x00500000 0x80000
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0xf803c000 0x400>;
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interrupts = <23 IRQ_TYPE_LEVEL_HIGH 0>;
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clocks = <&usb>, <&udphs_clk>;
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clocks = <&utmi>, <&udphs_clk>;
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clock-names = "hclk", "pclk";
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status = "disabled";
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@ -1130,7 +1130,6 @@ watchdog@fffffe40 {
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atmel,watchdog-type = "hardware";
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atmel,reset-type = "all";
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atmel,dbg-halt;
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atmel,idle-halt;
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status = "disabled";
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};
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@ -1186,7 +1185,7 @@ usb1: ehci@00700000 {
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compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
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reg = <0x00700000 0x100000>;
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interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
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clocks = <&usb>, <&uhphs_clk>, <&uhpck>;
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clocks = <&utmi>, <&uhphs_clk>, <&uhpck>;
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clock-names = "usb_clk", "ehci_clk", "uhpck";
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status = "disabled";
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};
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@ -439,7 +439,7 @@ ramc0: ramc@ffffea00 {
|
||||
};
|
||||
|
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dbgu: serial@ffffee00 {
|
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compatible = "atmel,at91sam9260-usart";
|
||||
compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
|
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reg = <0xffffee00 0x200>;
|
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interrupts = <2 IRQ_TYPE_LEVEL_HIGH 7>;
|
||||
dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(13)>,
|
||||
@ -1248,7 +1248,6 @@ watchdog@fffffe40 {
|
||||
atmel,watchdog-type = "hardware";
|
||||
atmel,reset-type = "all";
|
||||
atmel,dbg-halt;
|
||||
atmel,idle-halt;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -1416,7 +1415,7 @@ usb2: ehci@00700000 {
|
||||
compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
|
||||
reg = <0x00700000 0x100000>;
|
||||
interrupts = <32 IRQ_TYPE_LEVEL_HIGH 2>;
|
||||
clocks = <&usb>, <&uhphs_clk>, <&uhpck>;
|
||||
clocks = <&utmi>, <&uhphs_clk>, <&uhpck>;
|
||||
clock-names = "usb_clk", "ehci_clk", "uhpck";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -66,6 +66,7 @@ aliases {
|
||||
gpio4 = &pioE;
|
||||
tcb0 = &tcb0;
|
||||
tcb1 = &tcb1;
|
||||
i2c0 = &i2c0;
|
||||
i2c2 = &i2c2;
|
||||
};
|
||||
cpus {
|
||||
@ -259,7 +260,7 @@ usb2: ehci@00600000 {
|
||||
compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
|
||||
reg = <0x00600000 0x100000>;
|
||||
interrupts = <46 IRQ_TYPE_LEVEL_HIGH 2>;
|
||||
clocks = <&usb>, <&uhphs_clk>, <&uhpck>;
|
||||
clocks = <&utmi>, <&uhphs_clk>, <&uhpck>;
|
||||
clock-names = "usb_clk", "ehci_clk", "uhpck";
|
||||
status = "disabled";
|
||||
};
|
||||
@ -461,8 +462,8 @@ ddrck: ddrck {
|
||||
|
||||
lcdck: lcdck {
|
||||
#clock-cells = <0>;
|
||||
reg = <4>;
|
||||
clocks = <&smd>;
|
||||
reg = <3>;
|
||||
clocks = <&mck>;
|
||||
};
|
||||
|
||||
smdck: smdck {
|
||||
@ -770,7 +771,7 @@ dma1_clk: dma1_clk {
|
||||
reg = <50>;
|
||||
};
|
||||
|
||||
lcd_clk: lcd_clk {
|
||||
lcdc_clk: lcdc_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <51>;
|
||||
};
|
||||
@ -1063,7 +1064,7 @@ rtc@fc0686b0 {
|
||||
};
|
||||
|
||||
dbgu: serial@fc069000 {
|
||||
compatible = "atmel,at91sam9260-usart";
|
||||
compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
|
||||
reg = <0xfc069000 0x200>;
|
||||
interrupts = <2 IRQ_TYPE_LEVEL_HIGH 7>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
@ -13,10 +13,13 @@ CONFIG_MODULE_UNLOAD=y
|
||||
# CONFIG_BLK_DEV_BSG is not set
|
||||
# CONFIG_IOSCHED_DEADLINE is not set
|
||||
# CONFIG_IOSCHED_CFQ is not set
|
||||
CONFIG_ARCH_MULTI_V4T=y
|
||||
CONFIG_ARCH_MULTI_V5=y
|
||||
# CONFIG_ARCH_MULTI_V7 is not set
|
||||
CONFIG_ARCH_AT91=y
|
||||
CONFIG_SOC_SAM_V4_V5=y
|
||||
CONFIG_SOC_AT91RM9200=y
|
||||
CONFIG_SOC_AT91SAM9=y
|
||||
CONFIG_AT91_TIMER_HZ=128
|
||||
CONFIG_AEABI=y
|
||||
CONFIG_UACCESS_WITH_MEMCPY=y
|
||||
CONFIG_ZBOOT_ROM_TEXT=0x0
|
||||
@ -70,6 +73,7 @@ CONFIG_SCSI=y
|
||||
CONFIG_BLK_DEV_SD=y
|
||||
# CONFIG_SCSI_LOWLEVEL is not set
|
||||
CONFIG_NETDEVICES=y
|
||||
CONFIG_ARM_AT91_ETHER=y
|
||||
CONFIG_MACB=y
|
||||
# CONFIG_NET_VENDOR_BROADCOM is not set
|
||||
CONFIG_DM9000=y
|
||||
|
||||
@ -3,8 +3,6 @@
|
||||
CONFIG_SYSVIPC=y
|
||||
CONFIG_IRQ_DOMAIN_DEBUG=y
|
||||
CONFIG_LOG_BUF_SHIFT=14
|
||||
CONFIG_SYSFS_DEPRECATED=y
|
||||
CONFIG_SYSFS_DEPRECATED_V2=y
|
||||
CONFIG_BLK_DEV_INITRD=y
|
||||
CONFIG_EMBEDDED=y
|
||||
CONFIG_SLAB=y
|
||||
|
||||
@ -18,8 +18,11 @@
|
||||
#define AT91_DBGU 0xfc00c000 /* SAMA5D4_BASE_USART3 */
|
||||
#endif
|
||||
|
||||
/* Keep in sync with mach-at91/include/mach/hardware.h */
|
||||
#ifdef CONFIG_MMU
|
||||
#define AT91_IO_P2V(x) ((x) - 0x01000000)
|
||||
#else
|
||||
#define AT91_IO_P2V(x) (x)
|
||||
#endif
|
||||
|
||||
#define AT91_DBGU_SR (0x14) /* Status Register */
|
||||
#define AT91_DBGU_THR (0x1c) /* Transmitter Holding Register */
|
||||
|
||||
@ -1,55 +1,14 @@
|
||||
if ARCH_AT91
|
||||
|
||||
config HAVE_AT91_UTMI
|
||||
bool
|
||||
|
||||
config HAVE_AT91_USB_CLK
|
||||
bool
|
||||
|
||||
config COMMON_CLK_AT91
|
||||
bool
|
||||
select COMMON_CLK
|
||||
|
||||
config HAVE_AT91_SMD
|
||||
bool
|
||||
|
||||
config HAVE_AT91_H32MX
|
||||
bool
|
||||
|
||||
config SOC_SAMA5
|
||||
bool
|
||||
select ATMEL_AIC5_IRQ
|
||||
menuconfig ARCH_AT91
|
||||
bool "Atmel SoCs"
|
||||
select ARCH_REQUIRE_GPIOLIB
|
||||
select COMMON_CLK_AT91
|
||||
select CPU_V7
|
||||
select GENERIC_CLOCKEVENTS
|
||||
select MEMORY
|
||||
select ATMEL_SDRAMC
|
||||
select PHYLIB if NETDEVICES
|
||||
select PINCTRL
|
||||
select PINCTRL_AT91
|
||||
select SOC_BUS
|
||||
|
||||
menu "Atmel AT91 System-on-Chip"
|
||||
|
||||
choice
|
||||
|
||||
prompt "Core type"
|
||||
|
||||
config SOC_SAM_V4_V5
|
||||
bool "ARM9 AT91SAM9/AT91RM9200"
|
||||
help
|
||||
Select this if you are using one of Atmel's AT91SAM9 or
|
||||
AT91RM9200 SoC.
|
||||
|
||||
config SOC_SAM_V7
|
||||
bool "Cortex A5"
|
||||
help
|
||||
Select this if you are using one of Atmel's SAMA5D3 SoC.
|
||||
|
||||
endchoice
|
||||
|
||||
comment "Atmel AT91 Processor"
|
||||
|
||||
if SOC_SAM_V7
|
||||
if ARCH_AT91
|
||||
config SOC_SAMA5D3
|
||||
bool "SAMA5D3 family"
|
||||
bool "SAMA5D3 family" if ARCH_MULTI_V7
|
||||
select SOC_SAMA5
|
||||
select HAVE_FB_ATMEL
|
||||
select HAVE_AT91_UTMI
|
||||
@ -60,9 +19,8 @@ config SOC_SAMA5D3
|
||||
This support covers SAMA5D31, SAMA5D33, SAMA5D34, SAMA5D35, SAMA5D36.
|
||||
|
||||
config SOC_SAMA5D4
|
||||
bool "SAMA5D4 family"
|
||||
bool "SAMA5D4 family" if ARCH_MULTI_V7
|
||||
select SOC_SAMA5
|
||||
select CLKSRC_MMIO
|
||||
select CACHE_L2X0
|
||||
select HAVE_FB_ATMEL
|
||||
select HAVE_AT91_UTMI
|
||||
@ -71,29 +29,31 @@ config SOC_SAMA5D4
|
||||
select HAVE_AT91_H32MX
|
||||
help
|
||||
Select this if you are using one of Atmel's SAMA5D4 family SoC.
|
||||
endif
|
||||
|
||||
if SOC_SAM_V4_V5
|
||||
config SOC_AT91RM9200
|
||||
bool "AT91RM9200"
|
||||
bool "AT91RM9200" if ARCH_MULTI_V4T
|
||||
select ATMEL_AIC_IRQ
|
||||
select COMMON_CLK_AT91
|
||||
select ATMEL_ST
|
||||
select CPU_ARM920T
|
||||
select GENERIC_CLOCKEVENTS
|
||||
select HAVE_AT91_USB_CLK
|
||||
select MIGHT_HAVE_PCI
|
||||
select SOC_SAM_V4_V5
|
||||
select SRAM if PM
|
||||
help
|
||||
Select this if you are using Atmel's AT91RM9200 SoC.
|
||||
|
||||
config SOC_AT91SAM9
|
||||
bool "AT91SAM9"
|
||||
bool "AT91SAM9" if ARCH_MULTI_V5
|
||||
select ATMEL_AIC_IRQ
|
||||
select ATMEL_SDRAMC
|
||||
select COMMON_CLK_AT91
|
||||
select CPU_ARM926T
|
||||
select GENERIC_CLOCKEVENTS
|
||||
select HAVE_AT91_SMD
|
||||
select HAVE_AT91_USB_CLK
|
||||
select HAVE_AT91_UTMI
|
||||
select HAVE_FB_ATMEL
|
||||
select MEMORY
|
||||
select SOC_SAM_V4_V5
|
||||
select SRAM if PM
|
||||
help
|
||||
Select this if you are using one of those Atmel SoC:
|
||||
AT91SAM9260
|
||||
@ -112,40 +72,35 @@ config SOC_AT91SAM9
|
||||
AT91SAM9X25
|
||||
AT91SAM9X35
|
||||
AT91SAM9XE
|
||||
endif # SOC_SAM_V4_V5
|
||||
|
||||
comment "AT91 Feature Selections"
|
||||
config HAVE_AT91_UTMI
|
||||
bool
|
||||
|
||||
config AT91_SLOW_CLOCK
|
||||
bool "Suspend-to-RAM disables main oscillator"
|
||||
select SRAM
|
||||
depends on SUSPEND
|
||||
help
|
||||
Select this if you want Suspend-to-RAM to save the most power
|
||||
possible (without powering off the CPU) by disabling the PLLs
|
||||
and main oscillator so that only the 32 KiHz clock is available.
|
||||
config HAVE_AT91_USB_CLK
|
||||
bool
|
||||
|
||||
When only that slow-clock is available, some peripherals lose
|
||||
functionality. Many can't issue wakeup events unless faster
|
||||
clocks are available. Some lose their operating state and
|
||||
need to be completely re-initialized.
|
||||
config COMMON_CLK_AT91
|
||||
bool
|
||||
select COMMON_CLK
|
||||
|
||||
config AT91_TIMER_HZ
|
||||
int "Kernel HZ (jiffies per second)"
|
||||
range 32 1024
|
||||
depends on ARCH_AT91
|
||||
default "128" if SOC_AT91RM9200
|
||||
default "100"
|
||||
help
|
||||
On AT91rm9200 chips where you're using a system clock derived
|
||||
from the 32768 Hz hardware clock, this tick rate should divide
|
||||
it exactly: use a power-of-two value, such as 128 or 256, to
|
||||
reduce timing errors caused by rounding.
|
||||
config HAVE_AT91_SMD
|
||||
bool
|
||||
|
||||
On AT91sam926x chips, or otherwise when using a higher precision
|
||||
system clock (of at least several MHz), rounding is less of a
|
||||
problem so it can be safer to use a decimal values like 100.
|
||||
config HAVE_AT91_H32MX
|
||||
bool
|
||||
|
||||
endmenu
|
||||
config SOC_SAM_V4_V5
|
||||
bool
|
||||
|
||||
config SOC_SAM_V7
|
||||
bool
|
||||
|
||||
config SOC_SAMA5
|
||||
bool
|
||||
select ATMEL_AIC5_IRQ
|
||||
select ATMEL_SDRAMC
|
||||
select MEMORY
|
||||
select SOC_SAM_V7
|
||||
select SRAM if PM
|
||||
|
||||
endif
|
||||
|
||||
@ -1,19 +1,21 @@
|
||||
#
|
||||
# Makefile for the linux kernel.
|
||||
#
|
||||
ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include
|
||||
asflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include
|
||||
|
||||
obj-y := setup.o
|
||||
obj-y := soc.o
|
||||
|
||||
obj-$(CONFIG_SOC_AT91SAM9) += sam9_smc.o
|
||||
|
||||
# CPU-specific support
|
||||
obj-$(CONFIG_SOC_AT91RM9200) += at91rm9200.o at91rm9200_time.o
|
||||
obj-$(CONFIG_SOC_AT91RM9200) += at91rm9200.o
|
||||
obj-$(CONFIG_SOC_AT91SAM9) += at91sam9.o
|
||||
obj-$(CONFIG_SOC_SAMA5) += sama5.o
|
||||
|
||||
# Power Management
|
||||
obj-$(CONFIG_PM) += pm.o
|
||||
obj-$(CONFIG_AT91_SLOW_CLOCK) += pm_slowclock.o
|
||||
obj-$(CONFIG_PM) += pm_suspend.o
|
||||
|
||||
ifeq ($(CONFIG_PM_DEBUG),y)
|
||||
CFLAGS_pm.o += -DDEBUG
|
||||
|
||||
@ -8,60 +8,42 @@
|
||||
* Licensed under GPLv2 or later.
|
||||
*/
|
||||
|
||||
#include <linux/types.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_irq.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_platform.h>
|
||||
|
||||
#include <asm/setup.h>
|
||||
#include <asm/irq.h>
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach/map.h>
|
||||
#include <asm/mach/irq.h>
|
||||
#include <asm/system_misc.h>
|
||||
|
||||
#include <mach/at91_st.h>
|
||||
|
||||
#include "generic.h"
|
||||
#include "soc.h"
|
||||
|
||||
static void at91rm9200_restart(enum reboot_mode reboot_mode, const char *cmd)
|
||||
{
|
||||
/*
|
||||
* Perform a hardware reset with the use of the Watchdog timer.
|
||||
*/
|
||||
at91_st_write(AT91_ST_WDMR, AT91_ST_RSTEN | AT91_ST_EXTEN | 1);
|
||||
at91_st_write(AT91_ST_CR, AT91_ST_WDRST);
|
||||
}
|
||||
|
||||
static void __init at91rm9200_dt_timer_init(void)
|
||||
{
|
||||
of_clk_init(NULL);
|
||||
at91rm9200_timer_init();
|
||||
}
|
||||
static const struct at91_soc rm9200_socs[] = {
|
||||
AT91_SOC(AT91RM9200_CIDR_MATCH, 0, "at91rm9200 BGA", "at91rm9200"),
|
||||
{ /* sentinel */ },
|
||||
};
|
||||
|
||||
static void __init at91rm9200_dt_device_init(void)
|
||||
{
|
||||
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
|
||||
struct soc_device *soc;
|
||||
struct device *soc_dev = NULL;
|
||||
|
||||
soc = at91_soc_init(rm9200_socs);
|
||||
if (soc != NULL)
|
||||
soc_dev = soc_device_to_device(soc);
|
||||
|
||||
of_platform_populate(NULL, of_default_bus_match_table, NULL, soc_dev);
|
||||
|
||||
arm_pm_idle = at91rm9200_idle;
|
||||
arm_pm_restart = at91rm9200_restart;
|
||||
at91rm9200_pm_init();
|
||||
}
|
||||
|
||||
|
||||
|
||||
static const char *at91rm9200_dt_board_compat[] __initconst = {
|
||||
"atmel,at91rm9200",
|
||||
NULL
|
||||
};
|
||||
|
||||
DT_MACHINE_START(at91rm9200_dt, "Atmel AT91RM9200")
|
||||
.init_time = at91rm9200_dt_timer_init,
|
||||
.map_io = at91_map_io,
|
||||
.init_machine = at91rm9200_dt_device_init,
|
||||
.dt_compat = at91rm9200_dt_board_compat,
|
||||
MACHINE_END
|
||||
|
||||
@ -7,29 +7,68 @@
|
||||
* Licensed under GPLv2 or later.
|
||||
*/
|
||||
|
||||
#include <linux/types.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_irq.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/clk-provider.h>
|
||||
|
||||
#include <asm/system_misc.h>
|
||||
#include <asm/setup.h>
|
||||
#include <asm/irq.h>
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach/map.h>
|
||||
#include <asm/mach/irq.h>
|
||||
#include <asm/system_misc.h>
|
||||
|
||||
#include "generic.h"
|
||||
#include "soc.h"
|
||||
|
||||
static const struct at91_soc at91sam9_socs[] = {
|
||||
AT91_SOC(AT91SAM9260_CIDR_MATCH, 0, "at91sam9260", NULL),
|
||||
AT91_SOC(AT91SAM9261_CIDR_MATCH, 0, "at91sam9261", NULL),
|
||||
AT91_SOC(AT91SAM9263_CIDR_MATCH, 0, "at91sam9263", NULL),
|
||||
AT91_SOC(AT91SAM9G20_CIDR_MATCH, 0, "at91sam9g20", NULL),
|
||||
AT91_SOC(AT91SAM9RL64_CIDR_MATCH, 0, "at91sam9rl64", NULL),
|
||||
AT91_SOC(AT91SAM9G45_CIDR_MATCH, AT91SAM9M11_EXID_MATCH,
|
||||
"at91sam9m11", "at91sam9g45"),
|
||||
AT91_SOC(AT91SAM9G45_CIDR_MATCH, AT91SAM9M10_EXID_MATCH,
|
||||
"at91sam9m10", "at91sam9g45"),
|
||||
AT91_SOC(AT91SAM9G45_CIDR_MATCH, AT91SAM9G46_EXID_MATCH,
|
||||
"at91sam9g46", "at91sam9g45"),
|
||||
AT91_SOC(AT91SAM9G45_CIDR_MATCH, AT91SAM9G45_EXID_MATCH,
|
||||
"at91sam9g45", "at91sam9g45"),
|
||||
AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91SAM9G15_EXID_MATCH,
|
||||
"at91sam9g15", "at91sam9x5"),
|
||||
AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91SAM9G35_EXID_MATCH,
|
||||
"at91sam9g35", "at91sam9x5"),
|
||||
AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91SAM9X35_EXID_MATCH,
|
||||
"at91sam9x35", "at91sam9x5"),
|
||||
AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91SAM9G25_EXID_MATCH,
|
||||
"at91sam9g25", "at91sam9x5"),
|
||||
AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91SAM9X25_EXID_MATCH,
|
||||
"at91sam9x25", "at91sam9x5"),
|
||||
AT91_SOC(AT91SAM9N12_CIDR_MATCH, AT91SAM9CN12_EXID_MATCH,
|
||||
"at91sam9cn12", "at91sam9n12"),
|
||||
AT91_SOC(AT91SAM9N12_CIDR_MATCH, AT91SAM9N12_EXID_MATCH,
|
||||
"at91sam9n12", "at91sam9n12"),
|
||||
AT91_SOC(AT91SAM9N12_CIDR_MATCH, AT91SAM9CN11_EXID_MATCH,
|
||||
"at91sam9cn11", "at91sam9n12"),
|
||||
AT91_SOC(AT91SAM9XE128_CIDR_MATCH, 0, "at91sam9xe128", "at91sam9xe128"),
|
||||
AT91_SOC(AT91SAM9XE256_CIDR_MATCH, 0, "at91sam9xe256", "at91sam9xe256"),
|
||||
AT91_SOC(AT91SAM9XE512_CIDR_MATCH, 0, "at91sam9xe512", "at91sam9xe512"),
|
||||
{ /* sentinel */ },
|
||||
};
|
||||
|
||||
static void __init at91sam9_common_init(void)
|
||||
{
|
||||
struct soc_device *soc;
|
||||
struct device *soc_dev = NULL;
|
||||
|
||||
soc = at91_soc_init(at91sam9_socs);
|
||||
if (soc != NULL)
|
||||
soc_dev = soc_device_to_device(soc);
|
||||
|
||||
of_platform_populate(NULL, of_default_bus_match_table, NULL, soc_dev);
|
||||
|
||||
arm_pm_idle = at91sam9_idle;
|
||||
}
|
||||
|
||||
static void __init at91sam9_dt_device_init(void)
|
||||
{
|
||||
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
|
||||
|
||||
arm_pm_idle = at91sam9_idle;
|
||||
at91sam9_common_init();
|
||||
at91sam9260_pm_init();
|
||||
}
|
||||
|
||||
@ -40,16 +79,13 @@ static const char *at91_dt_board_compat[] __initconst = {
|
||||
|
||||
DT_MACHINE_START(at91sam_dt, "Atmel AT91SAM9")
|
||||
/* Maintainer: Atmel */
|
||||
.map_io = at91_map_io,
|
||||
.init_machine = at91sam9_dt_device_init,
|
||||
.dt_compat = at91_dt_board_compat,
|
||||
MACHINE_END
|
||||
|
||||
static void __init at91sam9g45_dt_device_init(void)
|
||||
{
|
||||
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
|
||||
|
||||
arm_pm_idle = at91sam9_idle;
|
||||
at91sam9_common_init();
|
||||
at91sam9g45_pm_init();
|
||||
}
|
||||
|
||||
@ -60,16 +96,13 @@ static const char *at91sam9g45_board_compat[] __initconst = {
|
||||
|
||||
DT_MACHINE_START(at91sam9g45_dt, "Atmel AT91SAM9G45")
|
||||
/* Maintainer: Atmel */
|
||||
.map_io = at91_map_io,
|
||||
.init_machine = at91sam9g45_dt_device_init,
|
||||
.dt_compat = at91sam9g45_board_compat,
|
||||
MACHINE_END
|
||||
|
||||
static void __init at91sam9x5_dt_device_init(void)
|
||||
{
|
||||
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
|
||||
|
||||
arm_pm_idle = at91sam9_idle;
|
||||
at91sam9_common_init();
|
||||
at91sam9x5_pm_init();
|
||||
}
|
||||
|
||||
@ -81,7 +114,6 @@ static const char *at91sam9x5_board_compat[] __initconst = {
|
||||
|
||||
DT_MACHINE_START(at91sam9x5_dt, "Atmel AT91SAM9")
|
||||
/* Maintainer: Atmel */
|
||||
.map_io = at91_map_io,
|
||||
.init_machine = at91sam9x5_dt_device_init,
|
||||
.dt_compat = at91sam9x5_board_compat,
|
||||
MACHINE_END
|
||||
|
||||
@ -18,17 +18,10 @@
|
||||
extern void __init at91_map_io(void);
|
||||
extern void __init at91_alt_map_io(void);
|
||||
|
||||
/* Timer */
|
||||
extern void at91rm9200_timer_init(void);
|
||||
|
||||
/* idle */
|
||||
extern void at91rm9200_idle(void);
|
||||
extern void at91sam9_idle(void);
|
||||
|
||||
/* Matrix */
|
||||
extern void at91_ioremap_matrix(u32 base_addr);
|
||||
|
||||
|
||||
#ifdef CONFIG_PM
|
||||
extern void __init at91rm9200_pm_init(void);
|
||||
extern void __init at91sam9260_pm_init(void);
|
||||
|
||||
@ -1,63 +0,0 @@
|
||||
/*
|
||||
* arch/arm/mach-at91/include/mach/at91_dbgu.h
|
||||
*
|
||||
* Copyright (C) 2005 Ivan Kokshaysky
|
||||
* Copyright (C) SAN People
|
||||
*
|
||||
* Debug Unit (DBGU) - System peripherals registers.
|
||||
* Based on AT91RM9200 datasheet revision E.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*/
|
||||
|
||||
#ifndef AT91_DBGU_H
|
||||
#define AT91_DBGU_H
|
||||
|
||||
#define AT91_DBGU_CR (0x00) /* Control Register */
|
||||
#define AT91_DBGU_MR (0x04) /* Mode Register */
|
||||
#define AT91_DBGU_IER (0x08) /* Interrupt Enable Register */
|
||||
#define AT91_DBGU_TXRDY (1 << 1) /* Transmitter Ready */
|
||||
#define AT91_DBGU_TXEMPTY (1 << 9) /* Transmitter Empty */
|
||||
#define AT91_DBGU_IDR (0x0c) /* Interrupt Disable Register */
|
||||
#define AT91_DBGU_IMR (0x10) /* Interrupt Mask Register */
|
||||
#define AT91_DBGU_SR (0x14) /* Status Register */
|
||||
#define AT91_DBGU_RHR (0x18) /* Receiver Holding Register */
|
||||
#define AT91_DBGU_THR (0x1c) /* Transmitter Holding Register */
|
||||
#define AT91_DBGU_BRGR (0x20) /* Baud Rate Generator Register */
|
||||
|
||||
#define AT91_DBGU_CIDR (0x40) /* Chip ID Register */
|
||||
#define AT91_DBGU_EXID (0x44) /* Chip ID Extension Register */
|
||||
#define AT91_DBGU_FNR (0x48) /* Force NTRST Register [SAM9 only] */
|
||||
#define AT91_DBGU_FNTRST (1 << 0) /* Force NTRST */
|
||||
|
||||
/*
|
||||
* Some AT91 parts that don't have full DEBUG units still support the ID
|
||||
* and extensions register.
|
||||
*/
|
||||
#define AT91_CIDR_VERSION (0x1f << 0) /* Version of the Device */
|
||||
#define AT91_CIDR_EPROC (7 << 5) /* Embedded Processor */
|
||||
#define AT91_CIDR_NVPSIZ (0xf << 8) /* Nonvolatile Program Memory Size */
|
||||
#define AT91_CIDR_NVPSIZ2 (0xf << 12) /* Second Nonvolatile Program Memory Size */
|
||||
#define AT91_CIDR_SRAMSIZ (0xf << 16) /* Internal SRAM Size */
|
||||
#define AT91_CIDR_SRAMSIZ_1K (1 << 16)
|
||||
#define AT91_CIDR_SRAMSIZ_2K (2 << 16)
|
||||
#define AT91_CIDR_SRAMSIZ_112K (4 << 16)
|
||||
#define AT91_CIDR_SRAMSIZ_4K (5 << 16)
|
||||
#define AT91_CIDR_SRAMSIZ_80K (6 << 16)
|
||||
#define AT91_CIDR_SRAMSIZ_160K (7 << 16)
|
||||
#define AT91_CIDR_SRAMSIZ_8K (8 << 16)
|
||||
#define AT91_CIDR_SRAMSIZ_16K (9 << 16)
|
||||
#define AT91_CIDR_SRAMSIZ_32K (10 << 16)
|
||||
#define AT91_CIDR_SRAMSIZ_64K (11 << 16)
|
||||
#define AT91_CIDR_SRAMSIZ_128K (12 << 16)
|
||||
#define AT91_CIDR_SRAMSIZ_256K (13 << 16)
|
||||
#define AT91_CIDR_SRAMSIZ_96K (14 << 16)
|
||||
#define AT91_CIDR_SRAMSIZ_512K (15 << 16)
|
||||
#define AT91_CIDR_ARCH (0xff << 20) /* Architecture Identifier */
|
||||
#define AT91_CIDR_NVPTYP (7 << 28) /* Nonvolatile Program Memory Type */
|
||||
#define AT91_CIDR_EXT (1 << 31) /* Extension Flag */
|
||||
|
||||
#endif
|
||||
@ -1,23 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
|
||||
*
|
||||
* Under GPLv2
|
||||
*/
|
||||
|
||||
#ifndef __MACH_AT91_MATRIX_H__
|
||||
#define __MACH_AT91_MATRIX_H__
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
extern void __iomem *at91_matrix_base;
|
||||
|
||||
#define at91_matrix_read(field) \
|
||||
__raw_readl(at91_matrix_base + field)
|
||||
|
||||
#define at91_matrix_write(field, value) \
|
||||
__raw_writel(value, at91_matrix_base + field)
|
||||
|
||||
#else
|
||||
.extern at91_matrix_base
|
||||
#endif
|
||||
|
||||
#endif /* __MACH_AT91_MATRIX_H__ */
|
||||
@ -1,61 +0,0 @@
|
||||
/*
|
||||
* arch/arm/mach-at91/include/mach/at91_st.h
|
||||
*
|
||||
* Copyright (C) 2005 Ivan Kokshaysky
|
||||
* Copyright (C) SAN People
|
||||
*
|
||||
* System Timer (ST) - System peripherals registers.
|
||||
* Based on AT91RM9200 datasheet revision E.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*/
|
||||
|
||||
#ifndef AT91_ST_H
|
||||
#define AT91_ST_H
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
extern void __iomem *at91_st_base;
|
||||
|
||||
#define at91_st_read(field) \
|
||||
__raw_readl(at91_st_base + field)
|
||||
|
||||
#define at91_st_write(field, value) \
|
||||
__raw_writel(value, at91_st_base + field)
|
||||
#else
|
||||
.extern at91_st_base
|
||||
#endif
|
||||
|
||||
#define AT91_ST_CR 0x00 /* Control Register */
|
||||
#define AT91_ST_WDRST (1 << 0) /* Watchdog Timer Restart */
|
||||
|
||||
#define AT91_ST_PIMR 0x04 /* Period Interval Mode Register */
|
||||
#define AT91_ST_PIV (0xffff << 0) /* Period Interval Value */
|
||||
|
||||
#define AT91_ST_WDMR 0x08 /* Watchdog Mode Register */
|
||||
#define AT91_ST_WDV (0xffff << 0) /* Watchdog Counter Value */
|
||||
#define AT91_ST_RSTEN (1 << 16) /* Reset Enable */
|
||||
#define AT91_ST_EXTEN (1 << 17) /* External Signal Assertion Enable */
|
||||
|
||||
#define AT91_ST_RTMR 0x0c /* Real-time Mode Register */
|
||||
#define AT91_ST_RTPRES (0xffff << 0) /* Real-time Prescalar Value */
|
||||
|
||||
#define AT91_ST_SR 0x10 /* Status Register */
|
||||
#define AT91_ST_PITS (1 << 0) /* Period Interval Timer Status */
|
||||
#define AT91_ST_WDOVF (1 << 1) /* Watchdog Overflow */
|
||||
#define AT91_ST_RTTINC (1 << 2) /* Real-time Timer Increment */
|
||||
#define AT91_ST_ALMS (1 << 3) /* Alarm Status */
|
||||
|
||||
#define AT91_ST_IER 0x14 /* Interrupt Enable Register */
|
||||
#define AT91_ST_IDR 0x18 /* Interrupt Disable Register */
|
||||
#define AT91_ST_IMR 0x1c /* Interrupt Mask Register */
|
||||
|
||||
#define AT91_ST_RTAR 0x20 /* Real-time Alarm Register */
|
||||
#define AT91_ST_ALMV (0xfffff << 0) /* Alarm Value */
|
||||
|
||||
#define AT91_ST_CRTR 0x24 /* Current Real-time Register */
|
||||
#define AT91_ST_CRTV (0xfffff << 0) /* Current Real-Time Value */
|
||||
|
||||
#endif
|
||||
@ -1,103 +0,0 @@
|
||||
/*
|
||||
* arch/arm/mach-at91/include/mach/at91rm9200.h
|
||||
*
|
||||
* Copyright (C) 2005 Ivan Kokshaysky
|
||||
* Copyright (C) SAN People
|
||||
*
|
||||
* Common definitions.
|
||||
* Based on AT91RM9200 datasheet revision E.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*/
|
||||
|
||||
#ifndef AT91RM9200_H
|
||||
#define AT91RM9200_H
|
||||
|
||||
/*
|
||||
* Peripheral identifiers/interrupts.
|
||||
*/
|
||||
#define AT91RM9200_ID_PIOA 2 /* Parallel IO Controller A */
|
||||
#define AT91RM9200_ID_PIOB 3 /* Parallel IO Controller B */
|
||||
#define AT91RM9200_ID_PIOC 4 /* Parallel IO Controller C */
|
||||
#define AT91RM9200_ID_PIOD 5 /* Parallel IO Controller D */
|
||||
#define AT91RM9200_ID_US0 6 /* USART 0 */
|
||||
#define AT91RM9200_ID_US1 7 /* USART 1 */
|
||||
#define AT91RM9200_ID_US2 8 /* USART 2 */
|
||||
#define AT91RM9200_ID_US3 9 /* USART 3 */
|
||||
#define AT91RM9200_ID_MCI 10 /* Multimedia Card Interface */
|
||||
#define AT91RM9200_ID_UDP 11 /* USB Device Port */
|
||||
#define AT91RM9200_ID_TWI 12 /* Two-Wire Interface */
|
||||
#define AT91RM9200_ID_SPI 13 /* Serial Peripheral Interface */
|
||||
#define AT91RM9200_ID_SSC0 14 /* Serial Synchronous Controller 0 */
|
||||
#define AT91RM9200_ID_SSC1 15 /* Serial Synchronous Controller 1 */
|
||||
#define AT91RM9200_ID_SSC2 16 /* Serial Synchronous Controller 2 */
|
||||
#define AT91RM9200_ID_TC0 17 /* Timer Counter 0 */
|
||||
#define AT91RM9200_ID_TC1 18 /* Timer Counter 1 */
|
||||
#define AT91RM9200_ID_TC2 19 /* Timer Counter 2 */
|
||||
#define AT91RM9200_ID_TC3 20 /* Timer Counter 3 */
|
||||
#define AT91RM9200_ID_TC4 21 /* Timer Counter 4 */
|
||||
#define AT91RM9200_ID_TC5 22 /* Timer Counter 5 */
|
||||
#define AT91RM9200_ID_UHP 23 /* USB Host port */
|
||||
#define AT91RM9200_ID_EMAC 24 /* Ethernet MAC */
|
||||
#define AT91RM9200_ID_IRQ0 25 /* Advanced Interrupt Controller (IRQ0) */
|
||||
#define AT91RM9200_ID_IRQ1 26 /* Advanced Interrupt Controller (IRQ1) */
|
||||
#define AT91RM9200_ID_IRQ2 27 /* Advanced Interrupt Controller (IRQ2) */
|
||||
#define AT91RM9200_ID_IRQ3 28 /* Advanced Interrupt Controller (IRQ3) */
|
||||
#define AT91RM9200_ID_IRQ4 29 /* Advanced Interrupt Controller (IRQ4) */
|
||||
#define AT91RM9200_ID_IRQ5 30 /* Advanced Interrupt Controller (IRQ5) */
|
||||
#define AT91RM9200_ID_IRQ6 31 /* Advanced Interrupt Controller (IRQ6) */
|
||||
|
||||
|
||||
/*
|
||||
* Peripheral physical base addresses.
|
||||
*/
|
||||
#define AT91RM9200_BASE_TCB0 0xfffa0000
|
||||
#define AT91RM9200_BASE_TC0 0xfffa0000
|
||||
#define AT91RM9200_BASE_TC1 0xfffa0040
|
||||
#define AT91RM9200_BASE_TC2 0xfffa0080
|
||||
#define AT91RM9200_BASE_TCB1 0xfffa4000
|
||||
#define AT91RM9200_BASE_TC3 0xfffa4000
|
||||
#define AT91RM9200_BASE_TC4 0xfffa4040
|
||||
#define AT91RM9200_BASE_TC5 0xfffa4080
|
||||
#define AT91RM9200_BASE_UDP 0xfffb0000
|
||||
#define AT91RM9200_BASE_MCI 0xfffb4000
|
||||
#define AT91RM9200_BASE_TWI 0xfffb8000
|
||||
#define AT91RM9200_BASE_EMAC 0xfffbc000
|
||||
#define AT91RM9200_BASE_US0 0xfffc0000
|
||||
#define AT91RM9200_BASE_US1 0xfffc4000
|
||||
#define AT91RM9200_BASE_US2 0xfffc8000
|
||||
#define AT91RM9200_BASE_US3 0xfffcc000
|
||||
#define AT91RM9200_BASE_SSC0 0xfffd0000
|
||||
#define AT91RM9200_BASE_SSC1 0xfffd4000
|
||||
#define AT91RM9200_BASE_SSC2 0xfffd8000
|
||||
#define AT91RM9200_BASE_SPI 0xfffe0000
|
||||
|
||||
|
||||
/*
|
||||
* System Peripherals
|
||||
*/
|
||||
#define AT91RM9200_BASE_DBGU AT91_BASE_DBGU0 /* Debug Unit */
|
||||
#define AT91RM9200_BASE_PIOA 0xfffff400 /* PIO Controller A */
|
||||
#define AT91RM9200_BASE_PIOB 0xfffff600 /* PIO Controller B */
|
||||
#define AT91RM9200_BASE_PIOC 0xfffff800 /* PIO Controller C */
|
||||
#define AT91RM9200_BASE_PIOD 0xfffffa00 /* PIO Controller D */
|
||||
#define AT91RM9200_BASE_ST 0xfffffd00 /* System Timer */
|
||||
#define AT91RM9200_BASE_RTC 0xfffffe00 /* Real-Time Clock */
|
||||
#define AT91RM9200_BASE_MC 0xffffff00 /* Memory Controllers */
|
||||
|
||||
/*
|
||||
* Internal Memory.
|
||||
*/
|
||||
#define AT91RM9200_ROM_BASE 0x00100000 /* Internal ROM base address */
|
||||
#define AT91RM9200_ROM_SIZE SZ_128K /* Internal ROM size (128Kb) */
|
||||
|
||||
#define AT91RM9200_SRAM_BASE 0x00200000 /* Internal SRAM base address */
|
||||
#define AT91RM9200_SRAM_SIZE SZ_16K /* Internal SRAM size (16Kb) */
|
||||
|
||||
#define AT91RM9200_UHP_BASE 0x00300000 /* USB Host controller */
|
||||
|
||||
|
||||
#endif
|
||||
@ -1,129 +0,0 @@
|
||||
/*
|
||||
* arch/arm/mach-at91/include/mach/at91sam9260.h
|
||||
*
|
||||
* (C) 2006 Andrew Victor
|
||||
*
|
||||
* Common definitions.
|
||||
* Based on AT91SAM9260 datasheet revision A (Preliminary).
|
||||
*
|
||||
* Includes also definitions for AT91SAM9XE and AT91SAM9G families
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*/
|
||||
|
||||
#ifndef AT91SAM9260_H
|
||||
#define AT91SAM9260_H
|
||||
|
||||
/*
|
||||
* Peripheral identifiers/interrupts.
|
||||
*/
|
||||
#define AT91SAM9260_ID_PIOA 2 /* Parallel IO Controller A */
|
||||
#define AT91SAM9260_ID_PIOB 3 /* Parallel IO Controller B */
|
||||
#define AT91SAM9260_ID_PIOC 4 /* Parallel IO Controller C */
|
||||
#define AT91SAM9260_ID_ADC 5 /* Analog-to-Digital Converter */
|
||||
#define AT91SAM9260_ID_US0 6 /* USART 0 */
|
||||
#define AT91SAM9260_ID_US1 7 /* USART 1 */
|
||||
#define AT91SAM9260_ID_US2 8 /* USART 2 */
|
||||
#define AT91SAM9260_ID_MCI 9 /* Multimedia Card Interface */
|
||||
#define AT91SAM9260_ID_UDP 10 /* USB Device Port */
|
||||
#define AT91SAM9260_ID_TWI 11 /* Two-Wire Interface */
|
||||
#define AT91SAM9260_ID_SPI0 12 /* Serial Peripheral Interface 0 */
|
||||
#define AT91SAM9260_ID_SPI1 13 /* Serial Peripheral Interface 1 */
|
||||
#define AT91SAM9260_ID_SSC 14 /* Serial Synchronous Controller */
|
||||
#define AT91SAM9260_ID_TC0 17 /* Timer Counter 0 */
|
||||
#define AT91SAM9260_ID_TC1 18 /* Timer Counter 1 */
|
||||
#define AT91SAM9260_ID_TC2 19 /* Timer Counter 2 */
|
||||
#define AT91SAM9260_ID_UHP 20 /* USB Host port */
|
||||
#define AT91SAM9260_ID_EMAC 21 /* Ethernet */
|
||||
#define AT91SAM9260_ID_ISI 22 /* Image Sensor Interface */
|
||||
#define AT91SAM9260_ID_US3 23 /* USART 3 */
|
||||
#define AT91SAM9260_ID_US4 24 /* USART 4 */
|
||||
#define AT91SAM9260_ID_US5 25 /* USART 5 */
|
||||
#define AT91SAM9260_ID_TC3 26 /* Timer Counter 3 */
|
||||
#define AT91SAM9260_ID_TC4 27 /* Timer Counter 4 */
|
||||
#define AT91SAM9260_ID_TC5 28 /* Timer Counter 5 */
|
||||
#define AT91SAM9260_ID_IRQ0 29 /* Advanced Interrupt Controller (IRQ0) */
|
||||
#define AT91SAM9260_ID_IRQ1 30 /* Advanced Interrupt Controller (IRQ1) */
|
||||
#define AT91SAM9260_ID_IRQ2 31 /* Advanced Interrupt Controller (IRQ2) */
|
||||
|
||||
|
||||
/*
|
||||
* User Peripheral physical base addresses.
|
||||
*/
|
||||
#define AT91SAM9260_BASE_TCB0 0xfffa0000
|
||||
#define AT91SAM9260_BASE_TC0 0xfffa0000
|
||||
#define AT91SAM9260_BASE_TC1 0xfffa0040
|
||||
#define AT91SAM9260_BASE_TC2 0xfffa0080
|
||||
#define AT91SAM9260_BASE_UDP 0xfffa4000
|
||||
#define AT91SAM9260_BASE_MCI 0xfffa8000
|
||||
#define AT91SAM9260_BASE_TWI 0xfffac000
|
||||
#define AT91SAM9260_BASE_US0 0xfffb0000
|
||||
#define AT91SAM9260_BASE_US1 0xfffb4000
|
||||
#define AT91SAM9260_BASE_US2 0xfffb8000
|
||||
#define AT91SAM9260_BASE_SSC 0xfffbc000
|
||||
#define AT91SAM9260_BASE_ISI 0xfffc0000
|
||||
#define AT91SAM9260_BASE_EMAC 0xfffc4000
|
||||
#define AT91SAM9260_BASE_SPI0 0xfffc8000
|
||||
#define AT91SAM9260_BASE_SPI1 0xfffcc000
|
||||
#define AT91SAM9260_BASE_US3 0xfffd0000
|
||||
#define AT91SAM9260_BASE_US4 0xfffd4000
|
||||
#define AT91SAM9260_BASE_US5 0xfffd8000
|
||||
#define AT91SAM9260_BASE_TCB1 0xfffdc000
|
||||
#define AT91SAM9260_BASE_TC3 0xfffdc000
|
||||
#define AT91SAM9260_BASE_TC4 0xfffdc040
|
||||
#define AT91SAM9260_BASE_TC5 0xfffdc080
|
||||
#define AT91SAM9260_BASE_ADC 0xfffe0000
|
||||
|
||||
/*
|
||||
* System Peripherals
|
||||
*/
|
||||
#define AT91SAM9260_BASE_ECC 0xffffe800
|
||||
#define AT91SAM9260_BASE_SDRAMC 0xffffea00
|
||||
#define AT91SAM9260_BASE_SMC 0xffffec00
|
||||
#define AT91SAM9260_BASE_MATRIX 0xffffee00
|
||||
#define AT91SAM9260_BASE_DBGU AT91_BASE_DBGU0
|
||||
#define AT91SAM9260_BASE_PIOA 0xfffff400
|
||||
#define AT91SAM9260_BASE_PIOB 0xfffff600
|
||||
#define AT91SAM9260_BASE_PIOC 0xfffff800
|
||||
#define AT91SAM9260_BASE_RSTC 0xfffffd00
|
||||
#define AT91SAM9260_BASE_SHDWC 0xfffffd10
|
||||
#define AT91SAM9260_BASE_RTT 0xfffffd20
|
||||
#define AT91SAM9260_BASE_PIT 0xfffffd30
|
||||
#define AT91SAM9260_BASE_WDT 0xfffffd40
|
||||
#define AT91SAM9260_BASE_GPBR 0xfffffd50
|
||||
|
||||
|
||||
/*
|
||||
* Internal Memory.
|
||||
*/
|
||||
#define AT91SAM9260_ROM_BASE 0x00100000 /* Internal ROM base address */
|
||||
#define AT91SAM9260_ROM_SIZE SZ_32K /* Internal ROM size (32Kb) */
|
||||
|
||||
#define AT91SAM9260_SRAM0_BASE 0x00200000 /* Internal SRAM 0 base address */
|
||||
#define AT91SAM9260_SRAM0_SIZE SZ_4K /* Internal SRAM 0 size (4Kb) */
|
||||
#define AT91SAM9260_SRAM1_BASE 0x00300000 /* Internal SRAM 1 base address */
|
||||
#define AT91SAM9260_SRAM1_SIZE SZ_4K /* Internal SRAM 1 size (4Kb) */
|
||||
#define AT91SAM9260_SRAM_BASE 0x002FF000 /* Internal SRAM base address */
|
||||
#define AT91SAM9260_SRAM_SIZE SZ_8K /* Internal SRAM size (8Kb) */
|
||||
|
||||
#define AT91SAM9260_UHP_BASE 0x00500000 /* USB Host controller */
|
||||
|
||||
#define AT91SAM9XE_FLASH_BASE 0x00200000 /* Internal FLASH base address */
|
||||
#define AT91SAM9XE_SRAM_BASE 0x00300000 /* Internal SRAM base address */
|
||||
|
||||
#define AT91SAM9G20_ROM_BASE 0x00100000 /* Internal ROM base address */
|
||||
#define AT91SAM9G20_ROM_SIZE SZ_32K /* Internal ROM size (32Kb) */
|
||||
|
||||
#define AT91SAM9G20_SRAM0_BASE 0x00200000 /* Internal SRAM 0 base address */
|
||||
#define AT91SAM9G20_SRAM0_SIZE SZ_16K /* Internal SRAM 0 size (16Kb) */
|
||||
#define AT91SAM9G20_SRAM1_BASE 0x00300000 /* Internal SRAM 1 base address */
|
||||
#define AT91SAM9G20_SRAM1_SIZE SZ_16K /* Internal SRAM 1 size (16Kb) */
|
||||
#define AT91SAM9G20_SRAM_BASE 0x002FC000 /* Internal SRAM base address */
|
||||
#define AT91SAM9G20_SRAM_SIZE SZ_32K /* Internal SRAM size (32Kb) */
|
||||
|
||||
#define AT91SAM9G20_UHP_BASE 0x00500000 /* USB Host controller */
|
||||
|
||||
#endif
|
||||
@ -1,80 +0,0 @@
|
||||
/*
|
||||
* arch/arm/mach-at91/include/mach/at91sam9260_matrix.h
|
||||
*
|
||||
* Copyright (C) 2007 Atmel Corporation.
|
||||
*
|
||||
* Memory Controllers (MATRIX, EBI) - System peripherals registers.
|
||||
* Based on AT91SAM9260 datasheet revision B.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*/
|
||||
|
||||
#ifndef AT91SAM9260_MATRIX_H
|
||||
#define AT91SAM9260_MATRIX_H
|
||||
|
||||
#define AT91_MATRIX_MCFG0 0x00 /* Master Configuration Register 0 */
|
||||
#define AT91_MATRIX_MCFG1 0x04 /* Master Configuration Register 1 */
|
||||
#define AT91_MATRIX_MCFG2 0x08 /* Master Configuration Register 2 */
|
||||
#define AT91_MATRIX_MCFG3 0x0C /* Master Configuration Register 3 */
|
||||
#define AT91_MATRIX_MCFG4 0x10 /* Master Configuration Register 4 */
|
||||
#define AT91_MATRIX_MCFG5 0x14 /* Master Configuration Register 5 */
|
||||
#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */
|
||||
#define AT91_MATRIX_ULBT_INFINITE (0 << 0)
|
||||
#define AT91_MATRIX_ULBT_SINGLE (1 << 0)
|
||||
#define AT91_MATRIX_ULBT_FOUR (2 << 0)
|
||||
#define AT91_MATRIX_ULBT_EIGHT (3 << 0)
|
||||
#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0)
|
||||
|
||||
#define AT91_MATRIX_SCFG0 0x40 /* Slave Configuration Register 0 */
|
||||
#define AT91_MATRIX_SCFG1 0x44 /* Slave Configuration Register 1 */
|
||||
#define AT91_MATRIX_SCFG2 0x48 /* Slave Configuration Register 2 */
|
||||
#define AT91_MATRIX_SCFG3 0x4C /* Slave Configuration Register 3 */
|
||||
#define AT91_MATRIX_SCFG4 0x50 /* Slave Configuration Register 4 */
|
||||
#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */
|
||||
#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */
|
||||
#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
|
||||
#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
|
||||
#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
|
||||
#define AT91_MATRIX_FIXED_DEFMSTR (7 << 18) /* Fixed Index of Default Master */
|
||||
#define AT91_MATRIX_ARBT (3 << 24) /* Arbitration Type */
|
||||
#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24)
|
||||
#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
|
||||
|
||||
#define AT91_MATRIX_PRAS0 0x80 /* Priority Register A for Slave 0 */
|
||||
#define AT91_MATRIX_PRAS1 0x88 /* Priority Register A for Slave 1 */
|
||||
#define AT91_MATRIX_PRAS2 0x90 /* Priority Register A for Slave 2 */
|
||||
#define AT91_MATRIX_PRAS3 0x98 /* Priority Register A for Slave 3 */
|
||||
#define AT91_MATRIX_PRAS4 0xA0 /* Priority Register A for Slave 4 */
|
||||
#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */
|
||||
#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */
|
||||
#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */
|
||||
#define AT91_MATRIX_M3PR (3 << 12) /* Master 3 Priority */
|
||||
#define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */
|
||||
#define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */
|
||||
|
||||
#define AT91_MATRIX_MRCR 0x100 /* Master Remap Control Register */
|
||||
#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
|
||||
#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
|
||||
|
||||
#define AT91_MATRIX_EBICSA 0x11C /* EBI Chip Select Assignment Register */
|
||||
#define AT91_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */
|
||||
#define AT91_MATRIX_CS1A_SMC (0 << 1)
|
||||
#define AT91_MATRIX_CS1A_SDRAMC (1 << 1)
|
||||
#define AT91_MATRIX_CS3A (1 << 3) /* Chip Select 3 Assignment */
|
||||
#define AT91_MATRIX_CS3A_SMC (0 << 3)
|
||||
#define AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3)
|
||||
#define AT91_MATRIX_CS4A (1 << 4) /* Chip Select 4 Assignment */
|
||||
#define AT91_MATRIX_CS4A_SMC (0 << 4)
|
||||
#define AT91_MATRIX_CS4A_SMC_CF1 (1 << 4)
|
||||
#define AT91_MATRIX_CS5A (1 << 5) /* Chip Select 5 Assignment */
|
||||
#define AT91_MATRIX_CS5A_SMC (0 << 5)
|
||||
#define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5)
|
||||
#define AT91_MATRIX_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
|
||||
#define AT91_MATRIX_VDDIOMSEL (1 << 16) /* Memory voltage selection */
|
||||
#define AT91_MATRIX_VDDIOMSEL_1_8V (0 << 16)
|
||||
#define AT91_MATRIX_VDDIOMSEL_3_3V (1 << 16)
|
||||
|
||||
#endif
|
||||
@ -1,99 +0,0 @@
|
||||
/*
|
||||
* arch/arm/mach-at91/include/mach/at91sam9261.h
|
||||
*
|
||||
* Copyright (C) SAN People
|
||||
*
|
||||
* Common definitions.
|
||||
* Based on AT91SAM9261 datasheet revision E. (Preliminary)
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*/
|
||||
|
||||
#ifndef AT91SAM9261_H
|
||||
#define AT91SAM9261_H
|
||||
|
||||
/*
|
||||
* Peripheral identifiers/interrupts.
|
||||
*/
|
||||
#define AT91SAM9261_ID_PIOA 2 /* Parallel IO Controller A */
|
||||
#define AT91SAM9261_ID_PIOB 3 /* Parallel IO Controller B */
|
||||
#define AT91SAM9261_ID_PIOC 4 /* Parallel IO Controller C */
|
||||
#define AT91SAM9261_ID_US0 6 /* USART 0 */
|
||||
#define AT91SAM9261_ID_US1 7 /* USART 1 */
|
||||
#define AT91SAM9261_ID_US2 8 /* USART 2 */
|
||||
#define AT91SAM9261_ID_MCI 9 /* Multimedia Card Interface */
|
||||
#define AT91SAM9261_ID_UDP 10 /* USB Device Port */
|
||||
#define AT91SAM9261_ID_TWI 11 /* Two-Wire Interface */
|
||||
#define AT91SAM9261_ID_SPI0 12 /* Serial Peripheral Interface 0 */
|
||||
#define AT91SAM9261_ID_SPI1 13 /* Serial Peripheral Interface 1 */
|
||||
#define AT91SAM9261_ID_SSC0 14 /* Serial Synchronous Controller 0 */
|
||||
#define AT91SAM9261_ID_SSC1 15 /* Serial Synchronous Controller 1 */
|
||||
#define AT91SAM9261_ID_SSC2 16 /* Serial Synchronous Controller 2 */
|
||||
#define AT91SAM9261_ID_TC0 17 /* Timer Counter 0 */
|
||||
#define AT91SAM9261_ID_TC1 18 /* Timer Counter 1 */
|
||||
#define AT91SAM9261_ID_TC2 19 /* Timer Counter 2 */
|
||||
#define AT91SAM9261_ID_UHP 20 /* USB Host port */
|
||||
#define AT91SAM9261_ID_LCDC 21 /* LDC Controller */
|
||||
#define AT91SAM9261_ID_IRQ0 29 /* Advanced Interrupt Controller (IRQ0) */
|
||||
#define AT91SAM9261_ID_IRQ1 30 /* Advanced Interrupt Controller (IRQ1) */
|
||||
#define AT91SAM9261_ID_IRQ2 31 /* Advanced Interrupt Controller (IRQ2) */
|
||||
|
||||
|
||||
/*
|
||||
* User Peripheral physical base addresses.
|
||||
*/
|
||||
#define AT91SAM9261_BASE_TCB0 0xfffa0000
|
||||
#define AT91SAM9261_BASE_TC0 0xfffa0000
|
||||
#define AT91SAM9261_BASE_TC1 0xfffa0040
|
||||
#define AT91SAM9261_BASE_TC2 0xfffa0080
|
||||
#define AT91SAM9261_BASE_UDP 0xfffa4000
|
||||
#define AT91SAM9261_BASE_MCI 0xfffa8000
|
||||
#define AT91SAM9261_BASE_TWI 0xfffac000
|
||||
#define AT91SAM9261_BASE_US0 0xfffb0000
|
||||
#define AT91SAM9261_BASE_US1 0xfffb4000
|
||||
#define AT91SAM9261_BASE_US2 0xfffb8000
|
||||
#define AT91SAM9261_BASE_SSC0 0xfffbc000
|
||||
#define AT91SAM9261_BASE_SSC1 0xfffc0000
|
||||
#define AT91SAM9261_BASE_SSC2 0xfffc4000
|
||||
#define AT91SAM9261_BASE_SPI0 0xfffc8000
|
||||
#define AT91SAM9261_BASE_SPI1 0xfffcc000
|
||||
|
||||
|
||||
/*
|
||||
* System Peripherals
|
||||
*/
|
||||
#define AT91SAM9261_BASE_SMC 0xffffec00
|
||||
#define AT91SAM9261_BASE_MATRIX 0xffffee00
|
||||
#define AT91SAM9261_BASE_SDRAMC 0xffffea00
|
||||
#define AT91SAM9261_BASE_DBGU AT91_BASE_DBGU0
|
||||
#define AT91SAM9261_BASE_PIOA 0xfffff400
|
||||
#define AT91SAM9261_BASE_PIOB 0xfffff600
|
||||
#define AT91SAM9261_BASE_PIOC 0xfffff800
|
||||
#define AT91SAM9261_BASE_RSTC 0xfffffd00
|
||||
#define AT91SAM9261_BASE_SHDWC 0xfffffd10
|
||||
#define AT91SAM9261_BASE_RTT 0xfffffd20
|
||||
#define AT91SAM9261_BASE_PIT 0xfffffd30
|
||||
#define AT91SAM9261_BASE_WDT 0xfffffd40
|
||||
#define AT91SAM9261_BASE_GPBR 0xfffffd50
|
||||
|
||||
|
||||
/*
|
||||
* Internal Memory.
|
||||
*/
|
||||
#define AT91SAM9261_SRAM_BASE 0x00300000 /* Internal SRAM base address */
|
||||
#define AT91SAM9261_SRAM_SIZE 0x00028000 /* Internal SRAM size (160Kb) */
|
||||
|
||||
#define AT91SAM9G10_SRAM_BASE AT91SAM9261_SRAM_BASE /* Internal SRAM base address */
|
||||
#define AT91SAM9G10_SRAM_SIZE 0x00004000 /* Internal SRAM size (16Kb) */
|
||||
|
||||
#define AT91SAM9261_ROM_BASE 0x00400000 /* Internal ROM base address */
|
||||
#define AT91SAM9261_ROM_SIZE SZ_32K /* Internal ROM size (32Kb) */
|
||||
|
||||
#define AT91SAM9261_UHP_BASE 0x00500000 /* USB Host controller */
|
||||
#define AT91SAM9261_LCDC_BASE 0x00600000 /* LDC controller */
|
||||
|
||||
|
||||
#endif
|
||||
@ -1,64 +0,0 @@
|
||||
/*
|
||||
* arch/arm/mach-at91/include/mach/at91sam9261_matrix.h
|
||||
*
|
||||
* Copyright (C) 2007 Atmel Corporation.
|
||||
*
|
||||
* Memory Controllers (MATRIX, EBI) - System peripherals registers.
|
||||
* Based on AT91SAM9261 datasheet revision D.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*/
|
||||
|
||||
#ifndef AT91SAM9261_MATRIX_H
|
||||
#define AT91SAM9261_MATRIX_H
|
||||
|
||||
#define AT91_MATRIX_MCFG 0x00 /* Master Configuration Register */
|
||||
#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
|
||||
#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
|
||||
|
||||
#define AT91_MATRIX_SCFG0 0x04 /* Slave Configuration Register 0 */
|
||||
#define AT91_MATRIX_SCFG1 0x08 /* Slave Configuration Register 1 */
|
||||
#define AT91_MATRIX_SCFG2 0x0C /* Slave Configuration Register 2 */
|
||||
#define AT91_MATRIX_SCFG3 0x10 /* Slave Configuration Register 3 */
|
||||
#define AT91_MATRIX_SCFG4 0x14 /* Slave Configuration Register 4 */
|
||||
#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */
|
||||
#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */
|
||||
#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
|
||||
#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
|
||||
#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
|
||||
#define AT91_MATRIX_FIXED_DEFMSTR (7 << 18) /* Fixed Index of Default Master */
|
||||
|
||||
#define AT91_MATRIX_TCR 0x24 /* TCM Configuration Register */
|
||||
#define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */
|
||||
#define AT91_MATRIX_ITCM_0 (0 << 0)
|
||||
#define AT91_MATRIX_ITCM_16 (5 << 0)
|
||||
#define AT91_MATRIX_ITCM_32 (6 << 0)
|
||||
#define AT91_MATRIX_ITCM_64 (7 << 0)
|
||||
#define AT91_MATRIX_DTCM_SIZE (0xf << 4) /* Size of DTCM enabled memory block */
|
||||
#define AT91_MATRIX_DTCM_0 (0 << 4)
|
||||
#define AT91_MATRIX_DTCM_16 (5 << 4)
|
||||
#define AT91_MATRIX_DTCM_32 (6 << 4)
|
||||
#define AT91_MATRIX_DTCM_64 (7 << 4)
|
||||
|
||||
#define AT91_MATRIX_EBICSA 0x30 /* EBI Chip Select Assignment Register */
|
||||
#define AT91_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */
|
||||
#define AT91_MATRIX_CS1A_SMC (0 << 1)
|
||||
#define AT91_MATRIX_CS1A_SDRAMC (1 << 1)
|
||||
#define AT91_MATRIX_CS3A (1 << 3) /* Chip Select 3 Assignment */
|
||||
#define AT91_MATRIX_CS3A_SMC (0 << 3)
|
||||
#define AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3)
|
||||
#define AT91_MATRIX_CS4A (1 << 4) /* Chip Select 4 Assignment */
|
||||
#define AT91_MATRIX_CS4A_SMC (0 << 4)
|
||||
#define AT91_MATRIX_CS4A_SMC_CF1 (1 << 4)
|
||||
#define AT91_MATRIX_CS5A (1 << 5) /* Chip Select 5 Assignment */
|
||||
#define AT91_MATRIX_CS5A_SMC (0 << 5)
|
||||
#define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5)
|
||||
#define AT91_MATRIX_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
|
||||
|
||||
#define AT91_MATRIX_USBPUCR 0x34 /* USB Pad Pull-Up Control Register */
|
||||
#define AT91_MATRIX_USBPUCR_PUON (1 << 30) /* USB Device PAD Pull-up Enable */
|
||||
|
||||
#endif
|
||||
@ -1,117 +0,0 @@
|
||||
/*
|
||||
* arch/arm/mach-at91/include/mach/at91sam9263.h
|
||||
*
|
||||
* (C) 2007 Atmel Corporation.
|
||||
*
|
||||
* Common definitions.
|
||||
* Based on AT91SAM9263 datasheet revision B (Preliminary).
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*/
|
||||
|
||||
#ifndef AT91SAM9263_H
|
||||
#define AT91SAM9263_H
|
||||
|
||||
/*
|
||||
* Peripheral identifiers/interrupts.
|
||||
*/
|
||||
#define AT91SAM9263_ID_PIOA 2 /* Parallel IO Controller A */
|
||||
#define AT91SAM9263_ID_PIOB 3 /* Parallel IO Controller B */
|
||||
#define AT91SAM9263_ID_PIOCDE 4 /* Parallel IO Controller C, D and E */
|
||||
#define AT91SAM9263_ID_US0 7 /* USART 0 */
|
||||
#define AT91SAM9263_ID_US1 8 /* USART 1 */
|
||||
#define AT91SAM9263_ID_US2 9 /* USART 2 */
|
||||
#define AT91SAM9263_ID_MCI0 10 /* Multimedia Card Interface 0 */
|
||||
#define AT91SAM9263_ID_MCI1 11 /* Multimedia Card Interface 1 */
|
||||
#define AT91SAM9263_ID_CAN 12 /* CAN */
|
||||
#define AT91SAM9263_ID_TWI 13 /* Two-Wire Interface */
|
||||
#define AT91SAM9263_ID_SPI0 14 /* Serial Peripheral Interface 0 */
|
||||
#define AT91SAM9263_ID_SPI1 15 /* Serial Peripheral Interface 1 */
|
||||
#define AT91SAM9263_ID_SSC0 16 /* Serial Synchronous Controller 0 */
|
||||
#define AT91SAM9263_ID_SSC1 17 /* Serial Synchronous Controller 1 */
|
||||
#define AT91SAM9263_ID_AC97C 18 /* AC97 Controller */
|
||||
#define AT91SAM9263_ID_TCB 19 /* Timer Counter 0, 1 and 2 */
|
||||
#define AT91SAM9263_ID_PWMC 20 /* Pulse Width Modulation Controller */
|
||||
#define AT91SAM9263_ID_EMAC 21 /* Ethernet */
|
||||
#define AT91SAM9263_ID_2DGE 23 /* 2D Graphic Engine */
|
||||
#define AT91SAM9263_ID_UDP 24 /* USB Device Port */
|
||||
#define AT91SAM9263_ID_ISI 25 /* Image Sensor Interface */
|
||||
#define AT91SAM9263_ID_LCDC 26 /* LCD Controller */
|
||||
#define AT91SAM9263_ID_DMA 27 /* DMA Controller */
|
||||
#define AT91SAM9263_ID_UHP 29 /* USB Host port */
|
||||
#define AT91SAM9263_ID_IRQ0 30 /* Advanced Interrupt Controller (IRQ0) */
|
||||
#define AT91SAM9263_ID_IRQ1 31 /* Advanced Interrupt Controller (IRQ1) */
|
||||
|
||||
|
||||
/*
|
||||
* User Peripheral physical base addresses.
|
||||
*/
|
||||
#define AT91SAM9263_BASE_UDP 0xfff78000
|
||||
#define AT91SAM9263_BASE_TCB0 0xfff7c000
|
||||
#define AT91SAM9263_BASE_TC0 0xfff7c000
|
||||
#define AT91SAM9263_BASE_TC1 0xfff7c040
|
||||
#define AT91SAM9263_BASE_TC2 0xfff7c080
|
||||
#define AT91SAM9263_BASE_MCI0 0xfff80000
|
||||
#define AT91SAM9263_BASE_MCI1 0xfff84000
|
||||
#define AT91SAM9263_BASE_TWI 0xfff88000
|
||||
#define AT91SAM9263_BASE_US0 0xfff8c000
|
||||
#define AT91SAM9263_BASE_US1 0xfff90000
|
||||
#define AT91SAM9263_BASE_US2 0xfff94000
|
||||
#define AT91SAM9263_BASE_SSC0 0xfff98000
|
||||
#define AT91SAM9263_BASE_SSC1 0xfff9c000
|
||||
#define AT91SAM9263_BASE_AC97C 0xfffa0000
|
||||
#define AT91SAM9263_BASE_SPI0 0xfffa4000
|
||||
#define AT91SAM9263_BASE_SPI1 0xfffa8000
|
||||
#define AT91SAM9263_BASE_CAN 0xfffac000
|
||||
#define AT91SAM9263_BASE_PWMC 0xfffb8000
|
||||
#define AT91SAM9263_BASE_EMAC 0xfffbc000
|
||||
#define AT91SAM9263_BASE_ISI 0xfffc4000
|
||||
#define AT91SAM9263_BASE_2DGE 0xfffc8000
|
||||
|
||||
/*
|
||||
* System Peripherals
|
||||
*/
|
||||
#define AT91SAM9263_BASE_ECC0 0xffffe000
|
||||
#define AT91SAM9263_BASE_SDRAMC0 0xffffe200
|
||||
#define AT91SAM9263_BASE_SMC0 0xffffe400
|
||||
#define AT91SAM9263_BASE_ECC1 0xffffe600
|
||||
#define AT91SAM9263_BASE_SDRAMC1 0xffffe800
|
||||
#define AT91SAM9263_BASE_SMC1 0xffffea00
|
||||
#define AT91SAM9263_BASE_MATRIX 0xffffec00
|
||||
#define AT91SAM9263_BASE_DBGU AT91_BASE_DBGU1
|
||||
#define AT91SAM9263_BASE_PIOA 0xfffff200
|
||||
#define AT91SAM9263_BASE_PIOB 0xfffff400
|
||||
#define AT91SAM9263_BASE_PIOC 0xfffff600
|
||||
#define AT91SAM9263_BASE_PIOD 0xfffff800
|
||||
#define AT91SAM9263_BASE_PIOE 0xfffffa00
|
||||
#define AT91SAM9263_BASE_RSTC 0xfffffd00
|
||||
#define AT91SAM9263_BASE_SHDWC 0xfffffd10
|
||||
#define AT91SAM9263_BASE_RTT0 0xfffffd20
|
||||
#define AT91SAM9263_BASE_PIT 0xfffffd30
|
||||
#define AT91SAM9263_BASE_WDT 0xfffffd40
|
||||
#define AT91SAM9263_BASE_RTT1 0xfffffd50
|
||||
#define AT91SAM9263_BASE_GPBR 0xfffffd60
|
||||
|
||||
#define AT91_SMC AT91_SMC0
|
||||
|
||||
/*
|
||||
* Internal Memory.
|
||||
*/
|
||||
#define AT91SAM9263_SRAM0_BASE 0x00300000 /* Internal SRAM 0 base address */
|
||||
#define AT91SAM9263_SRAM0_SIZE (80 * SZ_1K) /* Internal SRAM 0 size (80Kb) */
|
||||
|
||||
#define AT91SAM9263_ROM_BASE 0x00400000 /* Internal ROM base address */
|
||||
#define AT91SAM9263_ROM_SIZE SZ_128K /* Internal ROM size (128Kb) */
|
||||
|
||||
#define AT91SAM9263_SRAM1_BASE 0x00500000 /* Internal SRAM 1 base address */
|
||||
#define AT91SAM9263_SRAM1_SIZE SZ_16K /* Internal SRAM 1 size (16Kb) */
|
||||
|
||||
#define AT91SAM9263_LCDC_BASE 0x00700000 /* LCD Controller */
|
||||
#define AT91SAM9263_DMAC_BASE 0x00800000 /* DMA Controller */
|
||||
#define AT91SAM9263_UHP_BASE 0x00a00000 /* USB Host controller */
|
||||
|
||||
|
||||
#endif
|
||||
@ -1,129 +0,0 @@
|
||||
/*
|
||||
* arch/arm/mach-at91/include/mach/at91sam9263_matrix.h
|
||||
*
|
||||
* Copyright (C) 2006 Atmel Corporation.
|
||||
*
|
||||
* Memory Controllers (MATRIX, EBI) - System peripherals registers.
|
||||
* Based on AT91SAM9263 datasheet revision B (Preliminary).
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*/
|
||||
|
||||
#ifndef AT91SAM9263_MATRIX_H
|
||||
#define AT91SAM9263_MATRIX_H
|
||||
|
||||
#define AT91_MATRIX_MCFG0 0x00 /* Master Configuration Register 0 */
|
||||
#define AT91_MATRIX_MCFG1 0x04 /* Master Configuration Register 1 */
|
||||
#define AT91_MATRIX_MCFG2 0x08 /* Master Configuration Register 2 */
|
||||
#define AT91_MATRIX_MCFG3 0x0C /* Master Configuration Register 3 */
|
||||
#define AT91_MATRIX_MCFG4 0x10 /* Master Configuration Register 4 */
|
||||
#define AT91_MATRIX_MCFG5 0x14 /* Master Configuration Register 5 */
|
||||
#define AT91_MATRIX_MCFG6 0x18 /* Master Configuration Register 6 */
|
||||
#define AT91_MATRIX_MCFG7 0x1C /* Master Configuration Register 7 */
|
||||
#define AT91_MATRIX_MCFG8 0x20 /* Master Configuration Register 8 */
|
||||
#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */
|
||||
#define AT91_MATRIX_ULBT_INFINITE (0 << 0)
|
||||
#define AT91_MATRIX_ULBT_SINGLE (1 << 0)
|
||||
#define AT91_MATRIX_ULBT_FOUR (2 << 0)
|
||||
#define AT91_MATRIX_ULBT_EIGHT (3 << 0)
|
||||
#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0)
|
||||
|
||||
#define AT91_MATRIX_SCFG0 0x40 /* Slave Configuration Register 0 */
|
||||
#define AT91_MATRIX_SCFG1 0x44 /* Slave Configuration Register 1 */
|
||||
#define AT91_MATRIX_SCFG2 0x48 /* Slave Configuration Register 2 */
|
||||
#define AT91_MATRIX_SCFG3 0x4C /* Slave Configuration Register 3 */
|
||||
#define AT91_MATRIX_SCFG4 0x50 /* Slave Configuration Register 4 */
|
||||
#define AT91_MATRIX_SCFG5 0x54 /* Slave Configuration Register 5 */
|
||||
#define AT91_MATRIX_SCFG6 0x58 /* Slave Configuration Register 6 */
|
||||
#define AT91_MATRIX_SCFG7 0x5C /* Slave Configuration Register 7 */
|
||||
#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */
|
||||
#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */
|
||||
#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
|
||||
#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
|
||||
#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
|
||||
#define AT91_MATRIX_FIXED_DEFMSTR (0xf << 18) /* Fixed Index of Default Master */
|
||||
#define AT91_MATRIX_ARBT (3 << 24) /* Arbitration Type */
|
||||
#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24)
|
||||
#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
|
||||
|
||||
#define AT91_MATRIX_PRAS0 0x80 /* Priority Register A for Slave 0 */
|
||||
#define AT91_MATRIX_PRBS0 0x84 /* Priority Register B for Slave 0 */
|
||||
#define AT91_MATRIX_PRAS1 0x88 /* Priority Register A for Slave 1 */
|
||||
#define AT91_MATRIX_PRBS1 0x8C /* Priority Register B for Slave 1 */
|
||||
#define AT91_MATRIX_PRAS2 0x90 /* Priority Register A for Slave 2 */
|
||||
#define AT91_MATRIX_PRBS2 0x94 /* Priority Register B for Slave 2 */
|
||||
#define AT91_MATRIX_PRAS3 0x98 /* Priority Register A for Slave 3 */
|
||||
#define AT91_MATRIX_PRBS3 0x9C /* Priority Register B for Slave 3 */
|
||||
#define AT91_MATRIX_PRAS4 0xA0 /* Priority Register A for Slave 4 */
|
||||
#define AT91_MATRIX_PRBS4 0xA4 /* Priority Register B for Slave 4 */
|
||||
#define AT91_MATRIX_PRAS5 0xA8 /* Priority Register A for Slave 5 */
|
||||
#define AT91_MATRIX_PRBS5 0xAC /* Priority Register B for Slave 5 */
|
||||
#define AT91_MATRIX_PRAS6 0xB0 /* Priority Register A for Slave 6 */
|
||||
#define AT91_MATRIX_PRBS6 0xB4 /* Priority Register B for Slave 6 */
|
||||
#define AT91_MATRIX_PRAS7 0xB8 /* Priority Register A for Slave 7 */
|
||||
#define AT91_MATRIX_PRBS7 0xBC /* Priority Register B for Slave 7 */
|
||||
#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */
|
||||
#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */
|
||||
#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */
|
||||
#define AT91_MATRIX_M3PR (3 << 12) /* Master 3 Priority */
|
||||
#define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */
|
||||
#define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */
|
||||
#define AT91_MATRIX_M6PR (3 << 24) /* Master 6 Priority */
|
||||
#define AT91_MATRIX_M7PR (3 << 28) /* Master 7 Priority */
|
||||
#define AT91_MATRIX_M8PR (3 << 0) /* Master 8 Priority (in Register B) */
|
||||
|
||||
#define AT91_MATRIX_MRCR 0x100 /* Master Remap Control Register */
|
||||
#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
|
||||
#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
|
||||
#define AT91_MATRIX_RCB2 (1 << 2)
|
||||
#define AT91_MATRIX_RCB3 (1 << 3)
|
||||
#define AT91_MATRIX_RCB4 (1 << 4)
|
||||
#define AT91_MATRIX_RCB5 (1 << 5)
|
||||
#define AT91_MATRIX_RCB6 (1 << 6)
|
||||
#define AT91_MATRIX_RCB7 (1 << 7)
|
||||
#define AT91_MATRIX_RCB8 (1 << 8)
|
||||
|
||||
#define AT91_MATRIX_TCMR 0x114 /* TCM Configuration Register */
|
||||
#define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */
|
||||
#define AT91_MATRIX_ITCM_0 (0 << 0)
|
||||
#define AT91_MATRIX_ITCM_16 (5 << 0)
|
||||
#define AT91_MATRIX_ITCM_32 (6 << 0)
|
||||
#define AT91_MATRIX_DTCM_SIZE (0xf << 4) /* Size of DTCM enabled memory block */
|
||||
#define AT91_MATRIX_DTCM_0 (0 << 4)
|
||||
#define AT91_MATRIX_DTCM_16 (5 << 4)
|
||||
#define AT91_MATRIX_DTCM_32 (6 << 4)
|
||||
|
||||
#define AT91_MATRIX_EBI0CSA 0x120 /* EBI0 Chip Select Assignment Register */
|
||||
#define AT91_MATRIX_EBI0_CS1A (1 << 1) /* Chip Select 1 Assignment */
|
||||
#define AT91_MATRIX_EBI0_CS1A_SMC (0 << 1)
|
||||
#define AT91_MATRIX_EBI0_CS1A_SDRAMC (1 << 1)
|
||||
#define AT91_MATRIX_EBI0_CS3A (1 << 3) /* Chip Select 3 Assignment */
|
||||
#define AT91_MATRIX_EBI0_CS3A_SMC (0 << 3)
|
||||
#define AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA (1 << 3)
|
||||
#define AT91_MATRIX_EBI0_CS4A (1 << 4) /* Chip Select 4 Assignment */
|
||||
#define AT91_MATRIX_EBI0_CS4A_SMC (0 << 4)
|
||||
#define AT91_MATRIX_EBI0_CS4A_SMC_CF1 (1 << 4)
|
||||
#define AT91_MATRIX_EBI0_CS5A (1 << 5) /* Chip Select 5 Assignment */
|
||||
#define AT91_MATRIX_EBI0_CS5A_SMC (0 << 5)
|
||||
#define AT91_MATRIX_EBI0_CS5A_SMC_CF2 (1 << 5)
|
||||
#define AT91_MATRIX_EBI0_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
|
||||
#define AT91_MATRIX_EBI0_VDDIOMSEL (1 << 16) /* Memory voltage selection */
|
||||
#define AT91_MATRIX_EBI0_VDDIOMSEL_1_8V (0 << 16)
|
||||
#define AT91_MATRIX_EBI0_VDDIOMSEL_3_3V (1 << 16)
|
||||
|
||||
#define AT91_MATRIX_EBI1CSA 0x124 /* EBI1 Chip Select Assignment Register */
|
||||
#define AT91_MATRIX_EBI1_CS1A (1 << 1) /* Chip Select 1 Assignment */
|
||||
#define AT91_MATRIX_EBI1_CS1A_SMC (0 << 1)
|
||||
#define AT91_MATRIX_EBI1_CS1A_SDRAMC (1 << 1)
|
||||
#define AT91_MATRIX_EBI1_CS2A (1 << 3) /* Chip Select 3 Assignment */
|
||||
#define AT91_MATRIX_EBI1_CS2A_SMC (0 << 3)
|
||||
#define AT91_MATRIX_EBI1_CS2A_SMC_SMARTMEDIA (1 << 3)
|
||||
#define AT91_MATRIX_EBI1_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
|
||||
#define AT91_MATRIX_EBI1_VDDIOMSEL (1 << 16) /* Memory voltage selection */
|
||||
#define AT91_MATRIX_EBI1_VDDIOMSEL_1_8V (0 << 16)
|
||||
#define AT91_MATRIX_EBI1_VDDIOMSEL_3_3V (1 << 16)
|
||||
|
||||
#endif
|
||||
@ -16,8 +16,6 @@
|
||||
#ifndef AT91SAM9_SMC_H
|
||||
#define AT91SAM9_SMC_H
|
||||
|
||||
#include <mach/cpu.h>
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
struct sam9_smc_config {
|
||||
/* Setup register */
|
||||
|
||||
@ -1,143 +0,0 @@
|
||||
/*
|
||||
* Chip-specific header file for the AT91SAM9G45 family
|
||||
*
|
||||
* Copyright (C) 2008-2009 Atmel Corporation.
|
||||
*
|
||||
* Common definitions.
|
||||
* Based on AT91SAM9G45 preliminary datasheet.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*/
|
||||
|
||||
#ifndef AT91SAM9G45_H
|
||||
#define AT91SAM9G45_H
|
||||
|
||||
/*
|
||||
* Peripheral identifiers/interrupts.
|
||||
*/
|
||||
#define AT91SAM9G45_ID_PIOA 2 /* Parallel I/O Controller A */
|
||||
#define AT91SAM9G45_ID_PIOB 3 /* Parallel I/O Controller B */
|
||||
#define AT91SAM9G45_ID_PIOC 4 /* Parallel I/O Controller C */
|
||||
#define AT91SAM9G45_ID_PIODE 5 /* Parallel I/O Controller D and E */
|
||||
#define AT91SAM9G45_ID_TRNG 6 /* True Random Number Generator */
|
||||
#define AT91SAM9G45_ID_US0 7 /* USART 0 */
|
||||
#define AT91SAM9G45_ID_US1 8 /* USART 1 */
|
||||
#define AT91SAM9G45_ID_US2 9 /* USART 2 */
|
||||
#define AT91SAM9G45_ID_US3 10 /* USART 3 */
|
||||
#define AT91SAM9G45_ID_MCI0 11 /* High Speed Multimedia Card Interface 0 */
|
||||
#define AT91SAM9G45_ID_TWI0 12 /* Two-Wire Interface 0 */
|
||||
#define AT91SAM9G45_ID_TWI1 13 /* Two-Wire Interface 1 */
|
||||
#define AT91SAM9G45_ID_SPI0 14 /* Serial Peripheral Interface 0 */
|
||||
#define AT91SAM9G45_ID_SPI1 15 /* Serial Peripheral Interface 1 */
|
||||
#define AT91SAM9G45_ID_SSC0 16 /* Synchronous Serial Controller 0 */
|
||||
#define AT91SAM9G45_ID_SSC1 17 /* Synchronous Serial Controller 1 */
|
||||
#define AT91SAM9G45_ID_TCB 18 /* Timer Counter 0, 1, 2, 3, 4 and 5 */
|
||||
#define AT91SAM9G45_ID_PWMC 19 /* Pulse Width Modulation Controller */
|
||||
#define AT91SAM9G45_ID_TSC 20 /* Touch Screen ADC Controller */
|
||||
#define AT91SAM9G45_ID_DMA 21 /* DMA Controller */
|
||||
#define AT91SAM9G45_ID_UHPHS 22 /* USB Host High Speed */
|
||||
#define AT91SAM9G45_ID_LCDC 23 /* LCD Controller */
|
||||
#define AT91SAM9G45_ID_AC97C 24 /* AC97 Controller */
|
||||
#define AT91SAM9G45_ID_EMAC 25 /* Ethernet MAC */
|
||||
#define AT91SAM9G45_ID_ISI 26 /* Image Sensor Interface */
|
||||
#define AT91SAM9G45_ID_UDPHS 27 /* USB Device High Speed */
|
||||
#define AT91SAM9G45_ID_AESTDESSHA 28 /* AES + T-DES + SHA */
|
||||
#define AT91SAM9G45_ID_MCI1 29 /* High Speed Multimedia Card Interface 1 */
|
||||
#define AT91SAM9G45_ID_VDEC 30 /* Video Decoder */
|
||||
#define AT91SAM9G45_ID_IRQ0 31 /* Advanced Interrupt Controller */
|
||||
|
||||
/*
|
||||
* User Peripheral physical base addresses.
|
||||
*/
|
||||
#define AT91SAM9G45_BASE_UDPHS 0xfff78000
|
||||
#define AT91SAM9G45_BASE_TCB0 0xfff7c000
|
||||
#define AT91SAM9G45_BASE_TC0 0xfff7c000
|
||||
#define AT91SAM9G45_BASE_TC1 0xfff7c040
|
||||
#define AT91SAM9G45_BASE_TC2 0xfff7c080
|
||||
#define AT91SAM9G45_BASE_MCI0 0xfff80000
|
||||
#define AT91SAM9G45_BASE_TWI0 0xfff84000
|
||||
#define AT91SAM9G45_BASE_TWI1 0xfff88000
|
||||
#define AT91SAM9G45_BASE_US0 0xfff8c000
|
||||
#define AT91SAM9G45_BASE_US1 0xfff90000
|
||||
#define AT91SAM9G45_BASE_US2 0xfff94000
|
||||
#define AT91SAM9G45_BASE_US3 0xfff98000
|
||||
#define AT91SAM9G45_BASE_SSC0 0xfff9c000
|
||||
#define AT91SAM9G45_BASE_SSC1 0xfffa0000
|
||||
#define AT91SAM9G45_BASE_SPI0 0xfffa4000
|
||||
#define AT91SAM9G45_BASE_SPI1 0xfffa8000
|
||||
#define AT91SAM9G45_BASE_AC97C 0xfffac000
|
||||
#define AT91SAM9G45_BASE_TSC 0xfffb0000
|
||||
#define AT91SAM9G45_BASE_ISI 0xfffb4000
|
||||
#define AT91SAM9G45_BASE_PWMC 0xfffb8000
|
||||
#define AT91SAM9G45_BASE_EMAC 0xfffbc000
|
||||
#define AT91SAM9G45_BASE_AES 0xfffc0000
|
||||
#define AT91SAM9G45_BASE_TDES 0xfffc4000
|
||||
#define AT91SAM9G45_BASE_SHA 0xfffc8000
|
||||
#define AT91SAM9G45_BASE_TRNG 0xfffcc000
|
||||
#define AT91SAM9G45_BASE_MCI1 0xfffd0000
|
||||
#define AT91SAM9G45_BASE_TCB1 0xfffd4000
|
||||
#define AT91SAM9G45_BASE_TC3 0xfffd4000
|
||||
#define AT91SAM9G45_BASE_TC4 0xfffd4040
|
||||
#define AT91SAM9G45_BASE_TC5 0xfffd4080
|
||||
|
||||
/*
|
||||
* System Peripherals
|
||||
*/
|
||||
#define AT91SAM9G45_BASE_ECC 0xffffe200
|
||||
#define AT91SAM9G45_BASE_DDRSDRC1 0xffffe400
|
||||
#define AT91SAM9G45_BASE_DDRSDRC0 0xffffe600
|
||||
#define AT91SAM9G45_BASE_DMA 0xffffec00
|
||||
#define AT91SAM9G45_BASE_SMC 0xffffe800
|
||||
#define AT91SAM9G45_BASE_MATRIX 0xffffea00
|
||||
#define AT91SAM9G45_BASE_DBGU AT91_BASE_DBGU1
|
||||
#define AT91SAM9G45_BASE_PIOA 0xfffff200
|
||||
#define AT91SAM9G45_BASE_PIOB 0xfffff400
|
||||
#define AT91SAM9G45_BASE_PIOC 0xfffff600
|
||||
#define AT91SAM9G45_BASE_PIOD 0xfffff800
|
||||
#define AT91SAM9G45_BASE_PIOE 0xfffffa00
|
||||
#define AT91SAM9G45_BASE_RSTC 0xfffffd00
|
||||
#define AT91SAM9G45_BASE_SHDWC 0xfffffd10
|
||||
#define AT91SAM9G45_BASE_RTT 0xfffffd20
|
||||
#define AT91SAM9G45_BASE_PIT 0xfffffd30
|
||||
#define AT91SAM9G45_BASE_WDT 0xfffffd40
|
||||
#define AT91SAM9G45_BASE_RTC 0xfffffdb0
|
||||
#define AT91SAM9G45_BASE_GPBR 0xfffffd60
|
||||
|
||||
/*
|
||||
* Internal Memory.
|
||||
*/
|
||||
#define AT91SAM9G45_SRAM_BASE 0x00300000 /* Internal SRAM base address */
|
||||
#define AT91SAM9G45_SRAM_SIZE SZ_64K /* Internal SRAM size (64Kb) */
|
||||
|
||||
#define AT91SAM9G45_ROM_BASE 0x00400000 /* Internal ROM base address */
|
||||
#define AT91SAM9G45_ROM_SIZE SZ_64K /* Internal ROM size (64Kb) */
|
||||
|
||||
#define AT91SAM9G45_LCDC_BASE 0x00500000 /* LCD Controller */
|
||||
#define AT91SAM9G45_UDPHS_FIFO 0x00600000 /* USB Device HS controller */
|
||||
#define AT91SAM9G45_OHCI_BASE 0x00700000 /* USB Host controller (OHCI) */
|
||||
#define AT91SAM9G45_EHCI_BASE 0x00800000 /* USB Host controller (EHCI) */
|
||||
#define AT91SAM9G45_VDEC_BASE 0x00900000 /* Video Decoder Controller */
|
||||
|
||||
/*
|
||||
* DMA peripheral identifiers
|
||||
* for hardware handshaking interface
|
||||
*/
|
||||
#define AT_DMA_ID_MCI0 0
|
||||
#define AT_DMA_ID_SPI0_TX 1
|
||||
#define AT_DMA_ID_SPI0_RX 2
|
||||
#define AT_DMA_ID_SPI1_TX 3
|
||||
#define AT_DMA_ID_SPI1_RX 4
|
||||
#define AT_DMA_ID_SSC0_TX 5
|
||||
#define AT_DMA_ID_SSC0_RX 6
|
||||
#define AT_DMA_ID_SSC1_TX 7
|
||||
#define AT_DMA_ID_SSC1_RX 8
|
||||
#define AT_DMA_ID_AC97_TX 9
|
||||
#define AT_DMA_ID_AC97_RX 10
|
||||
#define AT_DMA_ID_AES_TX 11
|
||||
#define AT_DMA_ID_AES_RX 12
|
||||
#define AT_DMA_ID_MCI1 13
|
||||
|
||||
#endif
|
||||
@ -1,153 +0,0 @@
|
||||
/*
|
||||
* Matrix-centric header file for the AT91SAM9G45 family
|
||||
*
|
||||
* Copyright (C) 2008-2009 Atmel Corporation.
|
||||
*
|
||||
* Memory Controllers (MATRIX, EBI) - System peripherals registers.
|
||||
* Based on AT91SAM9G45 preliminary datasheet.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*/
|
||||
|
||||
#ifndef AT91SAM9G45_MATRIX_H
|
||||
#define AT91SAM9G45_MATRIX_H
|
||||
|
||||
#define AT91_MATRIX_MCFG0 0x00 /* Master Configuration Register 0 */
|
||||
#define AT91_MATRIX_MCFG1 0x04 /* Master Configuration Register 1 */
|
||||
#define AT91_MATRIX_MCFG2 0x08 /* Master Configuration Register 2 */
|
||||
#define AT91_MATRIX_MCFG3 0x0C /* Master Configuration Register 3 */
|
||||
#define AT91_MATRIX_MCFG4 0x10 /* Master Configuration Register 4 */
|
||||
#define AT91_MATRIX_MCFG5 0x14 /* Master Configuration Register 5 */
|
||||
#define AT91_MATRIX_MCFG6 0x18 /* Master Configuration Register 6 */
|
||||
#define AT91_MATRIX_MCFG7 0x1C /* Master Configuration Register 7 */
|
||||
#define AT91_MATRIX_MCFG8 0x20 /* Master Configuration Register 8 */
|
||||
#define AT91_MATRIX_MCFG9 0x24 /* Master Configuration Register 9 */
|
||||
#define AT91_MATRIX_MCFG10 0x28 /* Master Configuration Register 10 */
|
||||
#define AT91_MATRIX_MCFG11 0x2C /* Master Configuration Register 11 */
|
||||
#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */
|
||||
#define AT91_MATRIX_ULBT_INFINITE (0 << 0)
|
||||
#define AT91_MATRIX_ULBT_SINGLE (1 << 0)
|
||||
#define AT91_MATRIX_ULBT_FOUR (2 << 0)
|
||||
#define AT91_MATRIX_ULBT_EIGHT (3 << 0)
|
||||
#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0)
|
||||
#define AT91_MATRIX_ULBT_THIRTYTWO (5 << 0)
|
||||
#define AT91_MATRIX_ULBT_SIXTYFOUR (6 << 0)
|
||||
#define AT91_MATRIX_ULBT_128 (7 << 0)
|
||||
|
||||
#define AT91_MATRIX_SCFG0 0x40 /* Slave Configuration Register 0 */
|
||||
#define AT91_MATRIX_SCFG1 0x44 /* Slave Configuration Register 1 */
|
||||
#define AT91_MATRIX_SCFG2 0x48 /* Slave Configuration Register 2 */
|
||||
#define AT91_MATRIX_SCFG3 0x4C /* Slave Configuration Register 3 */
|
||||
#define AT91_MATRIX_SCFG4 0x50 /* Slave Configuration Register 4 */
|
||||
#define AT91_MATRIX_SCFG5 0x54 /* Slave Configuration Register 5 */
|
||||
#define AT91_MATRIX_SCFG6 0x58 /* Slave Configuration Register 6 */
|
||||
#define AT91_MATRIX_SCFG7 0x5C /* Slave Configuration Register 7 */
|
||||
#define AT91_MATRIX_SLOT_CYCLE (0x1ff << 0) /* Maximum Number of Allowed Cycles for a Burst */
|
||||
#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */
|
||||
#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
|
||||
#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
|
||||
#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
|
||||
#define AT91_MATRIX_FIXED_DEFMSTR (0xf << 18) /* Fixed Index of Default Master */
|
||||
|
||||
#define AT91_MATRIX_PRAS0 0x80 /* Priority Register A for Slave 0 */
|
||||
#define AT91_MATRIX_PRBS0 0x84 /* Priority Register B for Slave 0 */
|
||||
#define AT91_MATRIX_PRAS1 0x88 /* Priority Register A for Slave 1 */
|
||||
#define AT91_MATRIX_PRBS1 0x8C /* Priority Register B for Slave 1 */
|
||||
#define AT91_MATRIX_PRAS2 0x90 /* Priority Register A for Slave 2 */
|
||||
#define AT91_MATRIX_PRBS2 0x94 /* Priority Register B for Slave 2 */
|
||||
#define AT91_MATRIX_PRAS3 0x98 /* Priority Register A for Slave 3 */
|
||||
#define AT91_MATRIX_PRBS3 0x9C /* Priority Register B for Slave 3 */
|
||||
#define AT91_MATRIX_PRAS4 0xA0 /* Priority Register A for Slave 4 */
|
||||
#define AT91_MATRIX_PRBS4 0xA4 /* Priority Register B for Slave 4 */
|
||||
#define AT91_MATRIX_PRAS5 0xA8 /* Priority Register A for Slave 5 */
|
||||
#define AT91_MATRIX_PRBS5 0xAC /* Priority Register B for Slave 5 */
|
||||
#define AT91_MATRIX_PRAS6 0xB0 /* Priority Register A for Slave 6 */
|
||||
#define AT91_MATRIX_PRBS6 0xB4 /* Priority Register B for Slave 6 */
|
||||
#define AT91_MATRIX_PRAS7 0xB8 /* Priority Register A for Slave 7 */
|
||||
#define AT91_MATRIX_PRBS7 0xBC /* Priority Register B for Slave 7 */
|
||||
#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */
|
||||
#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */
|
||||
#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */
|
||||
#define AT91_MATRIX_M3PR (3 << 12) /* Master 3 Priority */
|
||||
#define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */
|
||||
#define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */
|
||||
#define AT91_MATRIX_M6PR (3 << 24) /* Master 6 Priority */
|
||||
#define AT91_MATRIX_M7PR (3 << 28) /* Master 7 Priority */
|
||||
#define AT91_MATRIX_M8PR (3 << 0) /* Master 8 Priority (in Register B) */
|
||||
#define AT91_MATRIX_M9PR (3 << 4) /* Master 9 Priority (in Register B) */
|
||||
#define AT91_MATRIX_M10PR (3 << 8) /* Master 10 Priority (in Register B) */
|
||||
#define AT91_MATRIX_M11PR (3 << 12) /* Master 11 Priority (in Register B) */
|
||||
|
||||
#define AT91_MATRIX_MRCR 0x100 /* Master Remap Control Register */
|
||||
#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
|
||||
#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
|
||||
#define AT91_MATRIX_RCB2 (1 << 2)
|
||||
#define AT91_MATRIX_RCB3 (1 << 3)
|
||||
#define AT91_MATRIX_RCB4 (1 << 4)
|
||||
#define AT91_MATRIX_RCB5 (1 << 5)
|
||||
#define AT91_MATRIX_RCB6 (1 << 6)
|
||||
#define AT91_MATRIX_RCB7 (1 << 7)
|
||||
#define AT91_MATRIX_RCB8 (1 << 8)
|
||||
#define AT91_MATRIX_RCB9 (1 << 9)
|
||||
#define AT91_MATRIX_RCB10 (1 << 10)
|
||||
#define AT91_MATRIX_RCB11 (1 << 11)
|
||||
|
||||
#define AT91_MATRIX_TCMR 0x110 /* TCM Configuration Register */
|
||||
#define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */
|
||||
#define AT91_MATRIX_ITCM_0 (0 << 0)
|
||||
#define AT91_MATRIX_ITCM_32 (6 << 0)
|
||||
#define AT91_MATRIX_DTCM_SIZE (0xf << 4) /* Size of DTCM enabled memory block */
|
||||
#define AT91_MATRIX_DTCM_0 (0 << 4)
|
||||
#define AT91_MATRIX_DTCM_32 (6 << 4)
|
||||
#define AT91_MATRIX_DTCM_64 (7 << 4)
|
||||
#define AT91_MATRIX_TCM_NWS (0x1 << 11) /* Wait state TCM register */
|
||||
#define AT91_MATRIX_TCM_NO_WS (0x0 << 11)
|
||||
#define AT91_MATRIX_TCM_ONE_WS (0x1 << 11)
|
||||
|
||||
#define AT91_MATRIX_VIDEO 0x118 /* Video Mode Configuration Register */
|
||||
#define AT91C_VDEC_SEL (0x1 << 0) /* Video Mode Selection */
|
||||
#define AT91C_VDEC_SEL_OFF (0 << 0)
|
||||
#define AT91C_VDEC_SEL_ON (1 << 0)
|
||||
|
||||
#define AT91_MATRIX_EBICSA 0x128 /* EBI Chip Select Assignment Register */
|
||||
#define AT91_MATRIX_EBI_CS1A (1 << 1) /* Chip Select 1 Assignment */
|
||||
#define AT91_MATRIX_EBI_CS1A_SMC (0 << 1)
|
||||
#define AT91_MATRIX_EBI_CS1A_SDRAMC (1 << 1)
|
||||
#define AT91_MATRIX_EBI_CS3A (1 << 3) /* Chip Select 3 Assignment */
|
||||
#define AT91_MATRIX_EBI_CS3A_SMC (0 << 3)
|
||||
#define AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA (1 << 3)
|
||||
#define AT91_MATRIX_EBI_CS4A (1 << 4) /* Chip Select 4 Assignment */
|
||||
#define AT91_MATRIX_EBI_CS4A_SMC (0 << 4)
|
||||
#define AT91_MATRIX_EBI_CS4A_SMC_CF0 (1 << 4)
|
||||
#define AT91_MATRIX_EBI_CS5A (1 << 5) /* Chip Select 5 Assignment */
|
||||
#define AT91_MATRIX_EBI_CS5A_SMC (0 << 5)
|
||||
#define AT91_MATRIX_EBI_CS5A_SMC_CF1 (1 << 5)
|
||||
#define AT91_MATRIX_EBI_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
|
||||
#define AT91_MATRIX_EBI_DBPU_ON (0 << 8)
|
||||
#define AT91_MATRIX_EBI_DBPU_OFF (1 << 8)
|
||||
#define AT91_MATRIX_EBI_VDDIOMSEL (1 << 16) /* Memory voltage selection */
|
||||
#define AT91_MATRIX_EBI_VDDIOMSEL_1_8V (0 << 16)
|
||||
#define AT91_MATRIX_EBI_VDDIOMSEL_3_3V (1 << 16)
|
||||
#define AT91_MATRIX_EBI_EBI_IOSR (1 << 17) /* EBI I/O slew rate selection */
|
||||
#define AT91_MATRIX_EBI_EBI_IOSR_REDUCED (0 << 17)
|
||||
#define AT91_MATRIX_EBI_EBI_IOSR_NORMAL (1 << 17)
|
||||
#define AT91_MATRIX_EBI_DDR_IOSR (1 << 18) /* DDR2 dedicated port I/O slew rate selection */
|
||||
#define AT91_MATRIX_EBI_DDR_IOSR_REDUCED (0 << 18)
|
||||
#define AT91_MATRIX_EBI_DDR_IOSR_NORMAL (1 << 18)
|
||||
|
||||
#define AT91_MATRIX_WPMR 0x1E4 /* Write Protect Mode Register */
|
||||
#define AT91_MATRIX_WPMR_WPEN (1 << 0) /* Write Protect ENable */
|
||||
#define AT91_MATRIX_WPMR_WP_WPDIS (0 << 0)
|
||||
#define AT91_MATRIX_WPMR_WP_WPEN (1 << 0)
|
||||
#define AT91_MATRIX_WPMR_WPKEY (0xFFFFFF << 8) /* Write Protect KEY */
|
||||
|
||||
#define AT91_MATRIX_WPSR 0x1E8 /* Write Protect Status Register */
|
||||
#define AT91_MATRIX_WPSR_WPVS (1 << 0) /* Write Protect Violation Status */
|
||||
#define AT91_MATRIX_WPSR_NO_WPV (0 << 0)
|
||||
#define AT91_MATRIX_WPSR_WPV (1 << 0)
|
||||
#define AT91_MATRIX_WPSR_WPVSRC (0xFFFF << 8) /* Write Protect Violation Source */
|
||||
|
||||
#endif
|
||||
@ -1,65 +0,0 @@
|
||||
/*
|
||||
* SoC specific header file for the AT91SAM9N12
|
||||
*
|
||||
* Copyright (C) 2012 Atmel Corporation
|
||||
*
|
||||
* Common definitions, based on AT91SAM9N12 SoC datasheet
|
||||
*
|
||||
* Licensed under GPLv2 or later
|
||||
*/
|
||||
|
||||
#ifndef _AT91SAM9N12_H_
|
||||
#define _AT91SAM9N12_H_
|
||||
|
||||
/*
|
||||
* Peripheral identifiers/interrupts.
|
||||
*/
|
||||
#define AT91SAM9N12_ID_PIOAB 2 /* Parallel I/O Controller A and B */
|
||||
#define AT91SAM9N12_ID_PIOCD 3 /* Parallel I/O Controller C and D */
|
||||
#define AT91SAM9N12_ID_FUSE 4 /* FUSE Controller */
|
||||
#define AT91SAM9N12_ID_USART0 5 /* USART 0 */
|
||||
#define AT91SAM9N12_ID_USART1 6 /* USART 1 */
|
||||
#define AT91SAM9N12_ID_USART2 7 /* USART 2 */
|
||||
#define AT91SAM9N12_ID_USART3 8 /* USART 3 */
|
||||
#define AT91SAM9N12_ID_TWI0 9 /* Two-Wire Interface 0 */
|
||||
#define AT91SAM9N12_ID_TWI1 10 /* Two-Wire Interface 1 */
|
||||
#define AT91SAM9N12_ID_MCI 12 /* High Speed Multimedia Card Interface */
|
||||
#define AT91SAM9N12_ID_SPI0 13 /* Serial Peripheral Interface 0 */
|
||||
#define AT91SAM9N12_ID_SPI1 14 /* Serial Peripheral Interface 1 */
|
||||
#define AT91SAM9N12_ID_UART0 15 /* UART 0 */
|
||||
#define AT91SAM9N12_ID_UART1 16 /* UART 1 */
|
||||
#define AT91SAM9N12_ID_TCB 17 /* Timer Counter 0, 1, 2, 3, 4 and 5 */
|
||||
#define AT91SAM9N12_ID_PWM 18 /* Pulse Width Modulation Controller */
|
||||
#define AT91SAM9N12_ID_ADC 19 /* ADC Controller */
|
||||
#define AT91SAM9N12_ID_DMA 20 /* DMA Controller */
|
||||
#define AT91SAM9N12_ID_UHP 22 /* USB Host High Speed */
|
||||
#define AT91SAM9N12_ID_UDP 23 /* USB Device High Speed */
|
||||
#define AT91SAM9N12_ID_LCDC 25 /* LCD Controller */
|
||||
#define AT91SAM9N12_ID_ISI 25 /* Image Sensor Interface */
|
||||
#define AT91SAM9N12_ID_SSC 28 /* Synchronous Serial Controller */
|
||||
#define AT91SAM9N12_ID_TRNG 30 /* TRNG */
|
||||
#define AT91SAM9N12_ID_IRQ0 31 /* Advanced Interrupt Controller */
|
||||
|
||||
/*
|
||||
* User Peripheral physical base addresses.
|
||||
*/
|
||||
#define AT91SAM9N12_BASE_USART0 0xf801c000
|
||||
#define AT91SAM9N12_BASE_USART1 0xf8020000
|
||||
#define AT91SAM9N12_BASE_USART2 0xf8024000
|
||||
#define AT91SAM9N12_BASE_USART3 0xf8028000
|
||||
|
||||
/*
|
||||
* System Peripherals
|
||||
*/
|
||||
#define AT91SAM9N12_BASE_RTC 0xfffffeb0
|
||||
|
||||
/*
|
||||
* Internal Memory.
|
||||
*/
|
||||
#define AT91SAM9N12_SRAM_BASE 0x00300000 /* Internal SRAM base address */
|
||||
#define AT91SAM9N12_SRAM_SIZE SZ_32K /* Internal SRAM size (32Kb) */
|
||||
|
||||
#define AT91SAM9N12_ROM_BASE 0x00100000 /* Internal ROM base address */
|
||||
#define AT91SAM9N12_ROM_SIZE SZ_128K /* Internal ROM size (128Kb) */
|
||||
|
||||
#endif
|
||||
@ -1,53 +0,0 @@
|
||||
/*
|
||||
* Matrix-centric header file for the AT91SAM9N12
|
||||
*
|
||||
* Copyright (C) 2012 Atmel Corporation.
|
||||
*
|
||||
* Only EBI related registers.
|
||||
* Write Protect register definitions may be useful.
|
||||
*
|
||||
* Licensed under GPLv2 or later.
|
||||
*/
|
||||
|
||||
#ifndef _AT91SAM9N12_MATRIX_H_
|
||||
#define _AT91SAM9N12_MATRIX_H_
|
||||
|
||||
#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x118) /* EBI Chip Select Assignment Register */
|
||||
#define AT91_MATRIX_EBI_CS1A (1 << 1) /* Chip Select 1 Assignment */
|
||||
#define AT91_MATRIX_EBI_CS1A_SMC (0 << 1)
|
||||
#define AT91_MATRIX_EBI_CS1A_SDRAMC (1 << 1)
|
||||
#define AT91_MATRIX_EBI_CS3A (1 << 3) /* Chip Select 3 Assignment */
|
||||
#define AT91_MATRIX_EBI_CS3A_SMC (0 << 3)
|
||||
#define AT91_MATRIX_EBI_CS3A_SMC_NANDFLASH (1 << 3)
|
||||
#define AT91_MATRIX_EBI_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
|
||||
#define AT91_MATRIX_EBI_DBPU_ON (0 << 8)
|
||||
#define AT91_MATRIX_EBI_DBPU_OFF (1 << 8)
|
||||
#define AT91_MATRIX_EBI_VDDIOMSEL (1 << 16) /* Memory voltage selection */
|
||||
#define AT91_MATRIX_EBI_VDDIOMSEL_1_8V (0 << 16)
|
||||
#define AT91_MATRIX_EBI_VDDIOMSEL_3_3V (1 << 16)
|
||||
#define AT91_MATRIX_EBI_EBI_IOSR (1 << 17) /* EBI I/O slew rate selection */
|
||||
#define AT91_MATRIX_EBI_EBI_IOSR_REDUCED (0 << 17)
|
||||
#define AT91_MATRIX_EBI_EBI_IOSR_NORMAL (1 << 17)
|
||||
#define AT91_MATRIX_EBI_DDR_IOSR (1 << 18) /* DDR2 dedicated port I/O slew rate selection */
|
||||
#define AT91_MATRIX_EBI_DDR_IOSR_REDUCED (0 << 18)
|
||||
#define AT91_MATRIX_EBI_DDR_IOSR_NORMAL (1 << 18)
|
||||
#define AT91_MATRIX_NFD0_SELECT (1 << 24) /* NAND Flash Data Bus Selection */
|
||||
#define AT91_MATRIX_NFD0_ON_D0 (0 << 24)
|
||||
#define AT91_MATRIX_NFD0_ON_D16 (1 << 24)
|
||||
#define AT91_MATRIX_DDR_MP_EN (1 << 25) /* DDR Multi-port Enable */
|
||||
#define AT91_MATRIX_MP_OFF (0 << 25)
|
||||
#define AT91_MATRIX_MP_ON (1 << 25)
|
||||
|
||||
#define AT91_MATRIX_WPMR (AT91_MATRIX + 0x1E4) /* Write Protect Mode Register */
|
||||
#define AT91_MATRIX_WPMR_WPEN (1 << 0) /* Write Protect ENable */
|
||||
#define AT91_MATRIX_WPMR_WP_WPDIS (0 << 0)
|
||||
#define AT91_MATRIX_WPMR_WP_WPEN (1 << 0)
|
||||
#define AT91_MATRIX_WPMR_WPKEY (0xFFFFFF << 8) /* Write Protect KEY */
|
||||
|
||||
#define AT91_MATRIX_WPSR (AT91_MATRIX + 0x1E8) /* Write Protect Status Register */
|
||||
#define AT91_MATRIX_WPSR_WPVS (1 << 0) /* Write Protect Violation Status */
|
||||
#define AT91_MATRIX_WPSR_NO_WPV (0 << 0)
|
||||
#define AT91_MATRIX_WPSR_WPV (1 << 0)
|
||||
#define AT91_MATRIX_WPSR_WPVSRC (0xFFFF << 8) /* Write Protect Violation Source */
|
||||
|
||||
#endif
|
||||
@ -1,105 +0,0 @@
|
||||
/*
|
||||
* arch/arm/mach-at91/include/mach/at91sam9260.h
|
||||
*
|
||||
* Copyright (C) 2007 Atmel Corporation
|
||||
*
|
||||
* Common definitions.
|
||||
* Based on AT91SAM9RL datasheet revision A. (Preliminary)
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file COPYING in the main directory of this archive for
|
||||
* more details.
|
||||
*/
|
||||
|
||||
#ifndef AT91SAM9RL_H
|
||||
#define AT91SAM9RL_H
|
||||
|
||||
/*
|
||||
* Peripheral identifiers/interrupts.
|
||||
*/
|
||||
#define AT91SAM9RL_ID_PIOA 2 /* Parallel IO Controller A */
|
||||
#define AT91SAM9RL_ID_PIOB 3 /* Parallel IO Controller B */
|
||||
#define AT91SAM9RL_ID_PIOC 4 /* Parallel IO Controller C */
|
||||
#define AT91SAM9RL_ID_PIOD 5 /* Parallel IO Controller D */
|
||||
#define AT91SAM9RL_ID_US0 6 /* USART 0 */
|
||||
#define AT91SAM9RL_ID_US1 7 /* USART 1 */
|
||||
#define AT91SAM9RL_ID_US2 8 /* USART 2 */
|
||||
#define AT91SAM9RL_ID_US3 9 /* USART 3 */
|
||||
#define AT91SAM9RL_ID_MCI 10 /* Multimedia Card Interface */
|
||||
#define AT91SAM9RL_ID_TWI0 11 /* TWI 0 */
|
||||
#define AT91SAM9RL_ID_TWI1 12 /* TWI 1 */
|
||||
#define AT91SAM9RL_ID_SPI 13 /* Serial Peripheral Interface */
|
||||
#define AT91SAM9RL_ID_SSC0 14 /* Serial Synchronous Controller 0 */
|
||||
#define AT91SAM9RL_ID_SSC1 15 /* Serial Synchronous Controller 1 */
|
||||
#define AT91SAM9RL_ID_TC0 16 /* Timer Counter 0 */
|
||||
#define AT91SAM9RL_ID_TC1 17 /* Timer Counter 1 */
|
||||
#define AT91SAM9RL_ID_TC2 18 /* Timer Counter 2 */
|
||||
#define AT91SAM9RL_ID_PWMC 19 /* Pulse Width Modulation Controller */
|
||||
#define AT91SAM9RL_ID_TSC 20 /* Touch Screen Controller */
|
||||
#define AT91SAM9RL_ID_DMA 21 /* DMA Controller */
|
||||
#define AT91SAM9RL_ID_UDPHS 22 /* USB Device HS */
|
||||
#define AT91SAM9RL_ID_LCDC 23 /* LCD Controller */
|
||||
#define AT91SAM9RL_ID_AC97C 24 /* AC97 Controller */
|
||||
#define AT91SAM9RL_ID_IRQ0 31 /* Advanced Interrupt Controller (IRQ0) */
|
||||
|
||||
|
||||
/*
|
||||
* User Peripheral physical base addresses.
|
||||
*/
|
||||
#define AT91SAM9RL_BASE_TCB0 0xfffa0000
|
||||
#define AT91SAM9RL_BASE_TC0 0xfffa0000
|
||||
#define AT91SAM9RL_BASE_TC1 0xfffa0040
|
||||
#define AT91SAM9RL_BASE_TC2 0xfffa0080
|
||||
#define AT91SAM9RL_BASE_MCI 0xfffa4000
|
||||
#define AT91SAM9RL_BASE_TWI0 0xfffa8000
|
||||
#define AT91SAM9RL_BASE_TWI1 0xfffac000
|
||||
#define AT91SAM9RL_BASE_US0 0xfffb0000
|
||||
#define AT91SAM9RL_BASE_US1 0xfffb4000
|
||||
#define AT91SAM9RL_BASE_US2 0xfffb8000
|
||||
#define AT91SAM9RL_BASE_US3 0xfffbc000
|
||||
#define AT91SAM9RL_BASE_SSC0 0xfffc0000
|
||||
#define AT91SAM9RL_BASE_SSC1 0xfffc4000
|
||||
#define AT91SAM9RL_BASE_PWMC 0xfffc8000
|
||||
#define AT91SAM9RL_BASE_SPI 0xfffcc000
|
||||
#define AT91SAM9RL_BASE_TSC 0xfffd0000
|
||||
#define AT91SAM9RL_BASE_UDPHS 0xfffd4000
|
||||
#define AT91SAM9RL_BASE_AC97C 0xfffd8000
|
||||
|
||||
|
||||
/*
|
||||
* System Peripherals (offset from AT91_BASE_SYS)
|
||||
*/
|
||||
#define AT91_SCKCR (0xfffffd50 - AT91_BASE_SYS)
|
||||
|
||||
#define AT91SAM9RL_BASE_DMA 0xffffe600
|
||||
#define AT91SAM9RL_BASE_ECC 0xffffe800
|
||||
#define AT91SAM9RL_BASE_SDRAMC 0xffffea00
|
||||
#define AT91SAM9RL_BASE_SMC 0xffffec00
|
||||
#define AT91SAM9RL_BASE_MATRIX 0xffffee00
|
||||
#define AT91SAM9RL_BASE_DBGU AT91_BASE_DBGU0
|
||||
#define AT91SAM9RL_BASE_PIOA 0xfffff400
|
||||
#define AT91SAM9RL_BASE_PIOB 0xfffff600
|
||||
#define AT91SAM9RL_BASE_PIOC 0xfffff800
|
||||
#define AT91SAM9RL_BASE_PIOD 0xfffffa00
|
||||
#define AT91SAM9RL_BASE_RSTC 0xfffffd00
|
||||
#define AT91SAM9RL_BASE_SHDWC 0xfffffd10
|
||||
#define AT91SAM9RL_BASE_RTT 0xfffffd20
|
||||
#define AT91SAM9RL_BASE_PIT 0xfffffd30
|
||||
#define AT91SAM9RL_BASE_WDT 0xfffffd40
|
||||
#define AT91SAM9RL_BASE_GPBR 0xfffffd60
|
||||
#define AT91SAM9RL_BASE_RTC 0xfffffe00
|
||||
|
||||
|
||||
/*
|
||||
* Internal Memory.
|
||||
*/
|
||||
#define AT91SAM9RL_SRAM_BASE 0x00300000 /* Internal SRAM base address */
|
||||
#define AT91SAM9RL_SRAM_SIZE SZ_16K /* Internal SRAM size (16Kb) */
|
||||
|
||||
#define AT91SAM9RL_ROM_BASE 0x00400000 /* Internal ROM base address */
|
||||
#define AT91SAM9RL_ROM_SIZE (2 * SZ_16K) /* Internal ROM size (32Kb) */
|
||||
|
||||
#define AT91SAM9RL_LCDC_BASE 0x00500000 /* LCD Controller */
|
||||
#define AT91SAM9RL_UDPHS_FIFO 0x00600000 /* USB Device HS controller */
|
||||
|
||||
#endif
|
||||
@ -1,96 +0,0 @@
|
||||
/*
|
||||
* arch/arm/mach-at91/include/mach/at91sam9rl_matrix.h
|
||||
*
|
||||
* Copyright (C) 2007 Atmel Corporation
|
||||
*
|
||||
* Memory Controllers (MATRIX, EBI) - System peripherals registers.
|
||||
* Based on AT91SAM9RL datasheet revision A. (Preliminary)
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file COPYING in the main directory of this archive for
|
||||
* more details.
|
||||
*/
|
||||
|
||||
#ifndef AT91SAM9RL_MATRIX_H
|
||||
#define AT91SAM9RL_MATRIX_H
|
||||
|
||||
#define AT91_MATRIX_MCFG0 0x00 /* Master Configuration Register 0 */
|
||||
#define AT91_MATRIX_MCFG1 0x04 /* Master Configuration Register 1 */
|
||||
#define AT91_MATRIX_MCFG2 0x08 /* Master Configuration Register 2 */
|
||||
#define AT91_MATRIX_MCFG3 0x0C /* Master Configuration Register 3 */
|
||||
#define AT91_MATRIX_MCFG4 0x10 /* Master Configuration Register 4 */
|
||||
#define AT91_MATRIX_MCFG5 0x14 /* Master Configuration Register 5 */
|
||||
#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */
|
||||
#define AT91_MATRIX_ULBT_INFINITE (0 << 0)
|
||||
#define AT91_MATRIX_ULBT_SINGLE (1 << 0)
|
||||
#define AT91_MATRIX_ULBT_FOUR (2 << 0)
|
||||
#define AT91_MATRIX_ULBT_EIGHT (3 << 0)
|
||||
#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0)
|
||||
|
||||
#define AT91_MATRIX_SCFG0 0x40 /* Slave Configuration Register 0 */
|
||||
#define AT91_MATRIX_SCFG1 0x44 /* Slave Configuration Register 1 */
|
||||
#define AT91_MATRIX_SCFG2 0x48 /* Slave Configuration Register 2 */
|
||||
#define AT91_MATRIX_SCFG3 0x4C /* Slave Configuration Register 3 */
|
||||
#define AT91_MATRIX_SCFG4 0x50 /* Slave Configuration Register 4 */
|
||||
#define AT91_MATRIX_SCFG5 0x54 /* Slave Configuration Register 5 */
|
||||
#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */
|
||||
#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */
|
||||
#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
|
||||
#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
|
||||
#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
|
||||
#define AT91_MATRIX_FIXED_DEFMSTR (0xf << 18) /* Fixed Index of Default Master */
|
||||
#define AT91_MATRIX_ARBT (3 << 24) /* Arbitration Type */
|
||||
#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24)
|
||||
#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
|
||||
|
||||
#define AT91_MATRIX_PRAS0 0x80 /* Priority Register A for Slave 0 */
|
||||
#define AT91_MATRIX_PRAS1 0x88 /* Priority Register A for Slave 1 */
|
||||
#define AT91_MATRIX_PRAS2 0x90 /* Priority Register A for Slave 2 */
|
||||
#define AT91_MATRIX_PRAS3 0x98 /* Priority Register A for Slave 3 */
|
||||
#define AT91_MATRIX_PRAS4 0xA0 /* Priority Register A for Slave 4 */
|
||||
#define AT91_MATRIX_PRAS5 0xA8 /* Priority Register A for Slave 5 */
|
||||
#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */
|
||||
#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */
|
||||
#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */
|
||||
#define AT91_MATRIX_M3PR (3 << 12) /* Master 3 Priority */
|
||||
#define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */
|
||||
#define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */
|
||||
|
||||
#define AT91_MATRIX_MRCR 0x100 /* Master Remap Control Register */
|
||||
#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
|
||||
#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
|
||||
#define AT91_MATRIX_RCB2 (1 << 2)
|
||||
#define AT91_MATRIX_RCB3 (1 << 3)
|
||||
#define AT91_MATRIX_RCB4 (1 << 4)
|
||||
#define AT91_MATRIX_RCB5 (1 << 5)
|
||||
|
||||
#define AT91_MATRIX_TCMR 0x114 /* TCM Configuration Register */
|
||||
#define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */
|
||||
#define AT91_MATRIX_ITCM_0 (0 << 0)
|
||||
#define AT91_MATRIX_ITCM_16 (5 << 0)
|
||||
#define AT91_MATRIX_ITCM_32 (6 << 0)
|
||||
#define AT91_MATRIX_DTCM_SIZE (0xf << 4) /* Size of DTCM enabled memory block */
|
||||
#define AT91_MATRIX_DTCM_0 (0 << 4)
|
||||
#define AT91_MATRIX_DTCM_16 (5 << 4)
|
||||
#define AT91_MATRIX_DTCM_32 (6 << 4)
|
||||
|
||||
#define AT91_MATRIX_EBICSA 0x120 /* EBI0 Chip Select Assignment Register */
|
||||
#define AT91_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */
|
||||
#define AT91_MATRIX_CS1A_SMC (0 << 1)
|
||||
#define AT91_MATRIX_CS1A_SDRAMC (1 << 1)
|
||||
#define AT91_MATRIX_CS3A (1 << 3) /* Chip Select 3 Assignment */
|
||||
#define AT91_MATRIX_CS3A_SMC (0 << 3)
|
||||
#define AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3)
|
||||
#define AT91_MATRIX_CS4A (1 << 4) /* Chip Select 4 Assignment */
|
||||
#define AT91_MATRIX_CS4A_SMC (0 << 4)
|
||||
#define AT91_MATRIX_CS4A_SMC_CF1 (1 << 4)
|
||||
#define AT91_MATRIX_CS5A (1 << 5) /* Chip Select 5 Assignment */
|
||||
#define AT91_MATRIX_CS5A_SMC (0 << 5)
|
||||
#define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5)
|
||||
#define AT91_MATRIX_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
|
||||
#define AT91_MATRIX_VDDIOMSEL (1 << 16) /* Memory voltage selection */
|
||||
#define AT91_MATRIX_VDDIOMSEL_1_8V (0 << 16)
|
||||
#define AT91_MATRIX_VDDIOMSEL_3_3V (1 << 16)
|
||||
|
||||
|
||||
#endif
|
||||
@ -1,71 +0,0 @@
|
||||
/*
|
||||
* Chip-specific header file for the AT91SAM9x5 family
|
||||
*
|
||||
* Copyright (C) 2009-2012 Atmel Corporation.
|
||||
*
|
||||
* Common definitions.
|
||||
* Based on AT91SAM9x5 datasheet.
|
||||
*
|
||||
* Licensed under GPLv2 or later.
|
||||
*/
|
||||
|
||||
#ifndef AT91SAM9X5_H
|
||||
#define AT91SAM9X5_H
|
||||
|
||||
/*
|
||||
* Peripheral identifiers/interrupts.
|
||||
*/
|
||||
#define AT91SAM9X5_ID_PIOAB 2 /* Parallel I/O Controller A and B */
|
||||
#define AT91SAM9X5_ID_PIOCD 3 /* Parallel I/O Controller C and D */
|
||||
#define AT91SAM9X5_ID_SMD 4 /* SMD Soft Modem (SMD) */
|
||||
#define AT91SAM9X5_ID_USART0 5 /* USART 0 */
|
||||
#define AT91SAM9X5_ID_USART1 6 /* USART 1 */
|
||||
#define AT91SAM9X5_ID_USART2 7 /* USART 2 */
|
||||
#define AT91SAM9X5_ID_USART3 8 /* USART 3 */
|
||||
#define AT91SAM9X5_ID_TWI0 9 /* Two-Wire Interface 0 */
|
||||
#define AT91SAM9X5_ID_TWI1 10 /* Two-Wire Interface 1 */
|
||||
#define AT91SAM9X5_ID_TWI2 11 /* Two-Wire Interface 2 */
|
||||
#define AT91SAM9X5_ID_MCI0 12 /* High Speed Multimedia Card Interface 0 */
|
||||
#define AT91SAM9X5_ID_SPI0 13 /* Serial Peripheral Interface 0 */
|
||||
#define AT91SAM9X5_ID_SPI1 14 /* Serial Peripheral Interface 1 */
|
||||
#define AT91SAM9X5_ID_UART0 15 /* UART 0 */
|
||||
#define AT91SAM9X5_ID_UART1 16 /* UART 1 */
|
||||
#define AT91SAM9X5_ID_TCB 17 /* Timer Counter 0, 1, 2, 3, 4 and 5 */
|
||||
#define AT91SAM9X5_ID_PWM 18 /* Pulse Width Modulation Controller */
|
||||
#define AT91SAM9X5_ID_ADC 19 /* ADC Controller */
|
||||
#define AT91SAM9X5_ID_DMA0 20 /* DMA Controller 0 */
|
||||
#define AT91SAM9X5_ID_DMA1 21 /* DMA Controller 1 */
|
||||
#define AT91SAM9X5_ID_UHPHS 22 /* USB Host High Speed */
|
||||
#define AT91SAM9X5_ID_UDPHS 23 /* USB Device High Speed */
|
||||
#define AT91SAM9X5_ID_EMAC0 24 /* Ethernet MAC0 */
|
||||
#define AT91SAM9X5_ID_LCDC 25 /* LCD Controller */
|
||||
#define AT91SAM9X5_ID_ISI 25 /* Image Sensor Interface */
|
||||
#define AT91SAM9X5_ID_MCI1 26 /* High Speed Multimedia Card Interface 1 */
|
||||
#define AT91SAM9X5_ID_EMAC1 27 /* Ethernet MAC1 */
|
||||
#define AT91SAM9X5_ID_SSC 28 /* Synchronous Serial Controller */
|
||||
#define AT91SAM9X5_ID_CAN0 29 /* CAN Controller 0 */
|
||||
#define AT91SAM9X5_ID_CAN1 30 /* CAN Controller 1 */
|
||||
#define AT91SAM9X5_ID_IRQ0 31 /* Advanced Interrupt Controller */
|
||||
|
||||
/*
|
||||
* User Peripheral physical base addresses.
|
||||
*/
|
||||
#define AT91SAM9X5_BASE_USART0 0xf801c000
|
||||
#define AT91SAM9X5_BASE_USART1 0xf8020000
|
||||
#define AT91SAM9X5_BASE_USART2 0xf8024000
|
||||
|
||||
/*
|
||||
* System Peripherals
|
||||
*/
|
||||
#define AT91SAM9X5_BASE_RTC 0xfffffeb0
|
||||
|
||||
/*
|
||||
* Internal Memory.
|
||||
*/
|
||||
#define AT91SAM9X5_SRAM_BASE 0x00300000 /* Internal SRAM base address */
|
||||
#define AT91SAM9X5_SRAM_SIZE SZ_32K /* Internal SRAM size (32Kb) */
|
||||
|
||||
#define AT91SAM9X5_ROM_BASE 0x00400000 /* Internal ROM base address */
|
||||
#define AT91SAM9X5_ROM_SIZE SZ_64K /* Internal ROM size (64Kb) */
|
||||
|
||||
#endif
|
||||
@ -1,53 +0,0 @@
|
||||
/*
|
||||
* Matrix-centric header file for the AT91SAM9x5 family
|
||||
*
|
||||
* Copyright (C) 2009-2012 Atmel Corporation.
|
||||
*
|
||||
* Only EBI related registers.
|
||||
* Write Protect register definitions may be useful.
|
||||
*
|
||||
* Licensed under GPLv2 or later.
|
||||
*/
|
||||
|
||||
#ifndef AT91SAM9X5_MATRIX_H
|
||||
#define AT91SAM9X5_MATRIX_H
|
||||
|
||||
#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x120) /* EBI Chip Select Assignment Register */
|
||||
#define AT91_MATRIX_EBI_CS1A (1 << 1) /* Chip Select 1 Assignment */
|
||||
#define AT91_MATRIX_EBI_CS1A_SMC (0 << 1)
|
||||
#define AT91_MATRIX_EBI_CS1A_SDRAMC (1 << 1)
|
||||
#define AT91_MATRIX_EBI_CS3A (1 << 3) /* Chip Select 3 Assignment */
|
||||
#define AT91_MATRIX_EBI_CS3A_SMC (0 << 3)
|
||||
#define AT91_MATRIX_EBI_CS3A_SMC_NANDFLASH (1 << 3)
|
||||
#define AT91_MATRIX_EBI_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
|
||||
#define AT91_MATRIX_EBI_DBPU_ON (0 << 8)
|
||||
#define AT91_MATRIX_EBI_DBPU_OFF (1 << 8)
|
||||
#define AT91_MATRIX_EBI_VDDIOMSEL (1 << 16) /* Memory voltage selection */
|
||||
#define AT91_MATRIX_EBI_VDDIOMSEL_1_8V (0 << 16)
|
||||
#define AT91_MATRIX_EBI_VDDIOMSEL_3_3V (1 << 16)
|
||||
#define AT91_MATRIX_EBI_EBI_IOSR (1 << 17) /* EBI I/O slew rate selection */
|
||||
#define AT91_MATRIX_EBI_EBI_IOSR_REDUCED (0 << 17)
|
||||
#define AT91_MATRIX_EBI_EBI_IOSR_NORMAL (1 << 17)
|
||||
#define AT91_MATRIX_EBI_DDR_IOSR (1 << 18) /* DDR2 dedicated port I/O slew rate selection */
|
||||
#define AT91_MATRIX_EBI_DDR_IOSR_REDUCED (0 << 18)
|
||||
#define AT91_MATRIX_EBI_DDR_IOSR_NORMAL (1 << 18)
|
||||
#define AT91_MATRIX_NFD0_SELECT (1 << 24) /* NAND Flash Data Bus Selection */
|
||||
#define AT91_MATRIX_NFD0_ON_D0 (0 << 24)
|
||||
#define AT91_MATRIX_NFD0_ON_D16 (1 << 24)
|
||||
#define AT91_MATRIX_DDR_MP_EN (1 << 25) /* DDR Multi-port Enable */
|
||||
#define AT91_MATRIX_MP_OFF (0 << 25)
|
||||
#define AT91_MATRIX_MP_ON (1 << 25)
|
||||
|
||||
#define AT91_MATRIX_WPMR (AT91_MATRIX + 0x1E4) /* Write Protect Mode Register */
|
||||
#define AT91_MATRIX_WPMR_WPEN (1 << 0) /* Write Protect ENable */
|
||||
#define AT91_MATRIX_WPMR_WP_WPDIS (0 << 0)
|
||||
#define AT91_MATRIX_WPMR_WP_WPEN (1 << 0)
|
||||
#define AT91_MATRIX_WPMR_WPKEY (0xFFFFFF << 8) /* Write Protect KEY */
|
||||
|
||||
#define AT91_MATRIX_WPSR (AT91_MATRIX + 0x1E8) /* Write Protect Status Register */
|
||||
#define AT91_MATRIX_WPSR_WPVS (1 << 0) /* Write Protect Violation Status */
|
||||
#define AT91_MATRIX_WPSR_NO_WPV (0 << 0)
|
||||
#define AT91_MATRIX_WPSR_WPV (1 << 0)
|
||||
#define AT91_MATRIX_WPSR_WPVSRC (0xFFFF << 8) /* Write Protect Violation Source */
|
||||
|
||||
#endif
|
||||
@ -1,216 +0,0 @@
|
||||
/*
|
||||
* arch/arm/mach-at91/include/mach/cpu.h
|
||||
*
|
||||
* Copyright (C) 2006 SAN People
|
||||
* Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __MACH_CPU_H__
|
||||
#define __MACH_CPU_H__
|
||||
|
||||
#define ARCH_ID_AT91RM9200 0x09290780
|
||||
#define ARCH_ID_AT91SAM9260 0x019803a0
|
||||
#define ARCH_ID_AT91SAM9261 0x019703a0
|
||||
#define ARCH_ID_AT91SAM9263 0x019607a0
|
||||
#define ARCH_ID_AT91SAM9G10 0x019903a0
|
||||
#define ARCH_ID_AT91SAM9G20 0x019905a0
|
||||
#define ARCH_ID_AT91SAM9RL64 0x019b03a0
|
||||
#define ARCH_ID_AT91SAM9G45 0x819b05a0
|
||||
#define ARCH_ID_AT91SAM9G45MRL 0x819b05a2 /* aka 9G45-ES2 & non ES lots */
|
||||
#define ARCH_ID_AT91SAM9G45ES 0x819b05a1 /* 9G45-ES (Engineering Sample) */
|
||||
#define ARCH_ID_AT91SAM9X5 0x819a05a0
|
||||
#define ARCH_ID_AT91SAM9N12 0x819a07a0
|
||||
|
||||
#define ARCH_ID_AT91SAM9XE128 0x329973a0
|
||||
#define ARCH_ID_AT91SAM9XE256 0x329a93a0
|
||||
#define ARCH_ID_AT91SAM9XE512 0x329aa3a0
|
||||
|
||||
#define ARCH_ID_AT91M40800 0x14080044
|
||||
#define ARCH_ID_AT91R40807 0x44080746
|
||||
#define ARCH_ID_AT91M40807 0x14080745
|
||||
#define ARCH_ID_AT91R40008 0x44000840
|
||||
|
||||
#define ARCH_ID_SAMA5 0x8A5C07C0
|
||||
|
||||
#define ARCH_EXID_AT91SAM9M11 0x00000001
|
||||
#define ARCH_EXID_AT91SAM9M10 0x00000002
|
||||
#define ARCH_EXID_AT91SAM9G46 0x00000003
|
||||
#define ARCH_EXID_AT91SAM9G45 0x00000004
|
||||
|
||||
#define ARCH_EXID_AT91SAM9G15 0x00000000
|
||||
#define ARCH_EXID_AT91SAM9G35 0x00000001
|
||||
#define ARCH_EXID_AT91SAM9X35 0x00000002
|
||||
#define ARCH_EXID_AT91SAM9G25 0x00000003
|
||||
#define ARCH_EXID_AT91SAM9X25 0x00000004
|
||||
|
||||
#define ARCH_EXID_SAMA5D3 0x00004300
|
||||
#define ARCH_EXID_SAMA5D31 0x00444300
|
||||
#define ARCH_EXID_SAMA5D33 0x00414300
|
||||
#define ARCH_EXID_SAMA5D34 0x00414301
|
||||
#define ARCH_EXID_SAMA5D35 0x00584300
|
||||
#define ARCH_EXID_SAMA5D36 0x00004301
|
||||
|
||||
#define ARCH_EXID_SAMA5D4 0x00000007
|
||||
#define ARCH_EXID_SAMA5D41 0x00000001
|
||||
#define ARCH_EXID_SAMA5D42 0x00000002
|
||||
#define ARCH_EXID_SAMA5D43 0x00000003
|
||||
#define ARCH_EXID_SAMA5D44 0x00000004
|
||||
|
||||
#define ARCH_FAMILY_AT91SAM9 0x01900000
|
||||
#define ARCH_FAMILY_AT91SAM9XE 0x02900000
|
||||
|
||||
/* RM9200 type */
|
||||
#define ARCH_REVISON_9200_BGA (0 << 0)
|
||||
#define ARCH_REVISON_9200_PQFP (1 << 0)
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
enum at91_soc_type {
|
||||
/* 920T */
|
||||
AT91_SOC_RM9200,
|
||||
|
||||
/* SAM92xx */
|
||||
AT91_SOC_SAM9260, AT91_SOC_SAM9261, AT91_SOC_SAM9263,
|
||||
|
||||
/* SAM9Gxx */
|
||||
AT91_SOC_SAM9G10, AT91_SOC_SAM9G20, AT91_SOC_SAM9G45,
|
||||
|
||||
/* SAM9RL */
|
||||
AT91_SOC_SAM9RL,
|
||||
|
||||
/* SAM9X5 */
|
||||
AT91_SOC_SAM9X5,
|
||||
|
||||
/* SAM9N12 */
|
||||
AT91_SOC_SAM9N12,
|
||||
|
||||
/* SAMA5D3 */
|
||||
AT91_SOC_SAMA5D3,
|
||||
|
||||
/* SAMA5D4 */
|
||||
AT91_SOC_SAMA5D4,
|
||||
|
||||
/* Unknown type */
|
||||
AT91_SOC_UNKNOWN,
|
||||
};
|
||||
|
||||
enum at91_soc_subtype {
|
||||
/* RM9200 */
|
||||
AT91_SOC_RM9200_BGA, AT91_SOC_RM9200_PQFP,
|
||||
|
||||
/* SAM9260 */
|
||||
AT91_SOC_SAM9XE,
|
||||
|
||||
/* SAM9G45 */
|
||||
AT91_SOC_SAM9G45ES, AT91_SOC_SAM9M10, AT91_SOC_SAM9G46, AT91_SOC_SAM9M11,
|
||||
|
||||
/* SAM9X5 */
|
||||
AT91_SOC_SAM9G15, AT91_SOC_SAM9G35, AT91_SOC_SAM9X35,
|
||||
AT91_SOC_SAM9G25, AT91_SOC_SAM9X25,
|
||||
|
||||
/* SAMA5D3 */
|
||||
AT91_SOC_SAMA5D31, AT91_SOC_SAMA5D33, AT91_SOC_SAMA5D34,
|
||||
AT91_SOC_SAMA5D35, AT91_SOC_SAMA5D36,
|
||||
|
||||
/* SAMA5D4 */
|
||||
AT91_SOC_SAMA5D41, AT91_SOC_SAMA5D42, AT91_SOC_SAMA5D43,
|
||||
AT91_SOC_SAMA5D44,
|
||||
|
||||
/* No subtype for this SoC */
|
||||
AT91_SOC_SUBTYPE_NONE,
|
||||
|
||||
/* Unknown subtype */
|
||||
AT91_SOC_SUBTYPE_UNKNOWN,
|
||||
};
|
||||
|
||||
struct at91_socinfo {
|
||||
unsigned int type, subtype;
|
||||
unsigned int cidr, exid;
|
||||
};
|
||||
|
||||
extern struct at91_socinfo at91_soc_initdata;
|
||||
const char *at91_get_soc_type(struct at91_socinfo *c);
|
||||
const char *at91_get_soc_subtype(struct at91_socinfo *c);
|
||||
|
||||
static inline int at91_soc_is_detected(void)
|
||||
{
|
||||
return at91_soc_initdata.type != AT91_SOC_UNKNOWN;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SOC_AT91RM9200
|
||||
#define cpu_is_at91rm9200() (at91_soc_initdata.type == AT91_SOC_RM9200)
|
||||
#define cpu_is_at91rm9200_bga() (at91_soc_initdata.subtype == AT91_SOC_RM9200_BGA)
|
||||
#define cpu_is_at91rm9200_pqfp() (at91_soc_initdata.subtype == AT91_SOC_RM9200_PQFP)
|
||||
#else
|
||||
#define cpu_is_at91rm9200() (0)
|
||||
#define cpu_is_at91rm9200_bga() (0)
|
||||
#define cpu_is_at91rm9200_pqfp() (0)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SOC_AT91SAM9
|
||||
#define cpu_is_at91sam9xe() (at91_soc_initdata.subtype == AT91_SOC_SAM9XE)
|
||||
#define cpu_is_at91sam9260() (at91_soc_initdata.type == AT91_SOC_SAM9260)
|
||||
#define cpu_is_at91sam9g20() (at91_soc_initdata.type == AT91_SOC_SAM9G20)
|
||||
#define cpu_is_at91sam9261() (at91_soc_initdata.type == AT91_SOC_SAM9261)
|
||||
#define cpu_is_at91sam9g10() (at91_soc_initdata.type == AT91_SOC_SAM9G10)
|
||||
#define cpu_is_at91sam9263() (at91_soc_initdata.type == AT91_SOC_SAM9263)
|
||||
#define cpu_is_at91sam9rl() (at91_soc_initdata.type == AT91_SOC_SAM9RL)
|
||||
#define cpu_is_at91sam9g45() (at91_soc_initdata.type == AT91_SOC_SAM9G45)
|
||||
#define cpu_is_at91sam9g45es() (at91_soc_initdata.subtype == AT91_SOC_SAM9G45ES)
|
||||
#define cpu_is_at91sam9m10() (at91_soc_initdata.subtype == AT91_SOC_SAM9M10)
|
||||
#define cpu_is_at91sam9g46() (at91_soc_initdata.subtype == AT91_SOC_SAM9G46)
|
||||
#define cpu_is_at91sam9m11() (at91_soc_initdata.subtype == AT91_SOC_SAM9M11)
|
||||
#define cpu_is_at91sam9x5() (at91_soc_initdata.type == AT91_SOC_SAM9X5)
|
||||
#define cpu_is_at91sam9g15() (at91_soc_initdata.subtype == AT91_SOC_SAM9G15)
|
||||
#define cpu_is_at91sam9g35() (at91_soc_initdata.subtype == AT91_SOC_SAM9G35)
|
||||
#define cpu_is_at91sam9x35() (at91_soc_initdata.subtype == AT91_SOC_SAM9X35)
|
||||
#define cpu_is_at91sam9g25() (at91_soc_initdata.subtype == AT91_SOC_SAM9G25)
|
||||
#define cpu_is_at91sam9x25() (at91_soc_initdata.subtype == AT91_SOC_SAM9X25)
|
||||
#define cpu_is_at91sam9n12() (at91_soc_initdata.type == AT91_SOC_SAM9N12)
|
||||
#else
|
||||
#define cpu_is_at91sam9xe() (0)
|
||||
#define cpu_is_at91sam9260() (0)
|
||||
#define cpu_is_at91sam9g20() (0)
|
||||
#define cpu_is_at91sam9261() (0)
|
||||
#define cpu_is_at91sam9g10() (0)
|
||||
#define cpu_is_at91sam9263() (0)
|
||||
#define cpu_is_at91sam9rl() (0)
|
||||
#define cpu_is_at91sam9g45() (0)
|
||||
#define cpu_is_at91sam9g45es() (0)
|
||||
#define cpu_is_at91sam9m10() (0)
|
||||
#define cpu_is_at91sam9g46() (0)
|
||||
#define cpu_is_at91sam9m11() (0)
|
||||
#define cpu_is_at91sam9x5() (0)
|
||||
#define cpu_is_at91sam9g15() (0)
|
||||
#define cpu_is_at91sam9g35() (0)
|
||||
#define cpu_is_at91sam9x35() (0)
|
||||
#define cpu_is_at91sam9g25() (0)
|
||||
#define cpu_is_at91sam9x25() (0)
|
||||
#define cpu_is_at91sam9n12() (0)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SOC_SAMA5D3
|
||||
#define cpu_is_sama5d3() (at91_soc_initdata.type == AT91_SOC_SAMA5D3)
|
||||
#else
|
||||
#define cpu_is_sama5d3() (0)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SOC_SAMA5D4
|
||||
#define cpu_is_sama5d4() (at91_soc_initdata.type == AT91_SOC_SAMA5D4)
|
||||
#else
|
||||
#define cpu_is_sama5d4() (0)
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Since this is ARM, we will never run on any AVR32 CPU. But these
|
||||
* definitions may reduce clutter in common drivers.
|
||||
*/
|
||||
#define cpu_is_at32ap7000() (0)
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
#endif /* __MACH_CPU_H__ */
|
||||
@ -1,134 +0,0 @@
|
||||
/*
|
||||
* arch/arm/mach-at91/include/mach/hardware.h
|
||||
*
|
||||
* Copyright (C) 2003 SAN People
|
||||
* Copyright (C) 2003 ATMEL
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_HARDWARE_H
|
||||
#define __ASM_ARCH_HARDWARE_H
|
||||
|
||||
#include <asm/sizes.h>
|
||||
|
||||
/* DBGU base */
|
||||
/* rm9200, 9260/9g20, 9261/9g10, 9rl */
|
||||
#define AT91_BASE_DBGU0 0xfffff200
|
||||
/* 9263, 9g45, sama5d3 */
|
||||
#define AT91_BASE_DBGU1 0xffffee00
|
||||
/* sama5d4 */
|
||||
#define AT91_BASE_DBGU2 0xfc069000
|
||||
|
||||
#include <mach/at91rm9200.h>
|
||||
#include <mach/at91sam9260.h>
|
||||
#include <mach/at91sam9261.h>
|
||||
#include <mach/at91sam9263.h>
|
||||
#include <mach/at91sam9rl.h>
|
||||
#include <mach/at91sam9g45.h>
|
||||
#include <mach/at91sam9x5.h>
|
||||
#include <mach/at91sam9n12.h>
|
||||
#include <mach/sama5d3.h>
|
||||
#include <mach/sama5d4.h>
|
||||
|
||||
/*
|
||||
* On all at91 except rm9200 and x40 have the System Controller starts
|
||||
* at address 0xffffc000 and has a size of 16KiB.
|
||||
*
|
||||
* On rm9200 it's start at 0xfffe4000 of 111KiB with non reserved data starting
|
||||
* at 0xfffff000
|
||||
*
|
||||
* Removes the individual definitions of AT91_BASE_SYS and
|
||||
* replaces them with a common version at base 0xfffffc000 and size 16KiB
|
||||
* and map the same memory space
|
||||
*/
|
||||
#define AT91_BASE_SYS 0xffffc000
|
||||
|
||||
/*
|
||||
* On sama5d4 there is no system controller, we map some needed peripherals
|
||||
*/
|
||||
#define AT91_ALT_BASE_SYS 0xfc069000
|
||||
|
||||
/*
|
||||
* On all at91 have the Advanced Interrupt Controller starts at address
|
||||
* 0xfffff000 and the Power Management Controller starts at 0xfffffc00
|
||||
*/
|
||||
#define AT91_AIC 0xfffff000
|
||||
#define AT91_PMC 0xfffffc00
|
||||
|
||||
/*
|
||||
* Peripheral identifiers/interrupts.
|
||||
*/
|
||||
#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
|
||||
#define AT91_ID_SYS 1 /* System Peripherals */
|
||||
|
||||
#ifdef CONFIG_MMU
|
||||
/*
|
||||
* Remap the peripherals from address 0xFFF78000 .. 0xFFFFFFFF
|
||||
* to 0xFEF78000 .. 0xFF000000. (544Kb)
|
||||
*/
|
||||
#define AT91_IO_PHYS_BASE 0xFFF78000
|
||||
#define AT91_IO_VIRT_BASE IOMEM(0xFF000000 - AT91_IO_SIZE)
|
||||
|
||||
/*
|
||||
* On sama5d4, remap the peripherals from address 0xFC069000 .. 0xFC06F000
|
||||
* to 0xFB069000 .. 0xFB06F000. (24Kb)
|
||||
*/
|
||||
#define AT91_ALT_IO_PHYS_BASE AT91_ALT_BASE_SYS
|
||||
#define AT91_ALT_IO_VIRT_BASE IOMEM(0xFB069000)
|
||||
#else
|
||||
/*
|
||||
* Identity mapping for the non MMU case.
|
||||
*/
|
||||
#define AT91_IO_PHYS_BASE AT91_BASE_SYS
|
||||
#define AT91_IO_VIRT_BASE IOMEM(AT91_IO_PHYS_BASE)
|
||||
|
||||
#define AT91_ALT_IO_PHYS_BASE AT91_ALT_BASE_SYS
|
||||
#define AT91_ALT_IO_VIRT_BASE IOMEM(AT91_ALT_BASE_SYS)
|
||||
#endif
|
||||
|
||||
#define AT91_IO_SIZE (0xFFFFFFFF - AT91_IO_PHYS_BASE + 1)
|
||||
|
||||
/* Convert a physical IO address to virtual IO address */
|
||||
#define AT91_IO_P2V(x) ((x) - AT91_IO_PHYS_BASE + AT91_IO_VIRT_BASE)
|
||||
#define AT91_ALT_IO_P2V(x) ((x) - AT91_ALT_IO_PHYS_BASE + AT91_ALT_IO_VIRT_BASE)
|
||||
|
||||
/*
|
||||
* Virtual to Physical Address mapping for IO devices.
|
||||
*/
|
||||
#define AT91_VA_BASE_SYS AT91_IO_P2V(AT91_BASE_SYS)
|
||||
#define AT91_ALT_VA_BASE_SYS AT91_ALT_IO_P2V(AT91_ALT_BASE_SYS)
|
||||
|
||||
/* Internal SRAM is mapped below the IO devices */
|
||||
#define AT91_SRAM_MAX SZ_1M
|
||||
#define AT91_VIRT_BASE (AT91_IO_VIRT_BASE - AT91_SRAM_MAX)
|
||||
|
||||
/* External Memory Map */
|
||||
#define AT91_CHIPSELECT_0 0x10000000
|
||||
#define AT91_CHIPSELECT_1 0x20000000
|
||||
#define AT91_CHIPSELECT_2 0x30000000
|
||||
#define AT91_CHIPSELECT_3 0x40000000
|
||||
#define AT91_CHIPSELECT_4 0x50000000
|
||||
#define AT91_CHIPSELECT_5 0x60000000
|
||||
#define AT91_CHIPSELECT_6 0x70000000
|
||||
#define AT91_CHIPSELECT_7 0x80000000
|
||||
|
||||
/* Clocks */
|
||||
#define AT91_SLOW_CLOCK 32768 /* slow clock */
|
||||
|
||||
/*
|
||||
* FIXME: this is needed to communicate between the pinctrl driver and
|
||||
* the PM implementation in the machine. Possibly part of the PM
|
||||
* implementation should be moved down into the pinctrl driver and get
|
||||
* called as part of the generic suspend/resume path.
|
||||
*/
|
||||
#ifndef __ASSEMBLY__
|
||||
extern void at91_pinctrl_gpio_suspend(void);
|
||||
extern void at91_pinctrl_gpio_resume(void);
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@ -1,27 +0,0 @@
|
||||
/*
|
||||
* arch/arm/mach-at91/include/mach/io.h
|
||||
*
|
||||
* Copyright (C) 2003 SAN People
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_IO_H
|
||||
#define __ASM_ARCH_IO_H
|
||||
|
||||
#define IO_SPACE_LIMIT 0xFFFFFFFF
|
||||
#define __io(a) __typesafe_io(a)
|
||||
|
||||
#endif
|
||||
@ -1,86 +0,0 @@
|
||||
/*
|
||||
* Chip-specific header file for the SAMA5D3 family
|
||||
*
|
||||
* Copyright (C) 2013 Atmel,
|
||||
* 2013 Ludovic Desroches <ludovic.desroches@atmel.com>
|
||||
*
|
||||
* Common definitions.
|
||||
* Based on SAMA5D3 datasheet.
|
||||
*
|
||||
* Licensed under GPLv2 or later.
|
||||
*/
|
||||
|
||||
#ifndef SAMA5D3_H
|
||||
#define SAMA5D3_H
|
||||
|
||||
/*
|
||||
* Peripheral identifiers/interrupts.
|
||||
*/
|
||||
#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
|
||||
#define AT91_ID_SYS 1 /* System Peripherals */
|
||||
#define SAMA5D3_ID_DBGU 2 /* debug Unit (usually no special interrupt line) */
|
||||
#define AT91_ID_PIT 3 /* PIT */
|
||||
#define SAMA5D3_ID_WDT 4 /* Watchdog Timer Interrupt */
|
||||
#define SAMA5D3_ID_HSMC 5 /* Static Memory Controller */
|
||||
#define SAMA5D3_ID_PIOA 6 /* PIOA */
|
||||
#define SAMA5D3_ID_PIOB 7 /* PIOB */
|
||||
#define SAMA5D3_ID_PIOC 8 /* PIOC */
|
||||
#define SAMA5D3_ID_PIOD 9 /* PIOD */
|
||||
#define SAMA5D3_ID_PIOE 10 /* PIOE */
|
||||
#define SAMA5D3_ID_SMD 11 /* SMD Soft Modem */
|
||||
#define SAMA5D3_ID_USART0 12 /* USART0 */
|
||||
#define SAMA5D3_ID_USART1 13 /* USART1 */
|
||||
#define SAMA5D3_ID_USART2 14 /* USART2 */
|
||||
#define SAMA5D3_ID_USART3 15 /* USART3 */
|
||||
#define SAMA5D3_ID_UART0 16 /* UART 0 */
|
||||
#define SAMA5D3_ID_UART1 17 /* UART 1 */
|
||||
#define SAMA5D3_ID_TWI0 18 /* Two-Wire Interface 0 */
|
||||
#define SAMA5D3_ID_TWI1 19 /* Two-Wire Interface 1 */
|
||||
#define SAMA5D3_ID_TWI2 20 /* Two-Wire Interface 2 */
|
||||
#define SAMA5D3_ID_HSMCI0 21 /* MCI */
|
||||
#define SAMA5D3_ID_HSMCI1 22 /* MCI */
|
||||
#define SAMA5D3_ID_HSMCI2 23 /* MCI */
|
||||
#define SAMA5D3_ID_SPI0 24 /* Serial Peripheral Interface 0 */
|
||||
#define SAMA5D3_ID_SPI1 25 /* Serial Peripheral Interface 1 */
|
||||
#define SAMA5D3_ID_TC0 26 /* Timer Counter 0 */
|
||||
#define SAMA5D3_ID_TC1 27 /* Timer Counter 2 */
|
||||
#define SAMA5D3_ID_PWM 28 /* Pulse Width Modulation Controller */
|
||||
#define SAMA5D3_ID_ADC 29 /* Touch Screen ADC Controller */
|
||||
#define SAMA5D3_ID_DMA0 30 /* DMA Controller 0 */
|
||||
#define SAMA5D3_ID_DMA1 31 /* DMA Controller 1 */
|
||||
#define SAMA5D3_ID_UHPHS 32 /* USB Host High Speed */
|
||||
#define SAMA5D3_ID_UDPHS 33 /* USB Device High Speed */
|
||||
#define SAMA5D3_ID_GMAC 34 /* Gigabit Ethernet MAC */
|
||||
#define SAMA5D3_ID_EMAC 35 /* Ethernet MAC */
|
||||
#define SAMA5D3_ID_LCDC 36 /* LCD Controller */
|
||||
#define SAMA5D3_ID_ISI 37 /* Image Sensor Interface */
|
||||
#define SAMA5D3_ID_SSC0 38 /* Synchronous Serial Controller 0 */
|
||||
#define SAMA5D3_ID_SSC1 39 /* Synchronous Serial Controller 1 */
|
||||
#define SAMA5D3_ID_CAN0 40 /* CAN Controller 0 */
|
||||
#define SAMA5D3_ID_CAN1 41 /* CAN Controller 1 */
|
||||
#define SAMA5D3_ID_SHA 42 /* Secure Hash Algorithm */
|
||||
#define SAMA5D3_ID_AES 43 /* Advanced Encryption Standard */
|
||||
#define SAMA5D3_ID_TDES 44 /* Triple Data Encryption Standard */
|
||||
#define SAMA5D3_ID_TRNG 45 /* True Random Generator Number */
|
||||
#define SAMA5D3_ID_IRQ0 47 /* Advanced Interrupt Controller (IRQ0) */
|
||||
|
||||
/*
|
||||
* User Peripheral physical base addresses.
|
||||
*/
|
||||
#define SAMA5D3_BASE_USART0 0xf001c000
|
||||
#define SAMA5D3_BASE_USART1 0xf0020000
|
||||
#define SAMA5D3_BASE_USART2 0xf8020000
|
||||
#define SAMA5D3_BASE_USART3 0xf8024000
|
||||
|
||||
/*
|
||||
* System Peripherals
|
||||
*/
|
||||
#define SAMA5D3_BASE_RTC 0xfffffeb0
|
||||
|
||||
/*
|
||||
* Internal Memory
|
||||
*/
|
||||
#define SAMA5D3_SRAM_BASE 0x00300000 /* Internal SRAM base address */
|
||||
#define SAMA5D3_SRAM_SIZE (128 * SZ_1K) /* Internal SRAM size (128Kb) */
|
||||
|
||||
#endif
|
||||
@ -1,33 +0,0 @@
|
||||
/*
|
||||
* Chip-specific header file for the SAMA5D4 family
|
||||
*
|
||||
* Copyright (C) 2013 Atmel Corporation,
|
||||
* Nicolas Ferre <nicolas.ferre@atmel.com>
|
||||
*
|
||||
* Common definitions.
|
||||
* Based on SAMA5D4 datasheet.
|
||||
*
|
||||
* Licensed under GPLv2 or later.
|
||||
*/
|
||||
|
||||
#ifndef SAMA5D4_H
|
||||
#define SAMA5D4_H
|
||||
|
||||
/*
|
||||
* User Peripheral physical base addresses.
|
||||
*/
|
||||
#define SAMA5D4_BASE_USART3 0xfc00c000 /* (USART3 non-secure) Base Address */
|
||||
#define SAMA5D4_BASE_PMC 0xf0018000 /* (PMC) Base Address */
|
||||
#define SAMA5D4_BASE_MPDDRC 0xf0010000 /* (MPDDRC) Base Address */
|
||||
#define SAMA5D4_BASE_PIOD 0xfc068000 /* (PIOD) Base Address */
|
||||
|
||||
/* Some other peripherals */
|
||||
#define SAMA5D4_BASE_SYS2 SAMA5D4_BASE_PIOD
|
||||
|
||||
/*
|
||||
* Internal Memory.
|
||||
*/
|
||||
#define SAMA5D4_NS_SRAM_BASE 0x00210000 /* Internal SRAM base address Non-Secure */
|
||||
#define SAMA5D4_NS_SRAM_SIZE (64 * SZ_1K) /* Internal SRAM size Non-Secure part (64Kb) */
|
||||
|
||||
#endif
|
||||
@ -1,218 +0,0 @@
|
||||
/*
|
||||
* arch/arm/mach-at91/include/mach/uncompress.h
|
||||
*
|
||||
* Copyright (C) 2003 SAN People
|
||||
* Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_UNCOMPRESS_H
|
||||
#define __ASM_ARCH_UNCOMPRESS_H
|
||||
|
||||
#include <linux/io.h>
|
||||
#include <linux/atmel_serial.h>
|
||||
#include <mach/hardware.h>
|
||||
|
||||
#include <mach/at91_dbgu.h>
|
||||
#include <mach/cpu.h>
|
||||
|
||||
void __iomem *at91_uart;
|
||||
|
||||
static const u32 uarts_rm9200[] = {
|
||||
AT91_BASE_DBGU0,
|
||||
AT91RM9200_BASE_US0,
|
||||
AT91RM9200_BASE_US1,
|
||||
AT91RM9200_BASE_US2,
|
||||
AT91RM9200_BASE_US3,
|
||||
0,
|
||||
};
|
||||
|
||||
static const u32 uarts_sam9260[] = {
|
||||
AT91_BASE_DBGU0,
|
||||
AT91SAM9260_BASE_US0,
|
||||
AT91SAM9260_BASE_US1,
|
||||
AT91SAM9260_BASE_US2,
|
||||
AT91SAM9260_BASE_US3,
|
||||
AT91SAM9260_BASE_US4,
|
||||
AT91SAM9260_BASE_US5,
|
||||
0,
|
||||
};
|
||||
|
||||
static const u32 uarts_sam9261[] = {
|
||||
AT91_BASE_DBGU0,
|
||||
AT91SAM9261_BASE_US0,
|
||||
AT91SAM9261_BASE_US1,
|
||||
AT91SAM9261_BASE_US2,
|
||||
0,
|
||||
};
|
||||
|
||||
static const u32 uarts_sam9263[] = {
|
||||
AT91_BASE_DBGU1,
|
||||
AT91SAM9263_BASE_US0,
|
||||
AT91SAM9263_BASE_US1,
|
||||
AT91SAM9263_BASE_US2,
|
||||
0,
|
||||
};
|
||||
|
||||
static const u32 uarts_sam9g45[] = {
|
||||
AT91_BASE_DBGU1,
|
||||
AT91SAM9G45_BASE_US0,
|
||||
AT91SAM9G45_BASE_US1,
|
||||
AT91SAM9G45_BASE_US2,
|
||||
AT91SAM9G45_BASE_US3,
|
||||
0,
|
||||
};
|
||||
|
||||
static const u32 uarts_sam9rl[] = {
|
||||
AT91_BASE_DBGU0,
|
||||
AT91SAM9RL_BASE_US0,
|
||||
AT91SAM9RL_BASE_US1,
|
||||
AT91SAM9RL_BASE_US2,
|
||||
AT91SAM9RL_BASE_US3,
|
||||
0,
|
||||
};
|
||||
|
||||
static const u32 uarts_sam9x5[] = {
|
||||
AT91_BASE_DBGU0,
|
||||
AT91SAM9X5_BASE_USART0,
|
||||
AT91SAM9X5_BASE_USART1,
|
||||
AT91SAM9X5_BASE_USART2,
|
||||
0,
|
||||
};
|
||||
|
||||
static const u32 uarts_sama5d3[] = {
|
||||
AT91_BASE_DBGU1,
|
||||
SAMA5D3_BASE_USART0,
|
||||
SAMA5D3_BASE_USART1,
|
||||
SAMA5D3_BASE_USART2,
|
||||
SAMA5D3_BASE_USART3,
|
||||
0,
|
||||
};
|
||||
|
||||
static const u32 uarts_sama5d4[] = {
|
||||
AT91_BASE_DBGU2,
|
||||
SAMA5D4_BASE_USART3,
|
||||
0,
|
||||
};
|
||||
|
||||
static inline const u32* decomp_soc_detect(void __iomem *dbgu_base)
|
||||
{
|
||||
u32 cidr, socid;
|
||||
|
||||
cidr = __raw_readl(dbgu_base + AT91_DBGU_CIDR);
|
||||
socid = cidr & ~AT91_CIDR_VERSION;
|
||||
|
||||
switch (socid) {
|
||||
case ARCH_ID_AT91RM9200:
|
||||
return uarts_rm9200;
|
||||
|
||||
case ARCH_ID_AT91SAM9G20:
|
||||
case ARCH_ID_AT91SAM9260:
|
||||
return uarts_sam9260;
|
||||
|
||||
case ARCH_ID_AT91SAM9261:
|
||||
return uarts_sam9261;
|
||||
|
||||
case ARCH_ID_AT91SAM9263:
|
||||
return uarts_sam9263;
|
||||
|
||||
case ARCH_ID_AT91SAM9G45:
|
||||
return uarts_sam9g45;
|
||||
|
||||
case ARCH_ID_AT91SAM9RL64:
|
||||
return uarts_sam9rl;
|
||||
|
||||
case ARCH_ID_AT91SAM9N12:
|
||||
case ARCH_ID_AT91SAM9X5:
|
||||
return uarts_sam9x5;
|
||||
|
||||
case ARCH_ID_SAMA5:
|
||||
cidr = __raw_readl(dbgu_base + AT91_DBGU_EXID);
|
||||
if (cidr & ARCH_EXID_SAMA5D3)
|
||||
return uarts_sama5d3;
|
||||
else if (cidr & ARCH_EXID_SAMA5D4)
|
||||
return uarts_sama5d4;
|
||||
|
||||
break;
|
||||
}
|
||||
|
||||
/* at91sam9g10 */
|
||||
if ((cidr & ~AT91_CIDR_EXT) == ARCH_ID_AT91SAM9G10) {
|
||||
return uarts_sam9261;
|
||||
}
|
||||
/* at91sam9xe */
|
||||
else if ((cidr & AT91_CIDR_ARCH) == ARCH_FAMILY_AT91SAM9XE) {
|
||||
return uarts_sam9260;
|
||||
}
|
||||
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static inline void arch_decomp_setup(void)
|
||||
{
|
||||
int i = 0;
|
||||
const u32* usarts;
|
||||
|
||||
usarts = decomp_soc_detect((void __iomem *)AT91_BASE_DBGU0);
|
||||
if (!usarts)
|
||||
usarts = decomp_soc_detect((void __iomem *)AT91_BASE_DBGU1);
|
||||
if (!usarts)
|
||||
usarts = decomp_soc_detect((void __iomem *)AT91_BASE_DBGU2);
|
||||
if (!usarts) {
|
||||
at91_uart = NULL;
|
||||
return;
|
||||
}
|
||||
|
||||
do {
|
||||
/* physical address */
|
||||
at91_uart = (void __iomem *)usarts[i];
|
||||
|
||||
if (__raw_readl(at91_uart + ATMEL_US_BRGR))
|
||||
return;
|
||||
i++;
|
||||
} while (usarts[i]);
|
||||
|
||||
at91_uart = NULL;
|
||||
}
|
||||
|
||||
/*
|
||||
* The following code assumes the serial port has already been
|
||||
* initialized by the bootloader. If you didn't setup a port in
|
||||
* your bootloader then nothing will appear (which might be desired).
|
||||
*
|
||||
* This does not append a newline
|
||||
*/
|
||||
static void putc(int c)
|
||||
{
|
||||
if (!at91_uart)
|
||||
return;
|
||||
|
||||
while (!(__raw_readl(at91_uart + ATMEL_US_CSR) & ATMEL_US_TXRDY))
|
||||
barrier();
|
||||
__raw_writel(c, at91_uart + ATMEL_US_THR);
|
||||
}
|
||||
|
||||
static inline void flush(void)
|
||||
{
|
||||
if (!at91_uart)
|
||||
return;
|
||||
|
||||
/* wait for transmission to complete */
|
||||
while (!(__raw_readl(at91_uart + ATMEL_US_CSR) & ATMEL_US_TXEMPTY))
|
||||
barrier();
|
||||
}
|
||||
|
||||
#endif
|
||||
@ -29,19 +29,26 @@
|
||||
#include <linux/atomic.h>
|
||||
#include <asm/mach/time.h>
|
||||
#include <asm/mach/irq.h>
|
||||
|
||||
#include <mach/cpu.h>
|
||||
#include <mach/hardware.h>
|
||||
#include <asm/fncpy.h>
|
||||
#include <asm/cacheflush.h>
|
||||
|
||||
#include "generic.h"
|
||||
#include "pm.h"
|
||||
|
||||
/*
|
||||
* FIXME: this is needed to communicate between the pinctrl driver and
|
||||
* the PM implementation in the machine. Possibly part of the PM
|
||||
* implementation should be moved down into the pinctrl driver and get
|
||||
* called as part of the generic suspend/resume path.
|
||||
*/
|
||||
extern void at91_pinctrl_gpio_suspend(void);
|
||||
extern void at91_pinctrl_gpio_resume(void);
|
||||
|
||||
static struct {
|
||||
unsigned long uhp_udp_mask;
|
||||
int memctrl;
|
||||
} at91_pm_data;
|
||||
|
||||
static void (*at91_pm_standby)(void);
|
||||
void __iomem *at91_ramc_base[2];
|
||||
|
||||
static int at91_pm_valid_state(suspend_state_t state)
|
||||
@ -119,76 +126,67 @@ int at91_suspend_entering_slow_clock(void)
|
||||
}
|
||||
EXPORT_SYMBOL(at91_suspend_entering_slow_clock);
|
||||
|
||||
|
||||
static void (*slow_clock)(void __iomem *pmc, void __iomem *ramc0,
|
||||
static void (*at91_suspend_sram_fn)(void __iomem *pmc, void __iomem *ramc0,
|
||||
void __iomem *ramc1, int memctrl);
|
||||
|
||||
#ifdef CONFIG_AT91_SLOW_CLOCK
|
||||
extern void at91_slow_clock(void __iomem *pmc, void __iomem *ramc0,
|
||||
extern void at91_pm_suspend_in_sram(void __iomem *pmc, void __iomem *ramc0,
|
||||
void __iomem *ramc1, int memctrl);
|
||||
extern u32 at91_slow_clock_sz;
|
||||
#endif
|
||||
extern u32 at91_pm_suspend_in_sram_sz;
|
||||
|
||||
static void at91_pm_suspend(suspend_state_t state)
|
||||
{
|
||||
unsigned int pm_data = at91_pm_data.memctrl;
|
||||
|
||||
pm_data |= (state == PM_SUSPEND_MEM) ?
|
||||
AT91_PM_MODE(AT91_PM_SLOW_CLOCK) : 0;
|
||||
|
||||
flush_cache_all();
|
||||
outer_disable();
|
||||
|
||||
at91_suspend_sram_fn(at91_pmc_base, at91_ramc_base[0],
|
||||
at91_ramc_base[1], pm_data);
|
||||
|
||||
outer_resume();
|
||||
}
|
||||
|
||||
static int at91_pm_enter(suspend_state_t state)
|
||||
{
|
||||
at91_pinctrl_gpio_suspend();
|
||||
|
||||
switch (state) {
|
||||
/*
|
||||
* Suspend-to-RAM is like STANDBY plus slow clock mode, so
|
||||
* drivers must suspend more deeply, the master clock switches
|
||||
* to the clk32k and turns off the main oscillator
|
||||
*/
|
||||
case PM_SUSPEND_MEM:
|
||||
/*
|
||||
* Suspend-to-RAM is like STANDBY plus slow clock mode, so
|
||||
* drivers must suspend more deeply: only the master clock
|
||||
* controller may be using the main oscillator.
|
||||
* Ensure that clocks are in a valid state.
|
||||
*/
|
||||
case PM_SUSPEND_MEM:
|
||||
/*
|
||||
* Ensure that clocks are in a valid state.
|
||||
*/
|
||||
if (!at91_pm_verify_clocks())
|
||||
goto error;
|
||||
|
||||
/*
|
||||
* Enter slow clock mode by switching over to clk32k and
|
||||
* turning off the main oscillator; reverse on wakeup.
|
||||
*/
|
||||
if (slow_clock) {
|
||||
#ifdef CONFIG_AT91_SLOW_CLOCK
|
||||
/* copy slow_clock handler to SRAM, and call it */
|
||||
memcpy(slow_clock, at91_slow_clock, at91_slow_clock_sz);
|
||||
#endif
|
||||
slow_clock(at91_pmc_base, at91_ramc_base[0],
|
||||
at91_ramc_base[1],
|
||||
at91_pm_data.memctrl);
|
||||
break;
|
||||
} else {
|
||||
pr_info("AT91: PM - no slow clock mode enabled ...\n");
|
||||
/* FALLTHROUGH leaving master clock alone */
|
||||
}
|
||||
|
||||
/*
|
||||
* STANDBY mode has *all* drivers suspended; ignores irqs not
|
||||
* marked as 'wakeup' event sources; and reduces DRAM power.
|
||||
* But otherwise it's identical to PM_SUSPEND_ON: cpu idle, and
|
||||
* nothing fancy done with main or cpu clocks.
|
||||
*/
|
||||
case PM_SUSPEND_STANDBY:
|
||||
/*
|
||||
* NOTE: the Wait-for-Interrupt instruction needs to be
|
||||
* in icache so no SDRAM accesses are needed until the
|
||||
* wakeup IRQ occurs and self-refresh is terminated.
|
||||
* For ARM 926 based chips, this requirement is weaker
|
||||
* as at91sam9 can access a RAM in self-refresh mode.
|
||||
*/
|
||||
if (at91_pm_standby)
|
||||
at91_pm_standby();
|
||||
break;
|
||||
|
||||
case PM_SUSPEND_ON:
|
||||
cpu_do_idle();
|
||||
break;
|
||||
|
||||
default:
|
||||
pr_debug("AT91: PM - bogus suspend state %d\n", state);
|
||||
if (!at91_pm_verify_clocks())
|
||||
goto error;
|
||||
|
||||
at91_pm_suspend(state);
|
||||
|
||||
break;
|
||||
|
||||
/*
|
||||
* STANDBY mode has *all* drivers suspended; ignores irqs not
|
||||
* marked as 'wakeup' event sources; and reduces DRAM power.
|
||||
* But otherwise it's identical to PM_SUSPEND_ON: cpu idle, and
|
||||
* nothing fancy done with main or cpu clocks.
|
||||
*/
|
||||
case PM_SUSPEND_STANDBY:
|
||||
at91_pm_suspend(state);
|
||||
break;
|
||||
|
||||
case PM_SUSPEND_ON:
|
||||
cpu_do_idle();
|
||||
break;
|
||||
|
||||
default:
|
||||
pr_debug("AT91: PM - bogus suspend state %d\n", state);
|
||||
goto error;
|
||||
}
|
||||
|
||||
error:
|
||||
@ -218,12 +216,10 @@ static struct platform_device at91_cpuidle_device = {
|
||||
.name = "cpuidle-at91",
|
||||
};
|
||||
|
||||
void at91_pm_set_standby(void (*at91_standby)(void))
|
||||
static void at91_pm_set_standby(void (*at91_standby)(void))
|
||||
{
|
||||
if (at91_standby) {
|
||||
if (at91_standby)
|
||||
at91_cpuidle_device.dev.platform_data = at91_standby;
|
||||
at91_pm_standby = at91_standby;
|
||||
}
|
||||
}
|
||||
|
||||
static const struct of_device_id ramc_ids[] __initconst = {
|
||||
@ -263,60 +259,63 @@ static __init void at91_dt_ramc(void)
|
||||
at91_pm_set_standby(standby);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_AT91_SLOW_CLOCK
|
||||
static void __init at91_pm_sram_init(void)
|
||||
{
|
||||
struct gen_pool *sram_pool;
|
||||
phys_addr_t sram_pbase;
|
||||
unsigned long sram_base;
|
||||
struct device_node *node;
|
||||
struct platform_device *pdev;
|
||||
struct platform_device *pdev = NULL;
|
||||
|
||||
node = of_find_compatible_node(NULL, NULL, "mmio-sram");
|
||||
if (!node) {
|
||||
pr_warn("%s: failed to find sram node!\n", __func__);
|
||||
return;
|
||||
for_each_compatible_node(node, NULL, "mmio-sram") {
|
||||
pdev = of_find_device_by_node(node);
|
||||
if (pdev) {
|
||||
of_node_put(node);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
pdev = of_find_device_by_node(node);
|
||||
if (!pdev) {
|
||||
pr_warn("%s: failed to find sram device!\n", __func__);
|
||||
goto put_node;
|
||||
return;
|
||||
}
|
||||
|
||||
sram_pool = dev_get_gen_pool(&pdev->dev);
|
||||
if (!sram_pool) {
|
||||
pr_warn("%s: sram pool unavailable!\n", __func__);
|
||||
goto put_node;
|
||||
return;
|
||||
}
|
||||
|
||||
sram_base = gen_pool_alloc(sram_pool, at91_slow_clock_sz);
|
||||
sram_base = gen_pool_alloc(sram_pool, at91_pm_suspend_in_sram_sz);
|
||||
if (!sram_base) {
|
||||
pr_warn("%s: unable to alloc ocram!\n", __func__);
|
||||
goto put_node;
|
||||
pr_warn("%s: unable to alloc sram!\n", __func__);
|
||||
return;
|
||||
}
|
||||
|
||||
sram_pbase = gen_pool_virt_to_phys(sram_pool, sram_base);
|
||||
slow_clock = __arm_ioremap_exec(sram_pbase, at91_slow_clock_sz, false);
|
||||
at91_suspend_sram_fn = __arm_ioremap_exec(sram_pbase,
|
||||
at91_pm_suspend_in_sram_sz, false);
|
||||
if (!at91_suspend_sram_fn) {
|
||||
pr_warn("SRAM: Could not map\n");
|
||||
return;
|
||||
}
|
||||
|
||||
put_node:
|
||||
of_node_put(node);
|
||||
/* Copy the pm suspend handler to SRAM */
|
||||
at91_suspend_sram_fn = fncpy(at91_suspend_sram_fn,
|
||||
&at91_pm_suspend_in_sram, at91_pm_suspend_in_sram_sz);
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
static void __init at91_pm_init(void)
|
||||
{
|
||||
#ifdef CONFIG_AT91_SLOW_CLOCK
|
||||
at91_pm_sram_init();
|
||||
#endif
|
||||
|
||||
pr_info("AT91: Power Management%s\n", (slow_clock ? " (with slow clock mode)" : ""));
|
||||
|
||||
if (at91_cpuidle_device.dev.platform_data)
|
||||
platform_device_register(&at91_cpuidle_device);
|
||||
|
||||
suspend_set_ops(&at91_pm_ops);
|
||||
if (at91_suspend_sram_fn)
|
||||
suspend_set_ops(&at91_pm_ops);
|
||||
else
|
||||
pr_info("AT91: PM not supported, due to no SRAM allocated\n");
|
||||
}
|
||||
|
||||
void __init at91rm9200_pm_init(void)
|
||||
|
||||
@ -15,11 +15,13 @@
|
||||
|
||||
#include <mach/at91_ramc.h>
|
||||
|
||||
#ifdef CONFIG_PM
|
||||
extern void at91_pm_set_standby(void (*at91_standby)(void));
|
||||
#else
|
||||
static inline void at91_pm_set_standby(void (*at91_standby)(void)) { }
|
||||
#endif
|
||||
#define AT91_PM_MEMTYPE_MASK 0x0f
|
||||
|
||||
#define AT91_PM_MODE_OFFSET 4
|
||||
#define AT91_PM_MODE_MASK 0x01
|
||||
#define AT91_PM_MODE(x) (((x) & AT91_PM_MODE_MASK) << AT91_PM_MODE_OFFSET)
|
||||
|
||||
#define AT91_PM_SLOW_CLOCK 0x01
|
||||
|
||||
/*
|
||||
* The AT91RM9200 goes into self-refresh mode with this command, and will
|
||||
@ -31,6 +33,7 @@ static inline void at91_pm_set_standby(void (*at91_standby)(void)) { }
|
||||
* still in self-refresh is "not recommended", but seems to work.
|
||||
*/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
static inline void at91rm9200_standby(void)
|
||||
{
|
||||
u32 lpr = at91_ramc_read(0, AT91RM9200_SDRAMC_LPR);
|
||||
@ -44,7 +47,7 @@ static inline void at91rm9200_standby(void)
|
||||
" mcr p15, 0, %0, c7, c0, 4\n\t"
|
||||
" str %5, [%1, %2]"
|
||||
:
|
||||
: "r" (0), "r" (AT91_BASE_SYS), "r" (AT91RM9200_SDRAMC_LPR),
|
||||
: "r" (0), "r" (at91_ramc_base[0]), "r" (AT91RM9200_SDRAMC_LPR),
|
||||
"r" (1), "r" (AT91RM9200_SDRAMC_SRR),
|
||||
"r" (lpr));
|
||||
}
|
||||
@ -112,3 +115,4 @@ static inline void at91sam9_sdram_standby(void)
|
||||
}
|
||||
|
||||
#endif
|
||||
#endif
|
||||
|
||||
@ -1,323 +0,0 @@
|
||||
/*
|
||||
* arch/arm/mach-at91/pm_slow_clock.S
|
||||
*
|
||||
* Copyright (C) 2006 Savin Zlobec
|
||||
*
|
||||
* AT91SAM9 support:
|
||||
* Copyright (C) 2007 Anti Sullin <anti.sullin@artecdesign.ee
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <linux/linkage.h>
|
||||
#include <linux/clk/at91_pmc.h>
|
||||
#include <mach/hardware.h>
|
||||
#include <mach/at91_ramc.h>
|
||||
|
||||
/*
|
||||
* When SLOWDOWN_MASTER_CLOCK is defined we will also slow down the Master
|
||||
* clock during suspend by adjusting its prescalar and divisor.
|
||||
* NOTE: This hasn't been shown to be stable on SAM9s; and on the RM9200 there
|
||||
* are errata regarding adjusting the prescalar and divisor.
|
||||
*/
|
||||
#undef SLOWDOWN_MASTER_CLOCK
|
||||
|
||||
#define MCKRDY_TIMEOUT 1000
|
||||
#define MOSCRDY_TIMEOUT 1000
|
||||
#define PLLALOCK_TIMEOUT 1000
|
||||
#define PLLBLOCK_TIMEOUT 1000
|
||||
|
||||
pmc .req r0
|
||||
sdramc .req r1
|
||||
ramc1 .req r2
|
||||
memctrl .req r3
|
||||
tmp1 .req r4
|
||||
tmp2 .req r5
|
||||
|
||||
/*
|
||||
* Wait until master clock is ready (after switching master clock source)
|
||||
*/
|
||||
.macro wait_mckrdy
|
||||
mov tmp2, #MCKRDY_TIMEOUT
|
||||
1: sub tmp2, tmp2, #1
|
||||
cmp tmp2, #0
|
||||
beq 2f
|
||||
ldr tmp1, [pmc, #AT91_PMC_SR]
|
||||
tst tmp1, #AT91_PMC_MCKRDY
|
||||
beq 1b
|
||||
2:
|
||||
.endm
|
||||
|
||||
/*
|
||||
* Wait until master oscillator has stabilized.
|
||||
*/
|
||||
.macro wait_moscrdy
|
||||
mov tmp2, #MOSCRDY_TIMEOUT
|
||||
1: sub tmp2, tmp2, #1
|
||||
cmp tmp2, #0
|
||||
beq 2f
|
||||
ldr tmp1, [pmc, #AT91_PMC_SR]
|
||||
tst tmp1, #AT91_PMC_MOSCS
|
||||
beq 1b
|
||||
2:
|
||||
.endm
|
||||
|
||||
/*
|
||||
* Wait until PLLA has locked.
|
||||
*/
|
||||
.macro wait_pllalock
|
||||
mov tmp2, #PLLALOCK_TIMEOUT
|
||||
1: sub tmp2, tmp2, #1
|
||||
cmp tmp2, #0
|
||||
beq 2f
|
||||
ldr tmp1, [pmc, #AT91_PMC_SR]
|
||||
tst tmp1, #AT91_PMC_LOCKA
|
||||
beq 1b
|
||||
2:
|
||||
.endm
|
||||
|
||||
/*
|
||||
* Wait until PLLB has locked.
|
||||
*/
|
||||
.macro wait_pllblock
|
||||
mov tmp2, #PLLBLOCK_TIMEOUT
|
||||
1: sub tmp2, tmp2, #1
|
||||
cmp tmp2, #0
|
||||
beq 2f
|
||||
ldr tmp1, [pmc, #AT91_PMC_SR]
|
||||
tst tmp1, #AT91_PMC_LOCKB
|
||||
beq 1b
|
||||
2:
|
||||
.endm
|
||||
|
||||
.text
|
||||
|
||||
/* void at91_slow_clock(void __iomem *pmc, void __iomem *sdramc,
|
||||
* void __iomem *ramc1, int memctrl)
|
||||
*/
|
||||
ENTRY(at91_slow_clock)
|
||||
/* Save registers on stack */
|
||||
stmfd sp!, {r4 - r12, lr}
|
||||
|
||||
/*
|
||||
* Register usage:
|
||||
* R0 = Base address of AT91_PMC
|
||||
* R1 = Base address of RAM Controller (SDRAM, DDRSDR, or AT91_SYS)
|
||||
* R2 = Base address of second RAM Controller or 0 if not present
|
||||
* R3 = Memory controller
|
||||
* R4 = temporary register
|
||||
* R5 = temporary register
|
||||
*/
|
||||
|
||||
/* Drain write buffer */
|
||||
mov tmp1, #0
|
||||
mcr p15, 0, tmp1, c7, c10, 4
|
||||
|
||||
cmp memctrl, #AT91_MEMCTRL_MC
|
||||
bne ddr_sr_enable
|
||||
|
||||
/*
|
||||
* at91rm9200 Memory controller
|
||||
*/
|
||||
/* Put SDRAM in self-refresh mode */
|
||||
mov tmp1, #1
|
||||
str tmp1, [sdramc, #AT91RM9200_SDRAMC_SRR]
|
||||
b sdr_sr_done
|
||||
|
||||
/*
|
||||
* DDRSDR Memory controller
|
||||
*/
|
||||
ddr_sr_enable:
|
||||
cmp memctrl, #AT91_MEMCTRL_DDRSDR
|
||||
bne sdr_sr_enable
|
||||
|
||||
/* prepare for DDRAM self-refresh mode */
|
||||
ldr tmp1, [sdramc, #AT91_DDRSDRC_LPR]
|
||||
str tmp1, .saved_sam9_lpr
|
||||
bic tmp1, #AT91_DDRSDRC_LPCB
|
||||
orr tmp1, #AT91_DDRSDRC_LPCB_SELF_REFRESH
|
||||
|
||||
/* figure out if we use the second ram controller */
|
||||
cmp ramc1, #0
|
||||
ldrne tmp2, [ramc1, #AT91_DDRSDRC_LPR]
|
||||
strne tmp2, .saved_sam9_lpr1
|
||||
bicne tmp2, #AT91_DDRSDRC_LPCB
|
||||
orrne tmp2, #AT91_DDRSDRC_LPCB_SELF_REFRESH
|
||||
|
||||
/* Enable DDRAM self-refresh mode */
|
||||
str tmp1, [sdramc, #AT91_DDRSDRC_LPR]
|
||||
strne tmp2, [ramc1, #AT91_DDRSDRC_LPR]
|
||||
|
||||
b sdr_sr_done
|
||||
|
||||
/*
|
||||
* SDRAMC Memory controller
|
||||
*/
|
||||
sdr_sr_enable:
|
||||
/* Enable SDRAM self-refresh mode */
|
||||
ldr tmp1, [sdramc, #AT91_SDRAMC_LPR]
|
||||
str tmp1, .saved_sam9_lpr
|
||||
|
||||
bic tmp1, #AT91_SDRAMC_LPCB
|
||||
orr tmp1, #AT91_SDRAMC_LPCB_SELF_REFRESH
|
||||
str tmp1, [sdramc, #AT91_SDRAMC_LPR]
|
||||
|
||||
sdr_sr_done:
|
||||
/* Save Master clock setting */
|
||||
ldr tmp1, [pmc, #AT91_PMC_MCKR]
|
||||
str tmp1, .saved_mckr
|
||||
|
||||
/*
|
||||
* Set the Master clock source to slow clock
|
||||
*/
|
||||
bic tmp1, tmp1, #AT91_PMC_CSS
|
||||
str tmp1, [pmc, #AT91_PMC_MCKR]
|
||||
|
||||
wait_mckrdy
|
||||
|
||||
#ifdef SLOWDOWN_MASTER_CLOCK
|
||||
/*
|
||||
* Set the Master Clock PRES and MDIV fields.
|
||||
*
|
||||
* See AT91RM9200 errata #27 and #28 for details.
|
||||
*/
|
||||
mov tmp1, #0
|
||||
str tmp1, [pmc, #AT91_PMC_MCKR]
|
||||
|
||||
wait_mckrdy
|
||||
#endif
|
||||
|
||||
/* Save PLLA setting and disable it */
|
||||
ldr tmp1, [pmc, #AT91_CKGR_PLLAR]
|
||||
str tmp1, .saved_pllar
|
||||
|
||||
mov tmp1, #AT91_PMC_PLLCOUNT
|
||||
orr tmp1, tmp1, #(1 << 29) /* bit 29 always set */
|
||||
str tmp1, [pmc, #AT91_CKGR_PLLAR]
|
||||
|
||||
/* Save PLLB setting and disable it */
|
||||
ldr tmp1, [pmc, #AT91_CKGR_PLLBR]
|
||||
str tmp1, .saved_pllbr
|
||||
|
||||
mov tmp1, #AT91_PMC_PLLCOUNT
|
||||
str tmp1, [pmc, #AT91_CKGR_PLLBR]
|
||||
|
||||
/* Turn off the main oscillator */
|
||||
ldr tmp1, [pmc, #AT91_CKGR_MOR]
|
||||
bic tmp1, tmp1, #AT91_PMC_MOSCEN
|
||||
str tmp1, [pmc, #AT91_CKGR_MOR]
|
||||
|
||||
/* Wait for interrupt */
|
||||
mcr p15, 0, tmp1, c7, c0, 4
|
||||
|
||||
/* Turn on the main oscillator */
|
||||
ldr tmp1, [pmc, #AT91_CKGR_MOR]
|
||||
orr tmp1, tmp1, #AT91_PMC_MOSCEN
|
||||
str tmp1, [pmc, #AT91_CKGR_MOR]
|
||||
|
||||
wait_moscrdy
|
||||
|
||||
/* Restore PLLB setting */
|
||||
ldr tmp1, .saved_pllbr
|
||||
str tmp1, [pmc, #AT91_CKGR_PLLBR]
|
||||
|
||||
tst tmp1, #(AT91_PMC_MUL & 0xff0000)
|
||||
bne 1f
|
||||
tst tmp1, #(AT91_PMC_MUL & ~0xff0000)
|
||||
beq 2f
|
||||
1:
|
||||
wait_pllblock
|
||||
2:
|
||||
|
||||
/* Restore PLLA setting */
|
||||
ldr tmp1, .saved_pllar
|
||||
str tmp1, [pmc, #AT91_CKGR_PLLAR]
|
||||
|
||||
tst tmp1, #(AT91_PMC_MUL & 0xff0000)
|
||||
bne 3f
|
||||
tst tmp1, #(AT91_PMC_MUL & ~0xff0000)
|
||||
beq 4f
|
||||
3:
|
||||
wait_pllalock
|
||||
4:
|
||||
|
||||
#ifdef SLOWDOWN_MASTER_CLOCK
|
||||
/*
|
||||
* First set PRES if it was not 0,
|
||||
* than set CSS and MDIV fields.
|
||||
*
|
||||
* See AT91RM9200 errata #27 and #28 for details.
|
||||
*/
|
||||
ldr tmp1, .saved_mckr
|
||||
tst tmp1, #AT91_PMC_PRES
|
||||
beq 2f
|
||||
and tmp1, tmp1, #AT91_PMC_PRES
|
||||
str tmp1, [pmc, #AT91_PMC_MCKR]
|
||||
|
||||
wait_mckrdy
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Restore master clock setting
|
||||
*/
|
||||
2: ldr tmp1, .saved_mckr
|
||||
str tmp1, [pmc, #AT91_PMC_MCKR]
|
||||
|
||||
wait_mckrdy
|
||||
|
||||
/*
|
||||
* at91rm9200 Memory controller
|
||||
* Do nothing - self-refresh is automatically disabled.
|
||||
*/
|
||||
cmp memctrl, #AT91_MEMCTRL_MC
|
||||
beq ram_restored
|
||||
|
||||
/*
|
||||
* DDRSDR Memory controller
|
||||
*/
|
||||
cmp memctrl, #AT91_MEMCTRL_DDRSDR
|
||||
bne sdr_en_restore
|
||||
/* Restore LPR on AT91 with DDRAM */
|
||||
ldr tmp1, .saved_sam9_lpr
|
||||
str tmp1, [sdramc, #AT91_DDRSDRC_LPR]
|
||||
|
||||
/* if we use the second ram controller */
|
||||
cmp ramc1, #0
|
||||
ldrne tmp2, .saved_sam9_lpr1
|
||||
strne tmp2, [ramc1, #AT91_DDRSDRC_LPR]
|
||||
|
||||
b ram_restored
|
||||
|
||||
/*
|
||||
* SDRAMC Memory controller
|
||||
*/
|
||||
sdr_en_restore:
|
||||
/* Restore LPR on AT91 with SDRAM */
|
||||
ldr tmp1, .saved_sam9_lpr
|
||||
str tmp1, [sdramc, #AT91_SDRAMC_LPR]
|
||||
|
||||
ram_restored:
|
||||
/* Restore registers, and return */
|
||||
ldmfd sp!, {r4 - r12, pc}
|
||||
|
||||
|
||||
.saved_mckr:
|
||||
.word 0
|
||||
|
||||
.saved_pllar:
|
||||
.word 0
|
||||
|
||||
.saved_pllbr:
|
||||
.word 0
|
||||
|
||||
.saved_sam9_lpr:
|
||||
.word 0
|
||||
|
||||
.saved_sam9_lpr1:
|
||||
.word 0
|
||||
|
||||
ENTRY(at91_slow_clock_sz)
|
||||
.word .-at91_slow_clock
|
||||
337
arch/arm/mach-at91/pm_suspend.S
Normal file
337
arch/arm/mach-at91/pm_suspend.S
Normal file
@ -0,0 +1,337 @@
|
||||
/*
|
||||
* arch/arm/mach-at91/pm_slow_clock.S
|
||||
*
|
||||
* Copyright (C) 2006 Savin Zlobec
|
||||
*
|
||||
* AT91SAM9 support:
|
||||
* Copyright (C) 2007 Anti Sullin <anti.sullin@artecdesign.ee
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
*/
|
||||
#include <linux/linkage.h>
|
||||
#include <linux/clk/at91_pmc.h>
|
||||
#include <mach/at91_ramc.h>
|
||||
#include "pm.h"
|
||||
|
||||
#define SRAMC_SELF_FRESH_ACTIVE 0x01
|
||||
#define SRAMC_SELF_FRESH_EXIT 0x00
|
||||
|
||||
pmc .req r0
|
||||
tmp1 .req r4
|
||||
tmp2 .req r5
|
||||
|
||||
/*
|
||||
* Wait until master clock is ready (after switching master clock source)
|
||||
*/
|
||||
.macro wait_mckrdy
|
||||
1: ldr tmp1, [pmc, #AT91_PMC_SR]
|
||||
tst tmp1, #AT91_PMC_MCKRDY
|
||||
beq 1b
|
||||
.endm
|
||||
|
||||
/*
|
||||
* Wait until master oscillator has stabilized.
|
||||
*/
|
||||
.macro wait_moscrdy
|
||||
1: ldr tmp1, [pmc, #AT91_PMC_SR]
|
||||
tst tmp1, #AT91_PMC_MOSCS
|
||||
beq 1b
|
||||
.endm
|
||||
|
||||
/*
|
||||
* Wait until PLLA has locked.
|
||||
*/
|
||||
.macro wait_pllalock
|
||||
1: ldr tmp1, [pmc, #AT91_PMC_SR]
|
||||
tst tmp1, #AT91_PMC_LOCKA
|
||||
beq 1b
|
||||
.endm
|
||||
|
||||
/*
|
||||
* Put the processor to enter the idle state
|
||||
*/
|
||||
.macro at91_cpu_idle
|
||||
|
||||
#if defined(CONFIG_CPU_V7)
|
||||
mov tmp1, #AT91_PMC_PCK
|
||||
str tmp1, [pmc, #AT91_PMC_SCDR]
|
||||
|
||||
dsb
|
||||
|
||||
wfi @ Wait For Interrupt
|
||||
#else
|
||||
mcr p15, 0, tmp1, c7, c0, 4
|
||||
#endif
|
||||
|
||||
.endm
|
||||
|
||||
.text
|
||||
|
||||
.arm
|
||||
|
||||
/*
|
||||
* void at91_pm_suspend_in_sram(void __iomem *pmc, void __iomem *sdramc,
|
||||
* void __iomem *ramc1, int memctrl)
|
||||
* @input param:
|
||||
* @r0: base address of AT91_PMC
|
||||
* @r1: base address of SDRAM Controller (SDRAM, DDRSDR, or AT91_SYS)
|
||||
* @r2: base address of second SDRAM Controller or 0 if not present
|
||||
* @r3: pm information
|
||||
*/
|
||||
ENTRY(at91_pm_suspend_in_sram)
|
||||
/* Save registers on stack */
|
||||
stmfd sp!, {r4 - r12, lr}
|
||||
|
||||
/* Drain write buffer */
|
||||
mov tmp1, #0
|
||||
mcr p15, 0, tmp1, c7, c10, 4
|
||||
|
||||
str r0, .pmc_base
|
||||
str r1, .sramc_base
|
||||
str r2, .sramc1_base
|
||||
|
||||
and r0, r3, #AT91_PM_MEMTYPE_MASK
|
||||
str r0, .memtype
|
||||
|
||||
lsr r0, r3, #AT91_PM_MODE_OFFSET
|
||||
and r0, r0, #AT91_PM_MODE_MASK
|
||||
str r0, .pm_mode
|
||||
|
||||
/* Active the self-refresh mode */
|
||||
mov r0, #SRAMC_SELF_FRESH_ACTIVE
|
||||
bl at91_sramc_self_refresh
|
||||
|
||||
ldr r0, .pm_mode
|
||||
tst r0, #AT91_PM_SLOW_CLOCK
|
||||
beq skip_disable_main_clock
|
||||
|
||||
ldr pmc, .pmc_base
|
||||
|
||||
/* Save Master clock setting */
|
||||
ldr tmp1, [pmc, #AT91_PMC_MCKR]
|
||||
str tmp1, .saved_mckr
|
||||
|
||||
/*
|
||||
* Set the Master clock source to slow clock
|
||||
*/
|
||||
bic tmp1, tmp1, #AT91_PMC_CSS
|
||||
str tmp1, [pmc, #AT91_PMC_MCKR]
|
||||
|
||||
wait_mckrdy
|
||||
|
||||
/* Save PLLA setting and disable it */
|
||||
ldr tmp1, [pmc, #AT91_CKGR_PLLAR]
|
||||
str tmp1, .saved_pllar
|
||||
|
||||
mov tmp1, #AT91_PMC_PLLCOUNT
|
||||
orr tmp1, tmp1, #(1 << 29) /* bit 29 always set */
|
||||
str tmp1, [pmc, #AT91_CKGR_PLLAR]
|
||||
|
||||
/* Turn off the main oscillator */
|
||||
ldr tmp1, [pmc, #AT91_CKGR_MOR]
|
||||
bic tmp1, tmp1, #AT91_PMC_MOSCEN
|
||||
orr tmp1, tmp1, #AT91_PMC_KEY
|
||||
str tmp1, [pmc, #AT91_CKGR_MOR]
|
||||
|
||||
skip_disable_main_clock:
|
||||
ldr pmc, .pmc_base
|
||||
|
||||
/* Wait for interrupt */
|
||||
at91_cpu_idle
|
||||
|
||||
ldr r0, .pm_mode
|
||||
tst r0, #AT91_PM_SLOW_CLOCK
|
||||
beq skip_enable_main_clock
|
||||
|
||||
ldr pmc, .pmc_base
|
||||
|
||||
/* Turn on the main oscillator */
|
||||
ldr tmp1, [pmc, #AT91_CKGR_MOR]
|
||||
orr tmp1, tmp1, #AT91_PMC_MOSCEN
|
||||
orr tmp1, tmp1, #AT91_PMC_KEY
|
||||
str tmp1, [pmc, #AT91_CKGR_MOR]
|
||||
|
||||
wait_moscrdy
|
||||
|
||||
/* Restore PLLA setting */
|
||||
ldr tmp1, .saved_pllar
|
||||
str tmp1, [pmc, #AT91_CKGR_PLLAR]
|
||||
|
||||
tst tmp1, #(AT91_PMC_MUL & 0xff0000)
|
||||
bne 3f
|
||||
tst tmp1, #(AT91_PMC_MUL & ~0xff0000)
|
||||
beq 4f
|
||||
3:
|
||||
wait_pllalock
|
||||
4:
|
||||
|
||||
/*
|
||||
* Restore master clock setting
|
||||
*/
|
||||
ldr tmp1, .saved_mckr
|
||||
str tmp1, [pmc, #AT91_PMC_MCKR]
|
||||
|
||||
wait_mckrdy
|
||||
|
||||
skip_enable_main_clock:
|
||||
/* Exit the self-refresh mode */
|
||||
mov r0, #SRAMC_SELF_FRESH_EXIT
|
||||
bl at91_sramc_self_refresh
|
||||
|
||||
/* Restore registers, and return */
|
||||
ldmfd sp!, {r4 - r12, pc}
|
||||
ENDPROC(at91_pm_suspend_in_sram)
|
||||
|
||||
/*
|
||||
* void at91_sramc_self_refresh(unsigned int is_active)
|
||||
*
|
||||
* @input param:
|
||||
* @r0: 1 - active self-refresh mode
|
||||
* 0 - exit self-refresh mode
|
||||
* register usage:
|
||||
* @r1: memory type
|
||||
* @r2: base address of the sram controller
|
||||
*/
|
||||
|
||||
ENTRY(at91_sramc_self_refresh)
|
||||
ldr r1, .memtype
|
||||
ldr r2, .sramc_base
|
||||
|
||||
cmp r1, #AT91_MEMCTRL_MC
|
||||
bne ddrc_sf
|
||||
|
||||
/*
|
||||
* at91rm9200 Memory controller
|
||||
*/
|
||||
|
||||
/*
|
||||
* For exiting the self-refresh mode, do nothing,
|
||||
* automatically exit the self-refresh mode.
|
||||
*/
|
||||
tst r0, #SRAMC_SELF_FRESH_ACTIVE
|
||||
beq exit_sramc_sf
|
||||
|
||||
/* Active SDRAM self-refresh mode */
|
||||
mov r3, #1
|
||||
str r3, [r2, #AT91RM9200_SDRAMC_SRR]
|
||||
b exit_sramc_sf
|
||||
|
||||
ddrc_sf:
|
||||
cmp r1, #AT91_MEMCTRL_DDRSDR
|
||||
bne sdramc_sf
|
||||
|
||||
/*
|
||||
* DDR Memory controller
|
||||
*/
|
||||
tst r0, #SRAMC_SELF_FRESH_ACTIVE
|
||||
beq ddrc_exit_sf
|
||||
|
||||
/* LPDDR1 --> force DDR2 mode during self-refresh */
|
||||
ldr r3, [r2, #AT91_DDRSDRC_MDR]
|
||||
str r3, .saved_sam9_mdr
|
||||
bic r3, r3, #~AT91_DDRSDRC_MD
|
||||
cmp r3, #AT91_DDRSDRC_MD_LOW_POWER_DDR
|
||||
ldreq r3, [r2, #AT91_DDRSDRC_MDR]
|
||||
biceq r3, r3, #AT91_DDRSDRC_MD
|
||||
orreq r3, r3, #AT91_DDRSDRC_MD_DDR2
|
||||
streq r3, [r2, #AT91_DDRSDRC_MDR]
|
||||
|
||||
/* Active DDRC self-refresh mode */
|
||||
ldr r3, [r2, #AT91_DDRSDRC_LPR]
|
||||
str r3, .saved_sam9_lpr
|
||||
bic r3, r3, #AT91_DDRSDRC_LPCB
|
||||
orr r3, r3, #AT91_DDRSDRC_LPCB_SELF_REFRESH
|
||||
str r3, [r2, #AT91_DDRSDRC_LPR]
|
||||
|
||||
/* If using the 2nd ddr controller */
|
||||
ldr r2, .sramc1_base
|
||||
cmp r2, #0
|
||||
beq no_2nd_ddrc
|
||||
|
||||
ldr r3, [r2, #AT91_DDRSDRC_MDR]
|
||||
str r3, .saved_sam9_mdr1
|
||||
bic r3, r3, #~AT91_DDRSDRC_MD
|
||||
cmp r3, #AT91_DDRSDRC_MD_LOW_POWER_DDR
|
||||
ldreq r3, [r2, #AT91_DDRSDRC_MDR]
|
||||
biceq r3, r3, #AT91_DDRSDRC_MD
|
||||
orreq r3, r3, #AT91_DDRSDRC_MD_DDR2
|
||||
streq r3, [r2, #AT91_DDRSDRC_MDR]
|
||||
|
||||
/* Active DDRC self-refresh mode */
|
||||
ldr r3, [r2, #AT91_DDRSDRC_LPR]
|
||||
str r3, .saved_sam9_lpr1
|
||||
bic r3, r3, #AT91_DDRSDRC_LPCB
|
||||
orr r3, r3, #AT91_DDRSDRC_LPCB_SELF_REFRESH
|
||||
str r3, [r2, #AT91_DDRSDRC_LPR]
|
||||
|
||||
no_2nd_ddrc:
|
||||
b exit_sramc_sf
|
||||
|
||||
ddrc_exit_sf:
|
||||
/* Restore MDR in case of LPDDR1 */
|
||||
ldr r3, .saved_sam9_mdr
|
||||
str r3, [r2, #AT91_DDRSDRC_MDR]
|
||||
/* Restore LPR on AT91 with DDRAM */
|
||||
ldr r3, .saved_sam9_lpr
|
||||
str r3, [r2, #AT91_DDRSDRC_LPR]
|
||||
|
||||
/* If using the 2nd ddr controller */
|
||||
ldr r2, .sramc1_base
|
||||
cmp r2, #0
|
||||
ldrne r3, .saved_sam9_mdr1
|
||||
strne r3, [r2, #AT91_DDRSDRC_MDR]
|
||||
ldrne r3, .saved_sam9_lpr1
|
||||
strne r3, [r2, #AT91_DDRSDRC_LPR]
|
||||
|
||||
b exit_sramc_sf
|
||||
|
||||
/*
|
||||
* SDRAMC Memory controller
|
||||
*/
|
||||
sdramc_sf:
|
||||
tst r0, #SRAMC_SELF_FRESH_ACTIVE
|
||||
beq sdramc_exit_sf
|
||||
|
||||
/* Active SDRAMC self-refresh mode */
|
||||
ldr r3, [r2, #AT91_SDRAMC_LPR]
|
||||
str r3, .saved_sam9_lpr
|
||||
bic r3, r3, #AT91_SDRAMC_LPCB
|
||||
orr r3, r3, #AT91_SDRAMC_LPCB_SELF_REFRESH
|
||||
str r3, [r2, #AT91_SDRAMC_LPR]
|
||||
|
||||
sdramc_exit_sf:
|
||||
ldr r3, .saved_sam9_lpr
|
||||
str r3, [r2, #AT91_SDRAMC_LPR]
|
||||
|
||||
exit_sramc_sf:
|
||||
mov pc, lr
|
||||
ENDPROC(at91_sramc_self_refresh)
|
||||
|
||||
.pmc_base:
|
||||
.word 0
|
||||
.sramc_base:
|
||||
.word 0
|
||||
.sramc1_base:
|
||||
.word 0
|
||||
.memtype:
|
||||
.word 0
|
||||
.pm_mode:
|
||||
.word 0
|
||||
.saved_mckr:
|
||||
.word 0
|
||||
.saved_pllar:
|
||||
.word 0
|
||||
.saved_sam9_lpr:
|
||||
.word 0
|
||||
.saved_sam9_lpr1:
|
||||
.word 0
|
||||
.saved_sam9_mdr:
|
||||
.word 0
|
||||
.saved_sam9_mdr1:
|
||||
.word 0
|
||||
|
||||
ENTRY(at91_pm_suspend_in_sram_sz)
|
||||
.word .-at91_pm_suspend_in_sram
|
||||
@ -7,48 +7,48 @@
|
||||
* Licensed under GPLv2 or later.
|
||||
*/
|
||||
|
||||
#include <linux/types.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/micrel_phy.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_irq.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/phy.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/phy.h>
|
||||
|
||||
#include <mach/hardware.h>
|
||||
|
||||
#include <asm/setup.h>
|
||||
#include <asm/irq.h>
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach/map.h>
|
||||
#include <asm/mach/irq.h>
|
||||
#include <asm/system_misc.h>
|
||||
|
||||
#include "generic.h"
|
||||
#include "soc.h"
|
||||
|
||||
static int ksz8081_phy_fixup(struct phy_device *phy)
|
||||
{
|
||||
int value;
|
||||
|
||||
value = phy_read(phy, 0x16);
|
||||
value &= ~0x20;
|
||||
phy_write(phy, 0x16, value);
|
||||
|
||||
return 0;
|
||||
}
|
||||
static const struct at91_soc sama5_socs[] = {
|
||||
AT91_SOC(SAMA5D3_CIDR_MATCH, SAMA5D31_EXID_MATCH,
|
||||
"sama5d31", "sama5d3"),
|
||||
AT91_SOC(SAMA5D3_CIDR_MATCH, SAMA5D33_EXID_MATCH,
|
||||
"sama5d33", "sama5d3"),
|
||||
AT91_SOC(SAMA5D3_CIDR_MATCH, SAMA5D34_EXID_MATCH,
|
||||
"sama5d34", "sama5d3"),
|
||||
AT91_SOC(SAMA5D3_CIDR_MATCH, SAMA5D35_EXID_MATCH,
|
||||
"sama5d35", "sama5d3"),
|
||||
AT91_SOC(SAMA5D3_CIDR_MATCH, SAMA5D36_EXID_MATCH,
|
||||
"sama5d36", "sama5d3"),
|
||||
AT91_SOC(SAMA5D4_CIDR_MATCH, SAMA5D41_EXID_MATCH,
|
||||
"sama5d41", "sama5d4"),
|
||||
AT91_SOC(SAMA5D4_CIDR_MATCH, SAMA5D42_EXID_MATCH,
|
||||
"sama5d42", "sama5d4"),
|
||||
AT91_SOC(SAMA5D4_CIDR_MATCH, SAMA5D43_EXID_MATCH,
|
||||
"sama5d43", "sama5d4"),
|
||||
AT91_SOC(SAMA5D4_CIDR_MATCH, SAMA5D44_EXID_MATCH,
|
||||
"sama5d44", "sama5d4"),
|
||||
{ /* sentinel */ },
|
||||
};
|
||||
|
||||
static void __init sama5_dt_device_init(void)
|
||||
{
|
||||
if (of_machine_is_compatible("atmel,sama5d4ek") &&
|
||||
IS_ENABLED(CONFIG_PHYLIB)) {
|
||||
phy_register_fixup_for_id("fc028000.etherne:00",
|
||||
ksz8081_phy_fixup);
|
||||
}
|
||||
struct soc_device *soc;
|
||||
struct device *soc_dev = NULL;
|
||||
|
||||
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
|
||||
soc = at91_soc_init(sama5_socs);
|
||||
if (soc != NULL)
|
||||
soc_dev = soc_device_to_device(soc);
|
||||
|
||||
of_platform_populate(NULL, of_default_bus_match_table, NULL, soc_dev);
|
||||
at91sam9x5_pm_init();
|
||||
}
|
||||
|
||||
@ -59,44 +59,10 @@ static const char *sama5_dt_board_compat[] __initconst = {
|
||||
|
||||
DT_MACHINE_START(sama5_dt, "Atmel SAMA5")
|
||||
/* Maintainer: Atmel */
|
||||
.map_io = at91_map_io,
|
||||
.init_machine = sama5_dt_device_init,
|
||||
.dt_compat = sama5_dt_board_compat,
|
||||
MACHINE_END
|
||||
|
||||
static struct map_desc at91_io_desc[] __initdata = {
|
||||
{
|
||||
.virtual = (unsigned long)AT91_ALT_IO_P2V(SAMA5D4_BASE_MPDDRC),
|
||||
.pfn = __phys_to_pfn(SAMA5D4_BASE_MPDDRC),
|
||||
.length = SZ_512,
|
||||
.type = MT_DEVICE,
|
||||
},
|
||||
{
|
||||
.virtual = (unsigned long)AT91_ALT_IO_P2V(SAMA5D4_BASE_PMC),
|
||||
.pfn = __phys_to_pfn(SAMA5D4_BASE_PMC),
|
||||
.length = SZ_512,
|
||||
.type = MT_DEVICE,
|
||||
},
|
||||
{ /* On sama5d4, we use USART3 as serial console */
|
||||
.virtual = (unsigned long)AT91_ALT_IO_P2V(SAMA5D4_BASE_USART3),
|
||||
.pfn = __phys_to_pfn(SAMA5D4_BASE_USART3),
|
||||
.length = SZ_256,
|
||||
.type = MT_DEVICE,
|
||||
},
|
||||
{ /* A bunch of peripheral with fine grained IO space */
|
||||
.virtual = (unsigned long)AT91_ALT_IO_P2V(SAMA5D4_BASE_SYS2),
|
||||
.pfn = __phys_to_pfn(SAMA5D4_BASE_SYS2),
|
||||
.length = SZ_2K,
|
||||
.type = MT_DEVICE,
|
||||
},
|
||||
};
|
||||
|
||||
static void __init sama5_alt_map_io(void)
|
||||
{
|
||||
at91_alt_map_io();
|
||||
iotable_init(at91_io_desc, ARRAY_SIZE(at91_io_desc));
|
||||
}
|
||||
|
||||
static const char *sama5_alt_dt_board_compat[] __initconst = {
|
||||
"atmel,sama5d4",
|
||||
NULL
|
||||
@ -104,7 +70,6 @@ static const char *sama5_alt_dt_board_compat[] __initconst = {
|
||||
|
||||
DT_MACHINE_START(sama5_alt_dt, "Atmel SAMA5")
|
||||
/* Maintainer: Atmel */
|
||||
.map_io = sama5_alt_map_io,
|
||||
.init_machine = sama5_dt_device_init,
|
||||
.dt_compat = sama5_alt_dt_board_compat,
|
||||
.l2c_aux_mask = ~0UL,
|
||||
|
||||
@ -1,330 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2007 Atmel Corporation.
|
||||
* Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
|
||||
*
|
||||
* Under GPLv2
|
||||
*/
|
||||
|
||||
#define pr_fmt(fmt) "AT91: " fmt
|
||||
|
||||
#include <linux/module.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/mm.h>
|
||||
#include <linux/pm.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/pinctrl/machine.h>
|
||||
#include <linux/clk/at91_pmc.h>
|
||||
|
||||
#include <asm/system_misc.h>
|
||||
#include <asm/mach/map.h>
|
||||
|
||||
#include <mach/hardware.h>
|
||||
#include <mach/cpu.h>
|
||||
#include <mach/at91_dbgu.h>
|
||||
|
||||
#include "generic.h"
|
||||
#include "pm.h"
|
||||
|
||||
struct at91_socinfo at91_soc_initdata;
|
||||
EXPORT_SYMBOL(at91_soc_initdata);
|
||||
|
||||
static struct map_desc at91_io_desc __initdata __maybe_unused = {
|
||||
.virtual = (unsigned long)AT91_VA_BASE_SYS,
|
||||
.pfn = __phys_to_pfn(AT91_BASE_SYS),
|
||||
.length = SZ_16K,
|
||||
.type = MT_DEVICE,
|
||||
};
|
||||
|
||||
static struct map_desc at91_alt_io_desc __initdata __maybe_unused = {
|
||||
.virtual = (unsigned long)AT91_ALT_VA_BASE_SYS,
|
||||
.pfn = __phys_to_pfn(AT91_ALT_BASE_SYS),
|
||||
.length = 24 * SZ_1K,
|
||||
.type = MT_DEVICE,
|
||||
};
|
||||
|
||||
static void __init soc_detect(u32 dbgu_base)
|
||||
{
|
||||
u32 cidr, socid;
|
||||
|
||||
cidr = __raw_readl(AT91_IO_P2V(dbgu_base) + AT91_DBGU_CIDR);
|
||||
socid = cidr & ~AT91_CIDR_VERSION;
|
||||
|
||||
switch (socid) {
|
||||
case ARCH_ID_AT91RM9200:
|
||||
at91_soc_initdata.type = AT91_SOC_RM9200;
|
||||
if (at91_soc_initdata.subtype == AT91_SOC_SUBTYPE_UNKNOWN)
|
||||
at91_soc_initdata.subtype = AT91_SOC_RM9200_BGA;
|
||||
break;
|
||||
|
||||
case ARCH_ID_AT91SAM9260:
|
||||
at91_soc_initdata.type = AT91_SOC_SAM9260;
|
||||
at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE;
|
||||
break;
|
||||
|
||||
case ARCH_ID_AT91SAM9261:
|
||||
at91_soc_initdata.type = AT91_SOC_SAM9261;
|
||||
at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE;
|
||||
break;
|
||||
|
||||
case ARCH_ID_AT91SAM9263:
|
||||
at91_soc_initdata.type = AT91_SOC_SAM9263;
|
||||
at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE;
|
||||
break;
|
||||
|
||||
case ARCH_ID_AT91SAM9G20:
|
||||
at91_soc_initdata.type = AT91_SOC_SAM9G20;
|
||||
at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE;
|
||||
break;
|
||||
|
||||
case ARCH_ID_AT91SAM9G45:
|
||||
at91_soc_initdata.type = AT91_SOC_SAM9G45;
|
||||
if (cidr == ARCH_ID_AT91SAM9G45ES)
|
||||
at91_soc_initdata.subtype = AT91_SOC_SAM9G45ES;
|
||||
break;
|
||||
|
||||
case ARCH_ID_AT91SAM9RL64:
|
||||
at91_soc_initdata.type = AT91_SOC_SAM9RL;
|
||||
at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE;
|
||||
break;
|
||||
|
||||
case ARCH_ID_AT91SAM9X5:
|
||||
at91_soc_initdata.type = AT91_SOC_SAM9X5;
|
||||
break;
|
||||
|
||||
case ARCH_ID_AT91SAM9N12:
|
||||
at91_soc_initdata.type = AT91_SOC_SAM9N12;
|
||||
break;
|
||||
|
||||
case ARCH_ID_SAMA5:
|
||||
at91_soc_initdata.exid = __raw_readl(AT91_IO_P2V(dbgu_base) + AT91_DBGU_EXID);
|
||||
if (at91_soc_initdata.exid & ARCH_EXID_SAMA5D3) {
|
||||
at91_soc_initdata.type = AT91_SOC_SAMA5D3;
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
/* at91sam9g10 */
|
||||
if ((socid & ~AT91_CIDR_EXT) == ARCH_ID_AT91SAM9G10) {
|
||||
at91_soc_initdata.type = AT91_SOC_SAM9G10;
|
||||
at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE;
|
||||
}
|
||||
/* at91sam9xe */
|
||||
else if ((cidr & AT91_CIDR_ARCH) == ARCH_FAMILY_AT91SAM9XE) {
|
||||
at91_soc_initdata.type = AT91_SOC_SAM9260;
|
||||
at91_soc_initdata.subtype = AT91_SOC_SAM9XE;
|
||||
}
|
||||
|
||||
if (!at91_soc_is_detected())
|
||||
return;
|
||||
|
||||
at91_soc_initdata.cidr = cidr;
|
||||
|
||||
/* sub version of soc */
|
||||
if (!at91_soc_initdata.exid)
|
||||
at91_soc_initdata.exid = __raw_readl(AT91_IO_P2V(dbgu_base) + AT91_DBGU_EXID);
|
||||
|
||||
if (at91_soc_initdata.type == AT91_SOC_SAM9G45) {
|
||||
switch (at91_soc_initdata.exid) {
|
||||
case ARCH_EXID_AT91SAM9M10:
|
||||
at91_soc_initdata.subtype = AT91_SOC_SAM9M10;
|
||||
break;
|
||||
case ARCH_EXID_AT91SAM9G46:
|
||||
at91_soc_initdata.subtype = AT91_SOC_SAM9G46;
|
||||
break;
|
||||
case ARCH_EXID_AT91SAM9M11:
|
||||
at91_soc_initdata.subtype = AT91_SOC_SAM9M11;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (at91_soc_initdata.type == AT91_SOC_SAM9X5) {
|
||||
switch (at91_soc_initdata.exid) {
|
||||
case ARCH_EXID_AT91SAM9G15:
|
||||
at91_soc_initdata.subtype = AT91_SOC_SAM9G15;
|
||||
break;
|
||||
case ARCH_EXID_AT91SAM9G35:
|
||||
at91_soc_initdata.subtype = AT91_SOC_SAM9G35;
|
||||
break;
|
||||
case ARCH_EXID_AT91SAM9X35:
|
||||
at91_soc_initdata.subtype = AT91_SOC_SAM9X35;
|
||||
break;
|
||||
case ARCH_EXID_AT91SAM9G25:
|
||||
at91_soc_initdata.subtype = AT91_SOC_SAM9G25;
|
||||
break;
|
||||
case ARCH_EXID_AT91SAM9X25:
|
||||
at91_soc_initdata.subtype = AT91_SOC_SAM9X25;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (at91_soc_initdata.type == AT91_SOC_SAMA5D3) {
|
||||
switch (at91_soc_initdata.exid) {
|
||||
case ARCH_EXID_SAMA5D31:
|
||||
at91_soc_initdata.subtype = AT91_SOC_SAMA5D31;
|
||||
break;
|
||||
case ARCH_EXID_SAMA5D33:
|
||||
at91_soc_initdata.subtype = AT91_SOC_SAMA5D33;
|
||||
break;
|
||||
case ARCH_EXID_SAMA5D34:
|
||||
at91_soc_initdata.subtype = AT91_SOC_SAMA5D34;
|
||||
break;
|
||||
case ARCH_EXID_SAMA5D35:
|
||||
at91_soc_initdata.subtype = AT91_SOC_SAMA5D35;
|
||||
break;
|
||||
case ARCH_EXID_SAMA5D36:
|
||||
at91_soc_initdata.subtype = AT91_SOC_SAMA5D36;
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static void __init alt_soc_detect(u32 dbgu_base)
|
||||
{
|
||||
u32 cidr, socid;
|
||||
|
||||
/* SoC ID */
|
||||
cidr = __raw_readl(AT91_ALT_IO_P2V(dbgu_base) + AT91_DBGU_CIDR);
|
||||
socid = cidr & ~AT91_CIDR_VERSION;
|
||||
|
||||
switch (socid) {
|
||||
case ARCH_ID_SAMA5:
|
||||
at91_soc_initdata.exid = __raw_readl(AT91_ALT_IO_P2V(dbgu_base) + AT91_DBGU_EXID);
|
||||
if (at91_soc_initdata.exid & ARCH_EXID_SAMA5D3) {
|
||||
at91_soc_initdata.type = AT91_SOC_SAMA5D3;
|
||||
} else if (at91_soc_initdata.exid & ARCH_EXID_SAMA5D4) {
|
||||
at91_soc_initdata.type = AT91_SOC_SAMA5D4;
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
if (!at91_soc_is_detected())
|
||||
return;
|
||||
|
||||
at91_soc_initdata.cidr = cidr;
|
||||
|
||||
/* sub version of soc */
|
||||
if (!at91_soc_initdata.exid)
|
||||
at91_soc_initdata.exid = __raw_readl(AT91_ALT_IO_P2V(dbgu_base) + AT91_DBGU_EXID);
|
||||
|
||||
if (at91_soc_initdata.type == AT91_SOC_SAMA5D4) {
|
||||
switch (at91_soc_initdata.exid) {
|
||||
case ARCH_EXID_SAMA5D41:
|
||||
at91_soc_initdata.subtype = AT91_SOC_SAMA5D41;
|
||||
break;
|
||||
case ARCH_EXID_SAMA5D42:
|
||||
at91_soc_initdata.subtype = AT91_SOC_SAMA5D42;
|
||||
break;
|
||||
case ARCH_EXID_SAMA5D43:
|
||||
at91_soc_initdata.subtype = AT91_SOC_SAMA5D43;
|
||||
break;
|
||||
case ARCH_EXID_SAMA5D44:
|
||||
at91_soc_initdata.subtype = AT91_SOC_SAMA5D44;
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static const char *soc_name[] = {
|
||||
[AT91_SOC_RM9200] = "at91rm9200",
|
||||
[AT91_SOC_SAM9260] = "at91sam9260",
|
||||
[AT91_SOC_SAM9261] = "at91sam9261",
|
||||
[AT91_SOC_SAM9263] = "at91sam9263",
|
||||
[AT91_SOC_SAM9G10] = "at91sam9g10",
|
||||
[AT91_SOC_SAM9G20] = "at91sam9g20",
|
||||
[AT91_SOC_SAM9G45] = "at91sam9g45",
|
||||
[AT91_SOC_SAM9RL] = "at91sam9rl",
|
||||
[AT91_SOC_SAM9X5] = "at91sam9x5",
|
||||
[AT91_SOC_SAM9N12] = "at91sam9n12",
|
||||
[AT91_SOC_SAMA5D3] = "sama5d3",
|
||||
[AT91_SOC_SAMA5D4] = "sama5d4",
|
||||
[AT91_SOC_UNKNOWN] = "Unknown",
|
||||
};
|
||||
|
||||
const char *at91_get_soc_type(struct at91_socinfo *c)
|
||||
{
|
||||
return soc_name[c->type];
|
||||
}
|
||||
EXPORT_SYMBOL(at91_get_soc_type);
|
||||
|
||||
static const char *soc_subtype_name[] = {
|
||||
[AT91_SOC_RM9200_BGA] = "at91rm9200 BGA",
|
||||
[AT91_SOC_RM9200_PQFP] = "at91rm9200 PQFP",
|
||||
[AT91_SOC_SAM9XE] = "at91sam9xe",
|
||||
[AT91_SOC_SAM9G45ES] = "at91sam9g45es",
|
||||
[AT91_SOC_SAM9M10] = "at91sam9m10",
|
||||
[AT91_SOC_SAM9G46] = "at91sam9g46",
|
||||
[AT91_SOC_SAM9M11] = "at91sam9m11",
|
||||
[AT91_SOC_SAM9G15] = "at91sam9g15",
|
||||
[AT91_SOC_SAM9G35] = "at91sam9g35",
|
||||
[AT91_SOC_SAM9X35] = "at91sam9x35",
|
||||
[AT91_SOC_SAM9G25] = "at91sam9g25",
|
||||
[AT91_SOC_SAM9X25] = "at91sam9x25",
|
||||
[AT91_SOC_SAMA5D31] = "sama5d31",
|
||||
[AT91_SOC_SAMA5D33] = "sama5d33",
|
||||
[AT91_SOC_SAMA5D34] = "sama5d34",
|
||||
[AT91_SOC_SAMA5D35] = "sama5d35",
|
||||
[AT91_SOC_SAMA5D36] = "sama5d36",
|
||||
[AT91_SOC_SAMA5D41] = "sama5d41",
|
||||
[AT91_SOC_SAMA5D42] = "sama5d42",
|
||||
[AT91_SOC_SAMA5D43] = "sama5d43",
|
||||
[AT91_SOC_SAMA5D44] = "sama5d44",
|
||||
[AT91_SOC_SUBTYPE_NONE] = "None",
|
||||
[AT91_SOC_SUBTYPE_UNKNOWN] = "Unknown",
|
||||
};
|
||||
|
||||
const char *at91_get_soc_subtype(struct at91_socinfo *c)
|
||||
{
|
||||
return soc_subtype_name[c->subtype];
|
||||
}
|
||||
EXPORT_SYMBOL(at91_get_soc_subtype);
|
||||
|
||||
void __init at91_map_io(void)
|
||||
{
|
||||
/* Map peripherals */
|
||||
iotable_init(&at91_io_desc, 1);
|
||||
|
||||
at91_soc_initdata.type = AT91_SOC_UNKNOWN;
|
||||
at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_UNKNOWN;
|
||||
|
||||
soc_detect(AT91_BASE_DBGU0);
|
||||
if (!at91_soc_is_detected())
|
||||
soc_detect(AT91_BASE_DBGU1);
|
||||
|
||||
if (!at91_soc_is_detected())
|
||||
panic(pr_fmt("Impossible to detect the SOC type"));
|
||||
|
||||
pr_info("Detected soc type: %s\n",
|
||||
at91_get_soc_type(&at91_soc_initdata));
|
||||
if (at91_soc_initdata.subtype != AT91_SOC_SUBTYPE_NONE)
|
||||
pr_info("Detected soc subtype: %s\n",
|
||||
at91_get_soc_subtype(&at91_soc_initdata));
|
||||
}
|
||||
|
||||
void __init at91_alt_map_io(void)
|
||||
{
|
||||
/* Map peripherals */
|
||||
iotable_init(&at91_alt_io_desc, 1);
|
||||
|
||||
at91_soc_initdata.type = AT91_SOC_UNKNOWN;
|
||||
at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_UNKNOWN;
|
||||
|
||||
alt_soc_detect(AT91_BASE_DBGU2);
|
||||
if (!at91_soc_is_detected())
|
||||
panic("AT91: Impossible to detect the SOC type");
|
||||
|
||||
pr_info("AT91: Detected soc type: %s\n",
|
||||
at91_get_soc_type(&at91_soc_initdata));
|
||||
if (at91_soc_initdata.subtype != AT91_SOC_SUBTYPE_NONE)
|
||||
pr_info("AT91: Detected soc subtype: %s\n",
|
||||
at91_get_soc_subtype(&at91_soc_initdata));
|
||||
}
|
||||
|
||||
void __iomem *at91_matrix_base;
|
||||
EXPORT_SYMBOL_GPL(at91_matrix_base);
|
||||
|
||||
void __init at91_ioremap_matrix(u32 base_addr)
|
||||
{
|
||||
at91_matrix_base = ioremap(base_addr, 512);
|
||||
if (!at91_matrix_base)
|
||||
panic(pr_fmt("Impossible to ioremap at91_matrix_base\n"));
|
||||
}
|
||||
97
arch/arm/mach-at91/soc.c
Normal file
97
arch/arm/mach-at91/soc.c
Normal file
@ -0,0 +1,97 @@
|
||||
/*
|
||||
* Copyright (C) 2015 Atmel
|
||||
*
|
||||
* Alexandre Belloni <alexandre.belloni@free-electrons.com
|
||||
* Boris Brezillon <boris.brezillon@free-electrons.com
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*
|
||||
*/
|
||||
|
||||
#define pr_fmt(fmt) "AT91: " fmt
|
||||
|
||||
#include <linux/io.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/sys_soc.h>
|
||||
|
||||
#include "soc.h"
|
||||
|
||||
#define AT91_DBGU_CIDR 0x40
|
||||
#define AT91_DBGU_CIDR_VERSION(x) ((x) & 0x1f)
|
||||
#define AT91_DBGU_CIDR_EXT BIT(31)
|
||||
#define AT91_DBGU_CIDR_MATCH_MASK 0x7fffffe0
|
||||
#define AT91_DBGU_EXID 0x44
|
||||
|
||||
struct soc_device * __init at91_soc_init(const struct at91_soc *socs)
|
||||
{
|
||||
struct soc_device_attribute *soc_dev_attr;
|
||||
const struct at91_soc *soc;
|
||||
struct soc_device *soc_dev;
|
||||
struct device_node *np;
|
||||
void __iomem *regs;
|
||||
u32 cidr, exid;
|
||||
|
||||
np = of_find_compatible_node(NULL, NULL, "atmel,at91rm9200-dbgu");
|
||||
if (!np)
|
||||
np = of_find_compatible_node(NULL, NULL,
|
||||
"atmel,at91sam9260-dbgu");
|
||||
|
||||
if (!np) {
|
||||
pr_warn("Could not find DBGU node");
|
||||
return NULL;
|
||||
}
|
||||
|
||||
regs = of_iomap(np, 0);
|
||||
of_node_put(np);
|
||||
|
||||
if (!regs) {
|
||||
pr_warn("Could not map DBGU iomem range");
|
||||
return NULL;
|
||||
}
|
||||
|
||||
cidr = readl(regs + AT91_DBGU_CIDR);
|
||||
exid = readl(regs + AT91_DBGU_EXID);
|
||||
|
||||
iounmap(regs);
|
||||
|
||||
for (soc = socs; soc->name; soc++) {
|
||||
if (soc->cidr_match != (cidr & AT91_DBGU_CIDR_MATCH_MASK))
|
||||
continue;
|
||||
|
||||
if (!(cidr & AT91_DBGU_CIDR_EXT) || soc->exid_match == exid)
|
||||
break;
|
||||
}
|
||||
|
||||
if (!soc->name) {
|
||||
pr_warn("Could not find matching SoC description\n");
|
||||
return NULL;
|
||||
}
|
||||
|
||||
soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
|
||||
if (!soc_dev_attr)
|
||||
return NULL;
|
||||
|
||||
soc_dev_attr->family = soc->family;
|
||||
soc_dev_attr->soc_id = soc->name;
|
||||
soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%X",
|
||||
AT91_DBGU_CIDR_VERSION(cidr));
|
||||
soc_dev = soc_device_register(soc_dev_attr);
|
||||
if (IS_ERR(soc_dev)) {
|
||||
kfree(soc_dev_attr->revision);
|
||||
kfree(soc_dev_attr);
|
||||
pr_warn("Could not register SoC device\n");
|
||||
return NULL;
|
||||
}
|
||||
|
||||
if (soc->family)
|
||||
pr_info("Detected SoC family: %s\n", soc->family);
|
||||
pr_info("Detected SoC: %s, revision %X\n", soc->name,
|
||||
AT91_DBGU_CIDR_VERSION(cidr));
|
||||
|
||||
return soc_dev;
|
||||
}
|
||||
78
arch/arm/mach-at91/soc.h
Normal file
78
arch/arm/mach-at91/soc.h
Normal file
@ -0,0 +1,78 @@
|
||||
/*
|
||||
* Copyright (C) 2015 Atmel
|
||||
*
|
||||
* Boris Brezillon <boris.brezillon@free-electrons.com
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __AT91_SOC_H
|
||||
#define __AT91_SOC_H
|
||||
|
||||
#include <linux/sys_soc.h>
|
||||
|
||||
struct at91_soc {
|
||||
u32 cidr_match;
|
||||
u32 exid_match;
|
||||
const char *name;
|
||||
const char *family;
|
||||
};
|
||||
|
||||
#define AT91_SOC(__cidr, __exid, __name, __family) \
|
||||
{ \
|
||||
.cidr_match = (__cidr), \
|
||||
.exid_match = (__exid), \
|
||||
.name = (__name), \
|
||||
.family = (__family), \
|
||||
}
|
||||
|
||||
struct soc_device * __init
|
||||
at91_soc_init(const struct at91_soc *socs);
|
||||
|
||||
#define AT91RM9200_CIDR_MATCH 0x09290780
|
||||
|
||||
#define AT91SAM9260_CIDR_MATCH 0x019803a0
|
||||
#define AT91SAM9261_CIDR_MATCH 0x019703a0
|
||||
#define AT91SAM9263_CIDR_MATCH 0x019607a0
|
||||
#define AT91SAM9G20_CIDR_MATCH 0x019905a0
|
||||
#define AT91SAM9RL64_CIDR_MATCH 0x019b03a0
|
||||
#define AT91SAM9G45_CIDR_MATCH 0x019b05a0
|
||||
#define AT91SAM9X5_CIDR_MATCH 0x019a05a0
|
||||
#define AT91SAM9N12_CIDR_MATCH 0x019a07a0
|
||||
|
||||
#define AT91SAM9M11_EXID_MATCH 0x00000001
|
||||
#define AT91SAM9M10_EXID_MATCH 0x00000002
|
||||
#define AT91SAM9G46_EXID_MATCH 0x00000003
|
||||
#define AT91SAM9G45_EXID_MATCH 0x00000004
|
||||
|
||||
#define AT91SAM9G15_EXID_MATCH 0x00000000
|
||||
#define AT91SAM9G35_EXID_MATCH 0x00000001
|
||||
#define AT91SAM9X35_EXID_MATCH 0x00000002
|
||||
#define AT91SAM9G25_EXID_MATCH 0x00000003
|
||||
#define AT91SAM9X25_EXID_MATCH 0x00000004
|
||||
|
||||
#define AT91SAM9CN12_EXID_MATCH 0x00000005
|
||||
#define AT91SAM9N12_EXID_MATCH 0x00000006
|
||||
#define AT91SAM9CN11_EXID_MATCH 0x00000009
|
||||
|
||||
#define AT91SAM9XE128_CIDR_MATCH 0x329973a0
|
||||
#define AT91SAM9XE256_CIDR_MATCH 0x329a93a0
|
||||
#define AT91SAM9XE512_CIDR_MATCH 0x329aa3a0
|
||||
|
||||
#define SAMA5D3_CIDR_MATCH 0x0a5c07c0
|
||||
#define SAMA5D31_EXID_MATCH 0x00444300
|
||||
#define SAMA5D33_EXID_MATCH 0x00414300
|
||||
#define SAMA5D34_EXID_MATCH 0x00414301
|
||||
#define SAMA5D35_EXID_MATCH 0x00584300
|
||||
#define SAMA5D36_EXID_MATCH 0x00004301
|
||||
|
||||
#define SAMA5D4_CIDR_MATCH 0x0a5c07c0
|
||||
#define SAMA5D41_EXID_MATCH 0x00000001
|
||||
#define SAMA5D42_EXID_MATCH 0x00000002
|
||||
#define SAMA5D43_EXID_MATCH 0x00000003
|
||||
#define SAMA5D44_EXID_MATCH 0x00000004
|
||||
|
||||
#endif /* __AT91_SOC_H */
|
||||
@ -143,6 +143,10 @@ config ATMEL_PIT
|
||||
select CLKSRC_OF if OF
|
||||
def_bool SOC_AT91SAM9 || SOC_SAMA5
|
||||
|
||||
config ATMEL_ST
|
||||
bool
|
||||
select CLKSRC_OF
|
||||
|
||||
config CLKSRC_METAG_GENERIC
|
||||
def_bool y if METAG
|
||||
help
|
||||
|
||||
@ -1,5 +1,6 @@
|
||||
obj-$(CONFIG_CLKSRC_OF) += clksrc-of.o
|
||||
obj-$(CONFIG_ATMEL_PIT) += timer-atmel-pit.o
|
||||
obj-$(CONFIG_ATMEL_ST) += timer-atmel-st.o
|
||||
obj-$(CONFIG_ATMEL_TCB_CLKSRC) += tcb_clksrc.o
|
||||
obj-$(CONFIG_X86_PM_TIMER) += acpi_pm.o
|
||||
obj-$(CONFIG_SCx200HR_TIMER) += scx200_hrt.o
|
||||
|
||||
@ -24,19 +24,17 @@
|
||||
#include <linux/irq.h>
|
||||
#include <linux/clockchips.h>
|
||||
#include <linux/export.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/mfd/syscon.h>
|
||||
#include <linux/mfd/syscon/atmel-st.h>
|
||||
#include <linux/of_irq.h>
|
||||
|
||||
#include <asm/mach/time.h>
|
||||
|
||||
#include <mach/at91_st.h>
|
||||
#include <mach/hardware.h>
|
||||
#include <linux/regmap.h>
|
||||
|
||||
static unsigned long last_crtr;
|
||||
static u32 irqmask;
|
||||
static struct clock_event_device clkevt;
|
||||
static struct regmap *regmap_st;
|
||||
|
||||
#define AT91_SLOW_CLOCK 32768
|
||||
#define RM9200_TIMER_LATCH ((AT91_SLOW_CLOCK + HZ/2) / HZ)
|
||||
|
||||
/*
|
||||
@ -46,11 +44,11 @@ static struct clock_event_device clkevt;
|
||||
*/
|
||||
static inline unsigned long read_CRTR(void)
|
||||
{
|
||||
unsigned long x1, x2;
|
||||
unsigned int x1, x2;
|
||||
|
||||
x1 = at91_st_read(AT91_ST_CRTR);
|
||||
regmap_read(regmap_st, AT91_ST_CRTR, &x1);
|
||||
do {
|
||||
x2 = at91_st_read(AT91_ST_CRTR);
|
||||
regmap_read(regmap_st, AT91_ST_CRTR, &x2);
|
||||
if (x1 == x2)
|
||||
break;
|
||||
x1 = x2;
|
||||
@ -63,7 +61,10 @@ static inline unsigned long read_CRTR(void)
|
||||
*/
|
||||
static irqreturn_t at91rm9200_timer_interrupt(int irq, void *dev_id)
|
||||
{
|
||||
u32 sr = at91_st_read(AT91_ST_SR) & irqmask;
|
||||
u32 sr;
|
||||
|
||||
regmap_read(regmap_st, AT91_ST_SR, &sr);
|
||||
sr &= irqmask;
|
||||
|
||||
/*
|
||||
* irqs should be disabled here, but as the irq is shared they are only
|
||||
@ -92,13 +93,6 @@ static irqreturn_t at91rm9200_timer_interrupt(int irq, void *dev_id)
|
||||
return IRQ_NONE;
|
||||
}
|
||||
|
||||
static struct irqaction at91rm9200_timer_irq = {
|
||||
.name = "at91_tick",
|
||||
.flags = IRQF_SHARED | IRQF_TIMER | IRQF_IRQPOLL,
|
||||
.handler = at91rm9200_timer_interrupt,
|
||||
.irq = NR_IRQS_LEGACY + AT91_ID_SYS,
|
||||
};
|
||||
|
||||
static cycle_t read_clk32k(struct clocksource *cs)
|
||||
{
|
||||
return read_CRTR();
|
||||
@ -115,23 +109,25 @@ static struct clocksource clk32k = {
|
||||
static void
|
||||
clkevt32k_mode(enum clock_event_mode mode, struct clock_event_device *dev)
|
||||
{
|
||||
unsigned int val;
|
||||
|
||||
/* Disable and flush pending timer interrupts */
|
||||
at91_st_write(AT91_ST_IDR, AT91_ST_PITS | AT91_ST_ALMS);
|
||||
at91_st_read(AT91_ST_SR);
|
||||
regmap_write(regmap_st, AT91_ST_IDR, AT91_ST_PITS | AT91_ST_ALMS);
|
||||
regmap_read(regmap_st, AT91_ST_SR, &val);
|
||||
|
||||
last_crtr = read_CRTR();
|
||||
switch (mode) {
|
||||
case CLOCK_EVT_MODE_PERIODIC:
|
||||
/* PIT for periodic irqs; fixed rate of 1/HZ */
|
||||
irqmask = AT91_ST_PITS;
|
||||
at91_st_write(AT91_ST_PIMR, RM9200_TIMER_LATCH);
|
||||
regmap_write(regmap_st, AT91_ST_PIMR, RM9200_TIMER_LATCH);
|
||||
break;
|
||||
case CLOCK_EVT_MODE_ONESHOT:
|
||||
/* ALM for oneshot irqs, set by next_event()
|
||||
* before 32 seconds have passed
|
||||
*/
|
||||
irqmask = AT91_ST_ALMS;
|
||||
at91_st_write(AT91_ST_RTAR, last_crtr);
|
||||
regmap_write(regmap_st, AT91_ST_RTAR, last_crtr);
|
||||
break;
|
||||
case CLOCK_EVT_MODE_SHUTDOWN:
|
||||
case CLOCK_EVT_MODE_UNUSED:
|
||||
@ -139,7 +135,7 @@ clkevt32k_mode(enum clock_event_mode mode, struct clock_event_device *dev)
|
||||
irqmask = 0;
|
||||
break;
|
||||
}
|
||||
at91_st_write(AT91_ST_IER, irqmask);
|
||||
regmap_write(regmap_st, AT91_ST_IER, irqmask);
|
||||
}
|
||||
|
||||
static int
|
||||
@ -147,6 +143,7 @@ clkevt32k_next_event(unsigned long delta, struct clock_event_device *dev)
|
||||
{
|
||||
u32 alm;
|
||||
int status = 0;
|
||||
unsigned int val;
|
||||
|
||||
BUG_ON(delta < 2);
|
||||
|
||||
@ -162,12 +159,12 @@ clkevt32k_next_event(unsigned long delta, struct clock_event_device *dev)
|
||||
alm = read_CRTR();
|
||||
|
||||
/* Cancel any pending alarm; flush any pending IRQ */
|
||||
at91_st_write(AT91_ST_RTAR, alm);
|
||||
at91_st_read(AT91_ST_SR);
|
||||
regmap_write(regmap_st, AT91_ST_RTAR, alm);
|
||||
regmap_read(regmap_st, AT91_ST_SR, &val);
|
||||
|
||||
/* Schedule alarm by writing RTAR. */
|
||||
alm += delta;
|
||||
at91_st_write(AT91_ST_RTAR, alm);
|
||||
regmap_write(regmap_st, AT91_ST_RTAR, alm);
|
||||
|
||||
return status;
|
||||
}
|
||||
@ -180,66 +177,40 @@ static struct clock_event_device clkevt = {
|
||||
.set_mode = clkevt32k_mode,
|
||||
};
|
||||
|
||||
void __iomem *at91_st_base;
|
||||
EXPORT_SYMBOL_GPL(at91_st_base);
|
||||
|
||||
static const struct of_device_id at91rm9200_st_timer_ids[] = {
|
||||
{ .compatible = "atmel,at91rm9200-st" },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
static int __init of_at91rm9200_st_init(void)
|
||||
{
|
||||
struct device_node *np;
|
||||
int ret;
|
||||
|
||||
np = of_find_matching_node(NULL, at91rm9200_st_timer_ids);
|
||||
if (!np)
|
||||
goto err;
|
||||
|
||||
at91_st_base = of_iomap(np, 0);
|
||||
if (!at91_st_base)
|
||||
goto node_err;
|
||||
|
||||
/* Get the interrupts property */
|
||||
ret = irq_of_parse_and_map(np, 0);
|
||||
if (!ret)
|
||||
goto ioremap_err;
|
||||
at91rm9200_timer_irq.irq = ret;
|
||||
|
||||
of_node_put(np);
|
||||
|
||||
return 0;
|
||||
|
||||
ioremap_err:
|
||||
iounmap(at91_st_base);
|
||||
node_err:
|
||||
of_node_put(np);
|
||||
err:
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/*
|
||||
* ST (system timer) module supports both clockevents and clocksource.
|
||||
*/
|
||||
void __init at91rm9200_timer_init(void)
|
||||
static void __init atmel_st_timer_init(struct device_node *node)
|
||||
{
|
||||
/* For device tree enabled device: initialize here */
|
||||
of_at91rm9200_st_init();
|
||||
unsigned int val;
|
||||
int irq, ret;
|
||||
|
||||
regmap_st = syscon_node_to_regmap(node);
|
||||
if (IS_ERR(regmap_st))
|
||||
panic(pr_fmt("Unable to get regmap\n"));
|
||||
|
||||
/* Disable all timer interrupts, and clear any pending ones */
|
||||
at91_st_write(AT91_ST_IDR,
|
||||
regmap_write(regmap_st, AT91_ST_IDR,
|
||||
AT91_ST_PITS | AT91_ST_WDOVF | AT91_ST_RTTINC | AT91_ST_ALMS);
|
||||
at91_st_read(AT91_ST_SR);
|
||||
regmap_read(regmap_st, AT91_ST_SR, &val);
|
||||
|
||||
/* Get the interrupts property */
|
||||
irq = irq_of_parse_and_map(node, 0);
|
||||
if (!irq)
|
||||
panic(pr_fmt("Unable to get IRQ from DT\n"));
|
||||
|
||||
/* Make IRQs happen for the system timer */
|
||||
setup_irq(at91rm9200_timer_irq.irq, &at91rm9200_timer_irq);
|
||||
ret = request_irq(irq, at91rm9200_timer_interrupt,
|
||||
IRQF_SHARED | IRQF_TIMER | IRQF_IRQPOLL,
|
||||
"at91_tick", regmap_st);
|
||||
if (ret)
|
||||
panic(pr_fmt("Unable to setup IRQ\n"));
|
||||
|
||||
/* The 32KiHz "Slow Clock" (tick every 30517.58 nanoseconds) is used
|
||||
* directly for the clocksource and all clockevents, after adjusting
|
||||
* its prescaler from the 1 Hz default.
|
||||
*/
|
||||
at91_st_write(AT91_ST_RTMR, 1);
|
||||
regmap_write(regmap_st, AT91_ST_RTMR, 1);
|
||||
|
||||
/* Setup timer clockevent, with minimum of two ticks (important!!) */
|
||||
clkevt.cpumask = cpumask_of(0);
|
||||
@ -249,3 +220,5 @@ void __init at91rm9200_timer_init(void)
|
||||
/* register clocksource */
|
||||
clocksource_register_hz(&clk32k, AT91_SLOW_CLOCK);
|
||||
}
|
||||
CLOCKSOURCE_OF_DECLARE(atmel_st_timer, "atmel,at91rm9200-st",
|
||||
atmel_st_timer_init);
|
||||
@ -278,6 +278,7 @@ config BFIN_CFPCMCIA
|
||||
|
||||
config AT91_CF
|
||||
tristate "AT91 CompactFlash Controller"
|
||||
depends on PCI
|
||||
depends on PCMCIA && ARCH_AT91
|
||||
depends on !ARCH_MULTIPLATFORM
|
||||
help
|
||||
|
||||
@ -317,13 +317,14 @@ static int at91_cf_probe(struct platform_device *pdev)
|
||||
} else
|
||||
cf->socket.pci_irq = nr_irqs + 1;
|
||||
|
||||
/* pcmcia layer only remaps "real" memory not iospace */
|
||||
cf->socket.io_offset = (unsigned long) devm_ioremap(&pdev->dev,
|
||||
cf->phys_baseaddr + CF_IO_PHYS, SZ_2K);
|
||||
if (!cf->socket.io_offset) {
|
||||
status = -ENXIO;
|
||||
/*
|
||||
* pcmcia layer only remaps "real" memory not iospace
|
||||
* io_offset is set to 0x10000 to avoid the check in static_find_io().
|
||||
* */
|
||||
cf->socket.io_offset = 0x10000;
|
||||
status = pci_ioremap_io(0x10000, cf->phys_baseaddr + CF_IO_PHYS);
|
||||
if (status)
|
||||
goto fail0a;
|
||||
}
|
||||
|
||||
/* reserve chip-select regions */
|
||||
if (!devm_request_mem_region(&pdev->dev, io->start, resource_size(io), "at91_cf")) {
|
||||
|
||||
@ -154,7 +154,7 @@ config ARM_SP805_WATCHDOG
|
||||
|
||||
config AT91RM9200_WATCHDOG
|
||||
tristate "AT91RM9200 watchdog"
|
||||
depends on SOC_AT91RM9200
|
||||
depends on SOC_AT91RM9200 && MFD_SYSCON
|
||||
help
|
||||
Watchdog timer embedded into AT91RM9200 chips. This will reboot your
|
||||
system when the timeout is reached.
|
||||
|
||||
@ -12,27 +12,32 @@
|
||||
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
|
||||
|
||||
#include <linux/bitops.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/errno.h>
|
||||
#include <linux/fs.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/mfd/syscon.h>
|
||||
#include <linux/mfd/syscon/atmel-st.h>
|
||||
#include <linux/miscdevice.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/moduleparam.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/reboot.h>
|
||||
#include <linux/regmap.h>
|
||||
#include <linux/types.h>
|
||||
#include <linux/watchdog.h>
|
||||
#include <linux/uaccess.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_device.h>
|
||||
#include <mach/at91_st.h>
|
||||
|
||||
#define WDT_DEFAULT_TIME 5 /* seconds */
|
||||
#define WDT_MAX_TIME 256 /* seconds */
|
||||
|
||||
static int wdt_time = WDT_DEFAULT_TIME;
|
||||
static bool nowayout = WATCHDOG_NOWAYOUT;
|
||||
static struct regmap *regmap_st;
|
||||
|
||||
module_param(wdt_time, int, 0);
|
||||
MODULE_PARM_DESC(wdt_time, "Watchdog time in seconds. (default="
|
||||
@ -50,12 +55,33 @@ static unsigned long at91wdt_busy;
|
||||
|
||||
/* ......................................................................... */
|
||||
|
||||
static int at91rm9200_restart(struct notifier_block *this,
|
||||
unsigned long mode, void *cmd)
|
||||
{
|
||||
/*
|
||||
* Perform a hardware reset with the use of the Watchdog timer.
|
||||
*/
|
||||
regmap_write(regmap_st, AT91_ST_WDMR,
|
||||
AT91_ST_RSTEN | AT91_ST_EXTEN | 1);
|
||||
regmap_write(regmap_st, AT91_ST_CR, AT91_ST_WDRST);
|
||||
|
||||
mdelay(2000);
|
||||
|
||||
pr_emerg("Unable to restart system\n");
|
||||
return NOTIFY_DONE;
|
||||
}
|
||||
|
||||
static struct notifier_block at91rm9200_restart_nb = {
|
||||
.notifier_call = at91rm9200_restart,
|
||||
.priority = 192,
|
||||
};
|
||||
|
||||
/*
|
||||
* Disable the watchdog.
|
||||
*/
|
||||
static inline void at91_wdt_stop(void)
|
||||
{
|
||||
at91_st_write(AT91_ST_WDMR, AT91_ST_EXTEN);
|
||||
regmap_write(regmap_st, AT91_ST_WDMR, AT91_ST_EXTEN);
|
||||
}
|
||||
|
||||
/*
|
||||
@ -63,9 +89,9 @@ static inline void at91_wdt_stop(void)
|
||||
*/
|
||||
static inline void at91_wdt_start(void)
|
||||
{
|
||||
at91_st_write(AT91_ST_WDMR, AT91_ST_EXTEN | AT91_ST_RSTEN |
|
||||
regmap_write(regmap_st, AT91_ST_WDMR, AT91_ST_EXTEN | AT91_ST_RSTEN |
|
||||
(((65536 * wdt_time) >> 8) & AT91_ST_WDV));
|
||||
at91_st_write(AT91_ST_CR, AT91_ST_WDRST);
|
||||
regmap_write(regmap_st, AT91_ST_CR, AT91_ST_WDRST);
|
||||
}
|
||||
|
||||
/*
|
||||
@ -73,7 +99,7 @@ static inline void at91_wdt_start(void)
|
||||
*/
|
||||
static inline void at91_wdt_reload(void)
|
||||
{
|
||||
at91_st_write(AT91_ST_CR, AT91_ST_WDRST);
|
||||
regmap_write(regmap_st, AT91_ST_CR, AT91_ST_WDRST);
|
||||
}
|
||||
|
||||
/* ......................................................................... */
|
||||
@ -203,16 +229,32 @@ static struct miscdevice at91wdt_miscdev = {
|
||||
|
||||
static int at91wdt_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct device *parent;
|
||||
int res;
|
||||
|
||||
if (at91wdt_miscdev.parent)
|
||||
return -EBUSY;
|
||||
at91wdt_miscdev.parent = &pdev->dev;
|
||||
|
||||
parent = dev->parent;
|
||||
if (!parent) {
|
||||
dev_err(dev, "no parent\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
regmap_st = syscon_node_to_regmap(parent->of_node);
|
||||
if (!regmap_st)
|
||||
return -ENODEV;
|
||||
|
||||
res = misc_register(&at91wdt_miscdev);
|
||||
if (res)
|
||||
return res;
|
||||
|
||||
res = register_restart_handler(&at91rm9200_restart_nb);
|
||||
if (res)
|
||||
dev_warn(dev, "failed to register restart handler\n");
|
||||
|
||||
pr_info("AT91 Watchdog Timer enabled (%d seconds%s)\n",
|
||||
wdt_time, nowayout ? ", nowayout" : "");
|
||||
return 0;
|
||||
@ -220,8 +262,13 @@ static int at91wdt_probe(struct platform_device *pdev)
|
||||
|
||||
static int at91wdt_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
int res;
|
||||
|
||||
res = unregister_restart_handler(&at91rm9200_restart_nb);
|
||||
if (res)
|
||||
dev_warn(dev, "failed to unregister restart handler\n");
|
||||
|
||||
res = misc_deregister(&at91wdt_miscdev);
|
||||
if (!res)
|
||||
at91wdt_miscdev.parent = NULL;
|
||||
@ -267,7 +314,7 @@ static struct platform_driver at91wdt_driver = {
|
||||
.suspend = at91wdt_suspend,
|
||||
.resume = at91wdt_resume,
|
||||
.driver = {
|
||||
.name = "at91_wdt",
|
||||
.name = "atmel_st_watchdog",
|
||||
.of_match_table = at91_wdt_dt_ids,
|
||||
},
|
||||
};
|
||||
@ -296,4 +343,4 @@ module_exit(at91_wdt_exit);
|
||||
MODULE_AUTHOR("Andrew Victor");
|
||||
MODULE_DESCRIPTION("Watchdog driver for Atmel AT91RM9200");
|
||||
MODULE_LICENSE("GPL");
|
||||
MODULE_ALIAS("platform:at91_wdt");
|
||||
MODULE_ALIAS("platform:atmel_st_watchdog");
|
||||
|
||||
49
include/linux/mfd/syscon/atmel-st.h
Normal file
49
include/linux/mfd/syscon/atmel-st.h
Normal file
@ -0,0 +1,49 @@
|
||||
/*
|
||||
* Copyright (C) 2005 Ivan Kokshaysky
|
||||
* Copyright (C) SAN People
|
||||
*
|
||||
* System Timer (ST) - System peripherals registers.
|
||||
* Based on AT91RM9200 datasheet revision E.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*/
|
||||
|
||||
#ifndef _LINUX_MFD_SYSCON_ATMEL_ST_H
|
||||
#define _LINUX_MFD_SYSCON_ATMEL_ST_H
|
||||
|
||||
#include <linux/bitops.h>
|
||||
|
||||
#define AT91_ST_CR 0x00 /* Control Register */
|
||||
#define AT91_ST_WDRST BIT(0) /* Watchdog Timer Restart */
|
||||
|
||||
#define AT91_ST_PIMR 0x04 /* Period Interval Mode Register */
|
||||
#define AT91_ST_PIV 0xffff /* Period Interval Value */
|
||||
|
||||
#define AT91_ST_WDMR 0x08 /* Watchdog Mode Register */
|
||||
#define AT91_ST_WDV 0xffff /* Watchdog Counter Value */
|
||||
#define AT91_ST_RSTEN BIT(16) /* Reset Enable */
|
||||
#define AT91_ST_EXTEN BIT(17) /* External Signal Assertion Enable */
|
||||
|
||||
#define AT91_ST_RTMR 0x0c /* Real-time Mode Register */
|
||||
#define AT91_ST_RTPRES 0xffff /* Real-time Prescalar Value */
|
||||
|
||||
#define AT91_ST_SR 0x10 /* Status Register */
|
||||
#define AT91_ST_PITS BIT(0) /* Period Interval Timer Status */
|
||||
#define AT91_ST_WDOVF BIT(1) /* Watchdog Overflow */
|
||||
#define AT91_ST_RTTINC BIT(2) /* Real-time Timer Increment */
|
||||
#define AT91_ST_ALMS BIT(3) /* Alarm Status */
|
||||
|
||||
#define AT91_ST_IER 0x14 /* Interrupt Enable Register */
|
||||
#define AT91_ST_IDR 0x18 /* Interrupt Disable Register */
|
||||
#define AT91_ST_IMR 0x1c /* Interrupt Mask Register */
|
||||
|
||||
#define AT91_ST_RTAR 0x20 /* Real-time Alarm Register */
|
||||
#define AT91_ST_ALMV 0xfffff /* Alarm Value */
|
||||
|
||||
#define AT91_ST_CRTR 0x24 /* Current Real-time Register */
|
||||
#define AT91_ST_CRTV 0xfffff /* Current Real-Time Value */
|
||||
|
||||
#endif /* _LINUX_MFD_SYSCON_ATMEL_ST_H */
|
||||
@ -92,7 +92,7 @@
|
||||
#define AT91_DDRSDRC_UPD_MR (3 << 20) /* Update load mode register and extended mode register */
|
||||
|
||||
#define AT91_DDRSDRC_MDR 0x20 /* Memory Device Register */
|
||||
#define AT91_DDRSDRC_MD (3 << 0) /* Memory Device Type */
|
||||
#define AT91_DDRSDRC_MD (7 << 0) /* Memory Device Type */
|
||||
#define AT91_DDRSDRC_MD_SDR 0
|
||||
#define AT91_DDRSDRC_MD_LOW_POWER_SDR 1
|
||||
#define AT91_DDRSDRC_MD_LOW_POWER_DDR 3
|
||||
|
||||
Loading…
Reference in New Issue
Block a user