mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-23 08:02:37 +07:00
arm64: zynqmp: Add support for Xilinx zcu100-revC
This board has 2GB of memory, i2c, sd, wifi sdio, spis, uarts, display port and usbs. Board is using fixed clocks because clock driver hasn't been merged yet. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Rob Herring <robh@kernel.org>
This commit is contained in:
Michal Simek
parent
a7a16068ad
commit
5869ba0653
@ -15,3 +15,9 @@ shall have the following properties.
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Required root node properties:
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- compatible = "xlnx,zynqmp";
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Additional compatible strings:
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- Xilinx 96boards compatible board zcu100
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"xlnx,zynqmp-zcu100-revC", "xlnx,zynqmp-zcu100"
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@ -1,2 +1,3 @@
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# SPDX-License-Identifier: GPL-2.0
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dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-ep108.dtb
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dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu100-revC.dtb
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213
arch/arm64/boot/dts/xilinx/zynqmp-clk.dtsi
Normal file
213
arch/arm64/boot/dts/xilinx/zynqmp-clk.dtsi
Normal file
@ -0,0 +1,213 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Clock specification for Xilinx ZynqMP
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*
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* (C) Copyright 2015 - 2018, Xilinx, Inc.
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*
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* Michal Simek <michal.simek@xilinx.com>
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*/
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/ {
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clk100: clk100 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <100000000>;
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};
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clk125: clk125 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <125000000>;
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};
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clk200: clk200 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <200000000>;
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};
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clk250: clk250 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <250000000>;
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};
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clk300: clk300 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <300000000>;
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};
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clk600: clk600 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <600000000>;
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};
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dp_aclk: clock0 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <100000000>;
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clock-accuracy = <100>;
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};
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dp_aud_clk: clock1 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <24576000>;
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clock-accuracy = <100>;
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};
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dpdma_clk: dpdma_clk {
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compatible = "fixed-clock";
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#clock-cells = <0x0>;
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clock-frequency = <533000000>;
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};
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drm_clock: drm_clock {
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compatible = "fixed-clock";
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#clock-cells = <0x0>;
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clock-frequency = <262750000>;
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clock-accuracy = <0x64>;
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};
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};
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&can0 {
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clocks = <&clk100 &clk100>;
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};
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&can1 {
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clocks = <&clk100 &clk100>;
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};
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&fpd_dma_chan1 {
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clocks = <&clk600>, <&clk100>;
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};
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&fpd_dma_chan2 {
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clocks = <&clk600>, <&clk100>;
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};
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&fpd_dma_chan3 {
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clocks = <&clk600>, <&clk100>;
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};
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&fpd_dma_chan4 {
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clocks = <&clk600>, <&clk100>;
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};
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&fpd_dma_chan5 {
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clocks = <&clk600>, <&clk100>;
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};
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&fpd_dma_chan6 {
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clocks = <&clk600>, <&clk100>;
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};
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&fpd_dma_chan7 {
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clocks = <&clk600>, <&clk100>;
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};
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&fpd_dma_chan8 {
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clocks = <&clk600>, <&clk100>;
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};
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&lpd_dma_chan1 {
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clocks = <&clk600>, <&clk100>;
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};
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&lpd_dma_chan2 {
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clocks = <&clk600>, <&clk100>;
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};
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&lpd_dma_chan3 {
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clocks = <&clk600>, <&clk100>;
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};
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&lpd_dma_chan4 {
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clocks = <&clk600>, <&clk100>;
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};
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&lpd_dma_chan5 {
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clocks = <&clk600>, <&clk100>;
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};
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&lpd_dma_chan6 {
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clocks = <&clk600>, <&clk100>;
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};
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&lpd_dma_chan7 {
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clocks = <&clk600>, <&clk100>;
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};
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&lpd_dma_chan8 {
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clocks = <&clk600>, <&clk100>;
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};
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&gem0 {
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clocks = <&clk125>, <&clk125>, <&clk125>;
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};
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&gem1 {
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clocks = <&clk125>, <&clk125>, <&clk125>;
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};
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&gem2 {
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clocks = <&clk125>, <&clk125>, <&clk125>;
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};
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&gem3 {
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clocks = <&clk125>, <&clk125>, <&clk125>;
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};
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&gpio {
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clocks = <&clk100>;
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};
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&i2c0 {
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clocks = <&clk100>;
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};
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&i2c1 {
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clocks = <&clk100>;
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};
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&sata {
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clocks = <&clk250>;
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};
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&sdhci0 {
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clocks = <&clk200 &clk200>;
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};
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&sdhci1 {
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clocks = <&clk200 &clk200>;
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};
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&spi0 {
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clocks = <&clk200 &clk200>;
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};
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&spi1 {
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clocks = <&clk200 &clk200>;
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};
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&uart0 {
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clocks = <&clk100 &clk100>;
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};
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&uart1 {
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clocks = <&clk100 &clk100>;
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};
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&usb0 {
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clocks = <&clk250>, <&clk250>;
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};
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&usb1 {
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clocks = <&clk250>, <&clk250>;
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};
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&watchdog0 {
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clocks = <&clk250>;
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};
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289
arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts
Normal file
289
arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts
Normal file
@ -0,0 +1,289 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* dts file for Xilinx ZynqMP ZCU100 revC
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*
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* (C) Copyright 2016 - 2018, Xilinx, Inc.
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*
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* Michal Simek <michal.simek@xilinx.com>
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* Nathalie Chan King Choy
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*/
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/dts-v1/;
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#include "zynqmp.dtsi"
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#include "zynqmp-clk.dtsi"
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/gpio/gpio.h>
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/ {
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model = "ZynqMP ZCU100 RevC";
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compatible = "xlnx,zynqmp-zcu100-revC", "xlnx,zynqmp-zcu100", "xlnx,zynqmp";
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aliases {
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i2c0 = &i2c1;
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rtc0 = &rtc;
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serial0 = &uart1;
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serial1 = &uart0;
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serial2 = &dcc;
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spi0 = &spi0;
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spi1 = &spi1;
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mmc0 = &sdhci0;
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mmc1 = &sdhci1;
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};
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chosen {
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bootargs = "earlycon";
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stdout-path = "serial0:115200n8";
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};
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memory@0 {
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device_type = "memory";
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reg = <0x0 0x0 0x0 0x80000000>;
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};
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gpio-keys {
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compatible = "gpio-keys";
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#address-cells = <1>;
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#size-cells = <0>;
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autorepeat;
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sw4 {
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label = "sw4";
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gpios = <&gpio 23 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_POWER>;
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gpio-key,wakeup;
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autorepeat;
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};
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};
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leds {
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compatible = "gpio-leds";
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ds2 {
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label = "ds2";
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gpios = <&gpio 20 GPIO_ACTIVE_HIGH>;
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linux,default-trigger = "heartbeat";
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};
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ds3 {
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label = "ds3";
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gpios = <&gpio 19 GPIO_ACTIVE_HIGH>;
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linux,default-trigger = "phy0tx"; /* WLAN tx */
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default-state = "off";
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};
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ds4 {
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label = "ds4";
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gpios = <&gpio 18 GPIO_ACTIVE_HIGH>;
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linux,default-trigger = "phy0rx"; /* WLAN rx */
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default-state = "off";
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};
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ds5 {
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label = "ds5";
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gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
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linux,default-trigger = "bluetooth-power";
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};
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vbus_det { /* U5 USB5744 VBUS detection via MIO25 */
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label = "vbus_det";
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gpios = <&gpio 25 GPIO_ACTIVE_HIGH>;
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default-state = "on";
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};
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bt_power {
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label = "bt_power";
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gpios = <&gpio 8 GPIO_ACTIVE_HIGH>;
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default-state = "on";
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};
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};
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wmmcsdio_fixed: fixedregulator-mmcsdio {
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compatible = "regulator-fixed";
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regulator-name = "wmmcsdio_fixed";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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regulator-boot-on;
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};
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sdio_pwrseq: sdio_pwrseq {
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compatible = "mmc-pwrseq-simple";
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reset-gpios = <&gpio 7 GPIO_ACTIVE_LOW>; /* WIFI_EN */
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};
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};
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&dcc {
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status = "okay";
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};
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&gpio {
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status = "okay";
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gpio-line-names = "UART1_TX", "UART1_RX", "UART0_RX", "UART0_TX", "I2C1_SCL",
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"I2C1_SDA", "SPI1_SCLK", "WLAN_EN", "BT_EN", "SPI1_CS",
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"SPI1_MISO", "SPI1_MOSI", "I2C_MUX_RESET", "SD0_DAT0", "SD0_DAT1",
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"SD0_DAT2", "SD0_DAT3", "PS_LED3", "PS_LED2", "PS_LED1",
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"PS_LED0", "SD0_CMD", "SD0_CLK", "GPIO_PB", "SD0_DETECT",
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"VBUS_DET", "POWER_INT", "DP_AUX", "DP_HPD", "DP_OE",
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"DP_AUX_IN", "INA226_ALERT", "PS_FP_PWR_EN", "PL_PWR_EN", "POWER_KILL",
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"", "GPIO-A", "GPIO-B", "SPI0_SCLK", "GPIO-C",
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"GPIO-D", "SPI0_CS", "SPI0_MISO", "SPI_MOSI", "GPIO-E",
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"GPIO-F", "SD1_D0", "SD1_D1", "SD1_D2", "SD1_D3",
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"SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2",
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"USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3",
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"USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK",
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"USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1",
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"USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6",
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"USB_DATA7", "WLAN_IRQ", "PMIC_IRQ", /* MIO end and EMIO start */
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"", "",
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"", "", "", "", "", "", "", "", "", "",
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"", "", "", "", "", "", "", "", "", "",
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"", "", "", "", "", "", "", "", "", "",
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"", "", "", "", "", "", "", "", "", "",
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"", "", "", "", "", "", "", "", "", "",
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"", "", "", "", "", "", "", "", "", "",
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"", "", "", "", "", "", "", "", "", "",
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"", "", "", "", "", "", "", "", "", "",
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"", "", "", "", "", "", "", "", "", "",
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"", "", "", "";
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};
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&i2c1 {
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status = "okay";
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clock-frequency = <100000>;
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i2c-mux@75 { /* u11 */
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compatible = "nxp,pca9548";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x75>;
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i2csw_0: i2c@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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label = "LS-I2C0";
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};
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i2csw_1: i2c@1 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <1>;
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label = "LS-I2C1";
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};
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i2csw_2: i2c@2 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <2>;
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label = "HS-I2C2";
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};
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i2csw_3: i2c@3 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <3>;
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label = "HS-I2C3";
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};
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i2csw_4: i2c@4 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x4>;
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pmic: pmic@5e { /* Custom TI PMIC u33 */
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compatible = "ti,tps65086";
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reg = <0x5e>;
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interrupt-parent = <&gpio>;
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interrupts = <77 GPIO_ACTIVE_LOW>;
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#gpio-cells = <2>;
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gpio-controller;
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};
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};
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i2csw_5: i2c@5 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <5>;
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/* PS_PMBUS */
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ina226@40 { /* u35 */
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compatible = "ti,ina226";
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reg = <0x40>;
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shunt-resistor = <10000>;
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/* MIO31 is alert which should be routed to PMUFW */
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};
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};
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i2csw_6: i2c@6 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <6>;
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/*
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* Not Connected
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*/
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};
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i2csw_7: i2c@7 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <7>;
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/*
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* usb5744 (DNP) - U5
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* 100kHz - this is default freq for us
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*/
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};
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};
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};
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&rtc {
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status = "okay";
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};
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/* SD0 only supports 3.3V, no level shifter */
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&sdhci0 {
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status = "okay";
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no-1-8-v;
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broken-cd; /* CD has to be enabled by default */
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disable-wp;
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};
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&sdhci1 {
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status = "okay";
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bus-width = <0x4>;
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non-removable;
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disable-wp;
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cap-power-off-card;
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mmc-pwrseq = <&sdio_pwrseq>;
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vqmmc-supply = <&wmmcsdio_fixed>;
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#address-cells = <1>;
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#size-cells = <0>;
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wlcore: wifi@2 {
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compatible = "ti,wl1831";
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reg = <2>;
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interrupt-parent = <&gpio>;
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interrupts = <76 IRQ_TYPE_EDGE_RISING>; /* MIO76 WLAN_IRQ 1V8 */
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};
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};
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&spi0 { /* Low Speed connector */
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status = "okay";
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label = "LS-SPI0";
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};
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&spi1 { /* High Speed connector */
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status = "okay";
|
||||
label = "HS-SPI1";
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
status = "okay";
|
||||
|
||||
};
|
||||
|
||||
/* ULPI SMSC USB3320 */
|
||||
&usb0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* ULPI SMSC USB3320 */
|
||||
&usb1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&watchdog0 {
|
||||
status = "okay";
|
||||
};
|
||||
Loading…
Reference in New Issue
Block a user