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drm/amd/display: cleanup naming of DCN DPP functions

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Signed-off-by: Yue Hin Lau <Yuehin.Lau@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Yue Hin Lau 2017-08-19 12:10:28 -04:00 committed by Alex Deucher
parent b823defeb7
commit 58314e5812
4 changed files with 48 additions and 40 deletions
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41
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
View File

@ -123,7 +123,7 @@ void dpp_set_gamut_remap_bypass(struct dcn10_dpp *xfm)
#define IDENTITY_RATIO(ratio) (dal_fixed31_32_u2d19(ratio) == (1 << 19))
static bool dpp_get_optimal_number_of_taps(
bool dpp_get_optimal_number_of_taps(
struct transform *xfm,
struct scaler_data *scl_data,
const struct scaling_taps *in_taps)
@ -182,7 +182,7 @@ static bool dpp_get_optimal_number_of_taps(
return true;
}
static void dpp_reset(struct transform *xfm_base)
void dpp_reset(struct transform *xfm_base)
{
struct dcn10_dpp *xfm = TO_DCN10_DPP(xfm_base);
@ -197,26 +197,26 @@ static void dpp_reset(struct transform *xfm_base)
static bool oppn10_set_regamma_pwl(
static bool dcn10_dpp_cm_set_regamma_pwl(
struct transform *xfm_base, const struct pwl_params *params)
{
struct dcn10_dpp *xfm = TO_DCN10_DPP(xfm_base);
oppn10_power_on_regamma_lut(xfm_base, true);
opp_configure_regamma_lut(xfm_base, xfm->is_write_to_ram_a_safe);
dcn10_dpp_cm_power_on_regamma_lut(xfm_base, true);
dcn10_dpp_cm_configure_regamma_lut(xfm_base, xfm->is_write_to_ram_a_safe);
if (xfm->is_write_to_ram_a_safe)
opp_program_regamma_luta_settings(xfm_base, params);
dcn10_dpp_cm_program_regamma_luta_settings(xfm_base, params);
else
opp_program_regamma_lutb_settings(xfm_base, params);
dcn10_dpp_cm_program_regamma_lutb_settings(xfm_base, params);
opp_program_regamma_lut(
dcn10_dpp_cm_program_regamma_lut(
xfm_base, params->rgb_resulted, params->hw_points_num);
return true;
}
static void oppn10_set_regamma_mode(
static void dcn10_dpp_cm_set_regamma_mode(
struct transform *xfm_base,
enum opp_regamma mode)
{
@ -251,20 +251,21 @@ static void oppn10_set_regamma_mode(
static struct transform_funcs dcn10_dpp_funcs = {
.transform_reset = dpp_reset,
.transform_set_scaler = dcn10_dpp_set_scaler_manual_scale,
.transform_set_scaler = dcn10_dpp_dscl_set_scaler_manual_scale,
.transform_get_optimal_number_of_taps = dpp_get_optimal_number_of_taps,
.transform_set_gamut_remap = dcn_dpp_set_gamut_remap,
.opp_set_csc_adjustment = oppn10_set_output_csc_adjustment,
.opp_set_csc_default = oppn10_set_output_csc_default,
.opp_power_on_regamma_lut = oppn10_power_on_regamma_lut,
.opp_program_regamma_lut = opp_program_regamma_lut,
.opp_configure_regamma_lut = opp_configure_regamma_lut,
.opp_program_regamma_lutb_settings = opp_program_regamma_lutb_settings,
.opp_program_regamma_luta_settings = opp_program_regamma_luta_settings,
.opp_program_regamma_pwl = oppn10_set_regamma_pwl,
.opp_set_regamma_mode = oppn10_set_regamma_mode,
.transform_set_gamut_remap = dcn10_dpp_cm_set_gamut_remap,
.opp_set_csc_adjustment = dcn10_dpp_cm_set_output_csc_adjustment,
.opp_set_csc_default = dcn10_dpp_cm_set_output_csc_default,
.opp_power_on_regamma_lut = dcn10_dpp_cm_power_on_regamma_lut,
.opp_program_regamma_lut = dcn10_dpp_cm_program_regamma_lut,
.opp_configure_regamma_lut = dcn10_dpp_cm_configure_regamma_lut,
.opp_program_regamma_lutb_settings = dcn10_dpp_cm_program_regamma_lutb_settings,
.opp_program_regamma_luta_settings = dcn10_dpp_cm_program_regamma_luta_settings,
.opp_program_regamma_pwl = dcn10_dpp_cm_set_regamma_pwl,
.opp_set_regamma_mode = dcn10_dpp_cm_set_regamma_mode,
};
/*****************************************/
/* Constructor, Destructor */
/*****************************************/

25
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h
View File

@ -1387,41 +1387,48 @@ struct dcn10_dpp {
bool is_write_to_ram_a_safe;
};
void opp_program_regamma_lut(
bool dpp_get_optimal_number_of_taps(
struct transform *xfm,
struct scaler_data *scl_data,
const struct scaling_taps *in_taps);
void dpp_reset(struct transform *xfm_base);
void dcn10_dpp_cm_program_regamma_lut(
struct transform *xfm_base,
const struct pwl_result_data *rgb,
uint32_t num);
void oppn10_power_on_regamma_lut(
void dcn10_dpp_cm_power_on_regamma_lut(
struct transform *xfm_base,
bool power_on);
void opp_configure_regamma_lut(
void dcn10_dpp_cm_configure_regamma_lut(
struct transform *xfm_base,
bool is_ram_a);
/*program re gamma RAM A*/
void opp_program_regamma_luta_settings(
void dcn10_dpp_cm_program_regamma_luta_settings(
struct transform *xfm_base,
const struct pwl_params *params);
/*program re gamma RAM B*/
void opp_program_regamma_lutb_settings(
void dcn10_dpp_cm_program_regamma_lutb_settings(
struct transform *xfm_base,
const struct pwl_params *params);
void oppn10_set_output_csc_adjustment(
void dcn10_dpp_cm_set_output_csc_adjustment(
struct transform *xfm_base,
const struct out_csc_color_matrix *tbl_entry);
void oppn10_set_output_csc_default(
void dcn10_dpp_cm_set_output_csc_default(
struct transform *xfm_base,
const struct default_adjustment *default_adjust);
void dcn_dpp_set_gamut_remap(
void dcn10_dpp_cm_set_gamut_remap(
struct transform *xfm,
const struct xfm_grph_csc_adjustment *adjust);
void dcn10_dpp_set_scaler_manual_scale(
void dcn10_dpp_dscl_set_scaler_manual_scale(
struct transform *xfm_base,
const struct scaler_data *scl_data);

20
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
View File

@ -221,7 +221,7 @@ static void program_gamut_remap(
}
void dcn_dpp_set_gamut_remap(
void dcn10_dpp_cm_set_gamut_remap(
struct transform *xfm,
const struct xfm_grph_csc_adjustment *adjust)
{
@ -256,7 +256,7 @@ void dcn_dpp_set_gamut_remap(
}
}
void oppn10_set_output_csc_default(
void dcn10_dpp_cm_set_output_csc_default(
struct transform *xfm_base,
const struct default_adjustment *default_adjust)
{
@ -293,7 +293,7 @@ void oppn10_set_output_csc_default(
}
static void oppn10_program_color_matrix(
static void dcn10_dpp_cm_program_color_matrix(
struct dcn10_dpp *xfm,
const struct out_csc_color_matrix *tbl_entry)
{
@ -363,7 +363,7 @@ static void oppn10_program_color_matrix(
}
}
void oppn10_set_output_csc_adjustment(
void dcn10_dpp_cm_set_output_csc_adjustment(
struct transform *xfm_base,
const struct out_csc_color_matrix *tbl_entry)
{
@ -399,10 +399,10 @@ void oppn10_set_output_csc_adjustment(
*/
REG_SET(CM_OCSC_CONTROL, 0, CM_OCSC_MODE, ocsc_mode);
oppn10_program_color_matrix(xfm, tbl_entry);
dcn10_dpp_cm_program_color_matrix(xfm, tbl_entry);
}
void oppn10_power_on_regamma_lut(
void dcn10_dpp_cm_power_on_regamma_lut(
struct transform *xfm_base,
bool power_on)
{
@ -412,7 +412,7 @@ void oppn10_power_on_regamma_lut(
}
void opp_program_regamma_lut(
void dcn10_dpp_cm_program_regamma_lut(
struct transform *xfm_base,
const struct pwl_result_data *rgb,
uint32_t num)
@ -435,7 +435,7 @@ void opp_program_regamma_lut(
}
void opp_configure_regamma_lut(
void dcn10_dpp_cm_configure_regamma_lut(
struct transform *xfm_base,
bool is_ram_a)
{
@ -449,7 +449,7 @@ void opp_configure_regamma_lut(
}
/*program re gamma RAM A*/
void opp_program_regamma_luta_settings(
void dcn10_dpp_cm_program_regamma_luta_settings(
struct transform *xfm_base,
const struct pwl_params *params)
{
@ -612,7 +612,7 @@ void opp_program_regamma_luta_settings(
}
/*program re gamma RAM B*/
void opp_program_regamma_lutb_settings(
void dcn10_dpp_cm_program_regamma_lutb_settings(
struct transform *xfm_base,
const struct pwl_params *params)
{

2
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c
View File

@ -636,7 +636,7 @@ static void dpp_set_recout(
}
/* Main function to program scaler and line buffer in manual scaling mode */
void dcn10_dpp_set_scaler_manual_scale(
void dcn10_dpp_dscl_set_scaler_manual_scale(
struct transform *xfm_base,
const struct scaler_data *scl_data)
{