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drm/vc4: hdmi: Block odd horizontal timings
The FIFO between the pixelvalve and the HDMI controller runs at 2 pixels per clock cycle, and cannot deal with odd timings. Let's reject any mode with such timings. Signed-off-by: Maxime Ripard <maxime@cerno.tech> Reviewed-by: Dave Stevenson <dave.stevenson@raspberrypi.com> Link: https://patchwork.freedesktop.org/patch/msgid/20201029122522.1917579-2-maxime@cerno.tech
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@ -768,6 +768,11 @@ static int vc4_hdmi_encoder_atomic_check(struct drm_encoder *encoder,
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struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
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unsigned long long pixel_rate = mode->clock * 1000;
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if (vc4_hdmi->variant->unsupported_odd_h_timings &&
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((mode->hdisplay % 2) || (mode->hsync_start % 2) ||
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(mode->hsync_end % 2) || (mode->htotal % 2)))
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return -EINVAL;
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if (pixel_rate > vc4_hdmi->variant->max_pixel_clock)
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return -EINVAL;
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@ -780,6 +785,11 @@ vc4_hdmi_encoder_mode_valid(struct drm_encoder *encoder,
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{
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struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
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if (vc4_hdmi->variant->unsupported_odd_h_timings &&
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((mode->hdisplay % 2) || (mode->hsync_start % 2) ||
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(mode->hsync_end % 2) || (mode->htotal % 2)))
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return MODE_H_ILLEGAL;
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if ((mode->clock * 1000) > vc4_hdmi->variant->max_pixel_clock)
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return MODE_CLOCK_HIGH;
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@ -1832,6 +1842,7 @@ static const struct vc4_hdmi_variant bcm2711_hdmi0_variant = {
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PHY_LANE_2,
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PHY_LANE_CK,
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},
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.unsupported_odd_h_timings = true,
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.init_resources = vc5_hdmi_init_resources,
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.csc_setup = vc5_hdmi_csc_setup,
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@ -1857,6 +1868,7 @@ static const struct vc4_hdmi_variant bcm2711_hdmi1_variant = {
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PHY_LANE_CK,
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PHY_LANE_2,
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},
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.unsupported_odd_h_timings = true,
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.init_resources = vc5_hdmi_init_resources,
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.csc_setup = vc5_hdmi_csc_setup,
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@ -62,6 +62,9 @@ struct vc4_hdmi_variant {
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*/
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enum vc4_hdmi_phy_channel phy_lane_mapping[4];
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/* The BCM2711 cannot deal with odd horizontal pixel timings */
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bool unsupported_odd_h_timings;
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/* Callback to get the resources (memory region, interrupts,
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* clocks, etc) for that variant.
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*/
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