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ath9k_hw: Update ath9k_hw_set_dma for AR9300
Signed-off-by: Felix Fietkau <nbd@openwrt.org> Signed-off-by: John W. Linville <linville@tuxdriver.com>
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@ -836,13 +836,16 @@ u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan)
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static inline void ath9k_hw_set_dma(struct ath_hw *ah)
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{
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struct ath_common *common = ath9k_hw_common(ah);
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u32 regval;
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/*
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* set AHB_MODE not to do cacheline prefetches
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*/
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if (!AR_SREV_9300_20_OR_LATER(ah)) {
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regval = REG_READ(ah, AR_AHB_MODE);
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REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
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}
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/*
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* let mac dma reads be in 128 byte chunks
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@ -855,6 +858,7 @@ static inline void ath9k_hw_set_dma(struct ath_hw *ah)
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* The initial value depends on whether aggregation is enabled, and is
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* adjusted whenever underruns are detected.
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*/
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if (!AR_SREV_9300_20_OR_LATER(ah))
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REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
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/*
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@ -868,6 +872,14 @@ static inline void ath9k_hw_set_dma(struct ath_hw *ah)
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*/
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REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
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if (AR_SREV_9300_20_OR_LATER(ah)) {
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REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1);
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REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1);
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ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize -
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ah->caps.rx_status_len);
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}
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/*
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* reduce the number of usable entries in PCU TXBUF to avoid
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* wrap around issues.
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@ -39,6 +39,12 @@
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#define AR_CFG_PCI_MASTER_REQ_Q_THRESH 0x00060000
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#define AR_CFG_PCI_MASTER_REQ_Q_THRESH_S 17
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#define AR_RXBP_THRESH 0x0018
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#define AR_RXBP_THRESH_HP 0x0000000f
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#define AR_RXBP_THRESH_HP_S 0
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#define AR_RXBP_THRESH_LP 0x00003f00
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#define AR_RXBP_THRESH_LP_S 8
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#define AR_MIRT 0x0020
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#define AR_MIRT_VAL 0x0000ffff
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#define AR_MIRT_VAL_S 16
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