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drm/i915/intel_i2c: use INDEX cycles for i2c read transactions
It is very common for an i2c device to require a small 1 or 2 byte write followed by a read. For example, when reading from an i2c EEPROM it is common to write and address, offset or index followed by a reading some values. The i915 gmbus controller provides a special "INDEX" cycle for performing such a small write followed by a read. The INDEX can be either one or two bytes long. The advantage of using such a cycle is that the CPU has slightly less work to do once the read with INDEX cycle is started. Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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@ -204,13 +204,15 @@ intel_gpio_setup(struct intel_gmbus *bus, u32 pin)
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}
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static int
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gmbus_xfer_read(struct drm_i915_private *dev_priv, struct i2c_msg *msg)
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gmbus_xfer_read(struct drm_i915_private *dev_priv, struct i2c_msg *msg,
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u32 gmbus1_index)
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{
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int reg_offset = dev_priv->gpio_mmio_base;
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u16 len = msg->len;
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u8 *buf = msg->buf;
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I915_WRITE(GMBUS1 + reg_offset,
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gmbus1_index |
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GMBUS_CYCLE_WAIT |
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(len << GMBUS_BYTE_COUNT_SHIFT) |
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(msg->addr << GMBUS_SLAVE_ADDR_SHIFT) |
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@ -276,6 +278,46 @@ gmbus_xfer_write(struct drm_i915_private *dev_priv, struct i2c_msg *msg)
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return 0;
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}
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/*
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* The gmbus controller can combine a 1 or 2 byte write with a read that
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* immediately follows it by using an "INDEX" cycle.
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*/
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static bool
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gmbus_is_index_read(struct i2c_msg *msgs, int i, int num)
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{
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return (i + 1 < num &&
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!(msgs[i].flags & I2C_M_RD) && msgs[i].len <= 2 &&
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(msgs[i + 1].flags & I2C_M_RD));
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}
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static int
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gmbus_xfer_index_read(struct drm_i915_private *dev_priv, struct i2c_msg *msgs)
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{
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int reg_offset = dev_priv->gpio_mmio_base;
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u32 gmbus1_index = 0;
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u32 gmbus5 = 0;
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int ret;
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if (msgs[0].len == 2)
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gmbus5 = GMBUS_2BYTE_INDEX_EN |
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msgs[0].buf[1] | (msgs[0].buf[0] << 8);
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if (msgs[0].len == 1)
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gmbus1_index = GMBUS_CYCLE_INDEX |
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(msgs[0].buf[0] << GMBUS_SLAVE_INDEX_SHIFT);
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/* GMBUS5 holds 16-bit index */
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if (gmbus5)
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I915_WRITE(GMBUS5 + reg_offset, gmbus5);
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ret = gmbus_xfer_read(dev_priv, &msgs[1], gmbus1_index);
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/* Clear GMBUS5 after each index transfer */
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if (gmbus5)
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I915_WRITE(GMBUS5 + reg_offset, 0);
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return ret;
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}
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static int
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gmbus_xfer(struct i2c_adapter *adapter,
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struct i2c_msg *msgs,
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@ -300,10 +342,14 @@ gmbus_xfer(struct i2c_adapter *adapter,
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I915_WRITE(GMBUS0 + reg_offset, bus->reg0);
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for (i = 0; i < num; i++) {
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if (msgs[i].flags & I2C_M_RD)
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ret = gmbus_xfer_read(dev_priv, &msgs[i]);
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else
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if (gmbus_is_index_read(msgs, i, num)) {
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ret = gmbus_xfer_index_read(dev_priv, &msgs[i]);
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i += 1; /* set i to the index of the read xfer */
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} else if (msgs[i].flags & I2C_M_RD) {
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ret = gmbus_xfer_read(dev_priv, &msgs[i], 0);
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} else {
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ret = gmbus_xfer_write(dev_priv, &msgs[i]);
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}
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if (ret == -ETIMEDOUT)
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goto timeout;
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