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mlxsw: spectrum: Add initial support for Spectrum ASIC

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Add support for new generation Mellanox Spectrum ASIC, 10/25/40/50 and
100Gb/s Ethernet Switch.

The initial driver implements bridge forwarding offload including
bridge internal VLAN support, FDB static entries, FDB learning and
HW ageing including their setup.

Signed-off-by: Jiri Pirko <jiri@mellanox.com>
Signed-off-by: Ido Schimmel <idosch@mellanox.com>
Signed-off-by: Elad Raz <eladr@mellanox.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Jiri Pirko 2015-10-16 14:01:37 +02:00 committed by David S. Miller
parent a4feea74cd
commit 56ade8fe3f
10 changed files with 3374 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

11
drivers/net/ethernet/mellanox/mlxsw/Kconfig
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@ -30,3 +30,14 @@ config MLXSW_SWITCHX2
To compile this driver as a module, choose M here: the
module will be called mlxsw_switchx2.
config MLXSW_SPECTRUM
tristate "Mellanox Technologies Spectrum support"
depends on MLXSW_CORE && NET_SWITCHDEV
default m
---help---
This driver supports Mellanox Technologies Spectrum Ethernet
Switch ASICs.
To compile this driver as a module, choose M here: the
module will be called mlxsw_spectrum.

3
drivers/net/ethernet/mellanox/mlxsw/Makefile
View File

@ -4,3 +4,6 @@ obj-$(CONFIG_MLXSW_PCI) += mlxsw_pci.o
mlxsw_pci-objs := pci.o
obj-$(CONFIG_MLXSW_SWITCHX2) += mlxsw_switchx2.o
mlxsw_switchx2-objs := switchx2.o
obj-$(CONFIG_MLXSW_SPECTRUM) += mlxsw_spectrum.o
mlxsw_spectrum-objs := spectrum.o spectrum_buffers.o \
spectrum_switchdev.o

1
drivers/net/ethernet/mellanox/mlxsw/core.h
View File

@ -54,6 +54,7 @@
MODULE_ALIAS(MLXSW_MODULE_ALIAS_PREFIX kind)
#define MLXSW_DEVICE_KIND_SWITCHX2 "switchx2"
#define MLXSW_DEVICE_KIND_SPECTRUM "spectrum"
struct mlxsw_core;
struct mlxsw_driver;

3
drivers/net/ethernet/mellanox/mlxsw/pci.c
View File

@ -57,6 +57,7 @@ static const char mlxsw_pci_driver_name[] = "mlxsw_pci";
static const struct pci_device_id mlxsw_pci_id_table[] = {
{PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SWITCHX2), 0},
{PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SPECTRUM), 0},
{0, }
};
@ -67,6 +68,8 @@ static const char *mlxsw_pci_device_kind_get(const struct pci_device_id *id)
switch (id->device) {
case PCI_DEVICE_ID_MELLANOX_SWITCHX2:
return MLXSW_DEVICE_KIND_SWITCHX2;
case PCI_DEVICE_ID_MELLANOX_SPECTRUM:
return MLXSW_DEVICE_KIND_SPECTRUM;
default:
BUG();
}

1
drivers/net/ethernet/mellanox/mlxsw/pci.h
View File

@ -40,6 +40,7 @@
#include "item.h"
#define PCI_DEVICE_ID_MELLANOX_SWITCHX2 0xc738
#define PCI_DEVICE_ID_MELLANOX_SPECTRUM 0xcb84
#define MLXSW_PCI_BAR0_SIZE (1024 * 1024) /* 1MB */
#define MLXSW_PCI_PAGE_SIZE 4096

1948
drivers/net/ethernet/mellanox/mlxsw/spectrum.c Normal file
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File diff suppressed because it is too large Load Diff

121
drivers/net/ethernet/mellanox/mlxsw/spectrum.h Normal file
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@ -0,0 +1,121 @@
/*
* drivers/net/ethernet/mellanox/mlxsw/spectrum.h
* Copyright (c) 2015 Mellanox Technologies. All rights reserved.
* Copyright (c) 2015 Jiri Pirko <jiri@mellanox.com>
* Copyright (c) 2015 Ido Schimmel <idosch@mellanox.com>
* Copyright (c) 2015 Elad Raz <eladr@mellanox.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the names of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* Alternatively, this software may be distributed under the terms of the
* GNU General Public License ("GPL") version 2 as published by the Free
* Software Foundation.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _MLXSW_SPECTRUM_H
#define _MLXSW_SPECTRUM_H
#include <linux/types.h>
#include <linux/netdevice.h>
#include <linux/bitops.h>
#include <linux/if_vlan.h>
#include <net/switchdev.h>
#include "core.h"
#define MLXSW_SP_VFID_BASE VLAN_N_VID
struct mlxsw_sp_port;
struct mlxsw_sp {
unsigned long active_vfids[BITS_TO_LONGS(VLAN_N_VID)];
unsigned long active_fids[BITS_TO_LONGS(VLAN_N_VID)];
struct mlxsw_sp_port **ports;
struct mlxsw_core *core;
const struct mlxsw_bus_info *bus_info;
unsigned char base_mac[ETH_ALEN];
struct {
struct delayed_work dw;
#define MLXSW_SP_DEFAULT_LEARNING_INTERVAL 100
unsigned int interval; /* ms */
} fdb_notify;
#define MLXSW_SP_DEFAULT_AGEING_TIME 300
u32 ageing_time;
struct {
struct net_device *dev;
unsigned int ref_count;
} master_bridge;
};
struct mlxsw_sp_port_pcpu_stats {
u64 rx_packets;
u64 rx_bytes;
u64 tx_packets;
u64 tx_bytes;
struct u64_stats_sync syncp;
u32 tx_dropped;
};
struct mlxsw_sp_port {
struct net_device *dev;
struct mlxsw_sp_port_pcpu_stats __percpu *pcpu_stats;
struct mlxsw_sp *mlxsw_sp;
u8 local_port;
u8 stp_state;
u8 learning:1;
u8 learning_sync:1;
u16 pvid;
bool bridged;
/* 802.1Q bridge VLANs */
unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
/* VLAN interfaces */
unsigned long active_vfids[BITS_TO_LONGS(VLAN_N_VID)];
u16 nr_vfids;
};
enum mlxsw_sp_flood_table {
MLXSW_SP_FLOOD_TABLE_UC,
MLXSW_SP_FLOOD_TABLE_BM,
};
int mlxsw_sp_buffers_init(struct mlxsw_sp *mlxsw_sp);
int mlxsw_sp_port_buffers_init(struct mlxsw_sp_port *mlxsw_sp_port);
int mlxsw_sp_switchdev_init(struct mlxsw_sp *mlxsw_sp);
void mlxsw_sp_switchdev_fini(struct mlxsw_sp *mlxsw_sp);
int mlxsw_sp_port_vlan_init(struct mlxsw_sp_port *mlxsw_sp_port);
void mlxsw_sp_port_switchdev_init(struct mlxsw_sp_port *mlxsw_sp_port);
void mlxsw_sp_port_switchdev_fini(struct mlxsw_sp_port *mlxsw_sp_port);
int mlxsw_sp_port_vid_to_fid_set(struct mlxsw_sp_port *mlxsw_sp_port,
enum mlxsw_reg_svfa_mt mt, bool valid, u16 fid,
u16 vid);
int mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid_begin,
u16 vid_end, bool is_member, bool untagged);
int mlxsw_sp_port_add_vid(struct net_device *dev, __be16 __always_unused proto,
u16 vid);
int mlxsw_sp_port_kill_vid(struct net_device *dev,
__be16 __always_unused proto, u16 vid);
#endif

422
drivers/net/ethernet/mellanox/mlxsw/spectrum_buffers.c Normal file
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@ -0,0 +1,422 @@
/*
* drivers/net/ethernet/mellanox/mlxsw/spectrum_buffers.c
* Copyright (c) 2015 Mellanox Technologies. All rights reserved.
* Copyright (c) 2015 Jiri Pirko <jiri@mellanox.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the names of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* Alternatively, this software may be distributed under the terms of the
* GNU General Public License ("GPL") version 2 as published by the Free
* Software Foundation.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <linux/kernel.h>
#include <linux/types.h>
#include "spectrum.h"
#include "core.h"
#include "port.h"
#include "reg.h"
struct mlxsw_sp_pb {
u8 index;
u16 size;
};
#define MLXSW_SP_PB(_index, _size) \
{ \
.index = _index, \
.size = _size, \
}
static const struct mlxsw_sp_pb mlxsw_sp_pbs[] = {
MLXSW_SP_PB(0, 208),
MLXSW_SP_PB(1, 208),
MLXSW_SP_PB(2, 208),
MLXSW_SP_PB(3, 208),
MLXSW_SP_PB(4, 208),
MLXSW_SP_PB(5, 208),
MLXSW_SP_PB(6, 208),
MLXSW_SP_PB(7, 208),
MLXSW_SP_PB(9, 208),
};
#define MLXSW_SP_PBS_LEN ARRAY_SIZE(mlxsw_sp_pbs)
static int mlxsw_sp_port_pb_init(struct mlxsw_sp_port *mlxsw_sp_port)
{
char pbmc_pl[MLXSW_REG_PBMC_LEN];
int i;
mlxsw_reg_pbmc_pack(pbmc_pl, mlxsw_sp_port->local_port,
0xffff, 0xffff / 2);
for (i = 0; i < MLXSW_SP_PBS_LEN; i++) {
const struct mlxsw_sp_pb *pb;
pb = &mlxsw_sp_pbs[i];
mlxsw_reg_pbmc_lossy_buffer_pack(pbmc_pl, pb->index, pb->size);
}
return mlxsw_reg_write(mlxsw_sp_port->mlxsw_sp->core,
MLXSW_REG(pbmc), pbmc_pl);
}
#define MLXSW_SP_SB_BYTES_PER_CELL 96
struct mlxsw_sp_sb_pool {
u8 pool;
enum mlxsw_reg_sbpr_dir dir;
enum mlxsw_reg_sbpr_mode mode;
u32 size;
};
#define MLXSW_SP_SB_POOL_INGRESS_SIZE \
((15000000 - (2 * 20000 * MLXSW_PORT_MAX_PORTS)) / \
MLXSW_SP_SB_BYTES_PER_CELL)
#define MLXSW_SP_SB_POOL_EGRESS_SIZE \
((14000000 - (8 * 1500 * MLXSW_PORT_MAX_PORTS)) / \
MLXSW_SP_SB_BYTES_PER_CELL)
#define MLXSW_SP_SB_POOL(_pool, _dir, _mode, _size) \
{ \
.pool = _pool, \
.dir = _dir, \
.mode = _mode, \
.size = _size, \
}
#define MLXSW_SP_SB_POOL_INGRESS(_pool, _size) \
MLXSW_SP_SB_POOL(_pool, MLXSW_REG_SBPR_DIR_INGRESS, \
MLXSW_REG_SBPR_MODE_DYNAMIC, _size)
#define MLXSW_SP_SB_POOL_EGRESS(_pool, _size) \
MLXSW_SP_SB_POOL(_pool, MLXSW_REG_SBPR_DIR_EGRESS, \
MLXSW_REG_SBPR_MODE_DYNAMIC, _size)
static const struct mlxsw_sp_sb_pool mlxsw_sp_sb_pools[] = {
MLXSW_SP_SB_POOL_INGRESS(0, MLXSW_SP_SB_POOL_INGRESS_SIZE),
MLXSW_SP_SB_POOL_INGRESS(1, 0),
MLXSW_SP_SB_POOL_INGRESS(2, 0),
MLXSW_SP_SB_POOL_INGRESS(3, 0),
MLXSW_SP_SB_POOL_EGRESS(0, MLXSW_SP_SB_POOL_EGRESS_SIZE),
MLXSW_SP_SB_POOL_EGRESS(1, 0),
MLXSW_SP_SB_POOL_EGRESS(2, 0),
MLXSW_SP_SB_POOL_EGRESS(2, MLXSW_SP_SB_POOL_EGRESS_SIZE),
};
#define MLXSW_SP_SB_POOLS_LEN ARRAY_SIZE(mlxsw_sp_sb_pools)
static int mlxsw_sp_sb_pools_init(struct mlxsw_sp *mlxsw_sp)
{
char sbpr_pl[MLXSW_REG_SBPR_LEN];
int i;
int err;
for (i = 0; i < MLXSW_SP_SB_POOLS_LEN; i++) {
const struct mlxsw_sp_sb_pool *pool;
pool = &mlxsw_sp_sb_pools[i];
mlxsw_reg_sbpr_pack(sbpr_pl, pool->pool, pool->dir,
pool->mode, pool->size);
err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sbpr), sbpr_pl);
if (err)
return err;
}
return 0;
}
struct mlxsw_sp_sb_cm {
union {
u8 pg;
u8 tc;
} u;
enum mlxsw_reg_sbcm_dir dir;
u32 min_buff;
u32 max_buff;
u8 pool;
};
#define MLXSW_SP_SB_CM(_pg_tc, _dir, _min_buff, _max_buff, _pool) \
{ \
.u.pg = _pg_tc, \
.dir = _dir, \
.min_buff = _min_buff, \
.max_buff = _max_buff, \
.pool = _pool, \
}
#define MLXSW_SP_SB_CM_INGRESS(_pg, _min_buff, _max_buff) \
MLXSW_SP_SB_CM(_pg, MLXSW_REG_SBCM_DIR_INGRESS, \
_min_buff, _max_buff, 0)
#define MLXSW_SP_SB_CM_EGRESS(_tc, _min_buff, _max_buff) \
MLXSW_SP_SB_CM(_tc, MLXSW_REG_SBCM_DIR_EGRESS, \
_min_buff, _max_buff, 0)
#define MLXSW_SP_CPU_PORT_SB_CM_EGRESS(_tc) \
MLXSW_SP_SB_CM(_tc, MLXSW_REG_SBCM_DIR_EGRESS, 104, 2, 3)
static const struct mlxsw_sp_sb_cm mlxsw_sp_sb_cms[] = {
MLXSW_SP_SB_CM_INGRESS(0, 10000 / MLXSW_SP_SB_BYTES_PER_CELL, 8),
MLXSW_SP_SB_CM_INGRESS(1, 0, 0),
MLXSW_SP_SB_CM_INGRESS(2, 0, 0),
MLXSW_SP_SB_CM_INGRESS(3, 0, 0),
MLXSW_SP_SB_CM_INGRESS(4, 0, 0),
MLXSW_SP_SB_CM_INGRESS(5, 0, 0),
MLXSW_SP_SB_CM_INGRESS(6, 0, 0),
MLXSW_SP_SB_CM_INGRESS(7, 0, 0),
MLXSW_SP_SB_CM_INGRESS(9, 20000 / MLXSW_SP_SB_BYTES_PER_CELL, 0xff),
MLXSW_SP_SB_CM_EGRESS(0, 1500 / MLXSW_SP_SB_BYTES_PER_CELL, 9),
MLXSW_SP_SB_CM_EGRESS(1, 1500 / MLXSW_SP_SB_BYTES_PER_CELL, 9),
MLXSW_SP_SB_CM_EGRESS(2, 1500 / MLXSW_SP_SB_BYTES_PER_CELL, 9),
MLXSW_SP_SB_CM_EGRESS(3, 1500 / MLXSW_SP_SB_BYTES_PER_CELL, 9),
MLXSW_SP_SB_CM_EGRESS(4, 1500 / MLXSW_SP_SB_BYTES_PER_CELL, 9),
MLXSW_SP_SB_CM_EGRESS(5, 1500 / MLXSW_SP_SB_BYTES_PER_CELL, 9),
MLXSW_SP_SB_CM_EGRESS(6, 1500 / MLXSW_SP_SB_BYTES_PER_CELL, 9),
MLXSW_SP_SB_CM_EGRESS(7, 1500 / MLXSW_SP_SB_BYTES_PER_CELL, 9),
MLXSW_SP_SB_CM_EGRESS(8, 0, 0),
MLXSW_SP_SB_CM_EGRESS(9, 0, 0),
MLXSW_SP_SB_CM_EGRESS(10, 0, 0),
MLXSW_SP_SB_CM_EGRESS(11, 0, 0),
MLXSW_SP_SB_CM_EGRESS(12, 0, 0),
MLXSW_SP_SB_CM_EGRESS(13, 0, 0),
MLXSW_SP_SB_CM_EGRESS(14, 0, 0),
MLXSW_SP_SB_CM_EGRESS(15, 0, 0),
MLXSW_SP_SB_CM_EGRESS(16, 1, 0xff),
};
#define MLXSW_SP_SB_CMS_LEN ARRAY_SIZE(mlxsw_sp_sb_cms)
static const struct mlxsw_sp_sb_cm mlxsw_sp_cpu_port_sb_cms[] = {
MLXSW_SP_CPU_PORT_SB_CM_EGRESS(0),
MLXSW_SP_CPU_PORT_SB_CM_EGRESS(1),
MLXSW_SP_CPU_PORT_SB_CM_EGRESS(2),
MLXSW_SP_CPU_PORT_SB_CM_EGRESS(3),
MLXSW_SP_CPU_PORT_SB_CM_EGRESS(4),
MLXSW_SP_CPU_PORT_SB_CM_EGRESS(5),
MLXSW_SP_CPU_PORT_SB_CM_EGRESS(6),
MLXSW_SP_CPU_PORT_SB_CM_EGRESS(7),
MLXSW_SP_CPU_PORT_SB_CM_EGRESS(8),
MLXSW_SP_CPU_PORT_SB_CM_EGRESS(9),
MLXSW_SP_CPU_PORT_SB_CM_EGRESS(10),
MLXSW_SP_CPU_PORT_SB_CM_EGRESS(11),
MLXSW_SP_CPU_PORT_SB_CM_EGRESS(12),
MLXSW_SP_CPU_PORT_SB_CM_EGRESS(13),
MLXSW_SP_CPU_PORT_SB_CM_EGRESS(14),
MLXSW_SP_CPU_PORT_SB_CM_EGRESS(15),
MLXSW_SP_CPU_PORT_SB_CM_EGRESS(16),
MLXSW_SP_CPU_PORT_SB_CM_EGRESS(17),
MLXSW_SP_CPU_PORT_SB_CM_EGRESS(18),
MLXSW_SP_CPU_PORT_SB_CM_EGRESS(19),
MLXSW_SP_CPU_PORT_SB_CM_EGRESS(20),
MLXSW_SP_CPU_PORT_SB_CM_EGRESS(21),
MLXSW_SP_CPU_PORT_SB_CM_EGRESS(22),
MLXSW_SP_CPU_PORT_SB_CM_EGRESS(23),
MLXSW_SP_CPU_PORT_SB_CM_EGRESS(24),
MLXSW_SP_CPU_PORT_SB_CM_EGRESS(25),
MLXSW_SP_CPU_PORT_SB_CM_EGRESS(26),
MLXSW_SP_CPU_PORT_SB_CM_EGRESS(27),
MLXSW_SP_CPU_PORT_SB_CM_EGRESS(28),
MLXSW_SP_CPU_PORT_SB_CM_EGRESS(29),
MLXSW_SP_CPU_PORT_SB_CM_EGRESS(30),
MLXSW_SP_CPU_PORT_SB_CM_EGRESS(31),
};
#define MLXSW_SP_CPU_PORT_SB_MCS_LEN \
ARRAY_SIZE(mlxsw_sp_cpu_port_sb_cms)
static int mlxsw_sp_sb_cms_init(struct mlxsw_sp *mlxsw_sp, u8 local_port,
const struct mlxsw_sp_sb_cm *cms,
size_t cms_len)
{
char sbcm_pl[MLXSW_REG_SBCM_LEN];
int i;
int err;
for (i = 0; i < cms_len; i++) {
const struct mlxsw_sp_sb_cm *cm;
cm = &cms[i];
mlxsw_reg_sbcm_pack(sbcm_pl, local_port, cm->u.pg, cm->dir,
cm->min_buff, cm->max_buff, cm->pool);
err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sbcm), sbcm_pl);
if (err)
return err;
}
return 0;
}
static int mlxsw_sp_port_sb_cms_init(struct mlxsw_sp_port *mlxsw_sp_port)
{
return mlxsw_sp_sb_cms_init(mlxsw_sp_port->mlxsw_sp,
mlxsw_sp_port->local_port, mlxsw_sp_sb_cms,
MLXSW_SP_SB_CMS_LEN);
}
static int mlxsw_sp_cpu_port_sb_cms_init(struct mlxsw_sp *mlxsw_sp)
{
return mlxsw_sp_sb_cms_init(mlxsw_sp, 0, mlxsw_sp_cpu_port_sb_cms,
MLXSW_SP_CPU_PORT_SB_MCS_LEN);
}
struct mlxsw_sp_sb_pm {
u8 pool;
enum mlxsw_reg_sbpm_dir dir;
u32 min_buff;
u32 max_buff;
};
#define MLXSW_SP_SB_PM(_pool, _dir, _min_buff, _max_buff) \
{ \
.pool = _pool, \
.dir = _dir, \
.min_buff = _min_buff, \
.max_buff = _max_buff, \
}
#define MLXSW_SP_SB_PM_INGRESS(_pool, _min_buff, _max_buff) \
MLXSW_SP_SB_PM(_pool, MLXSW_REG_SBPM_DIR_INGRESS, \
_min_buff, _max_buff)
#define MLXSW_SP_SB_PM_EGRESS(_pool, _min_buff, _max_buff) \
MLXSW_SP_SB_PM(_pool, MLXSW_REG_SBPM_DIR_EGRESS, \
_min_buff, _max_buff)
static const struct mlxsw_sp_sb_pm mlxsw_sp_sb_pms[] = {
MLXSW_SP_SB_PM_INGRESS(0, 0, 0xff),
MLXSW_SP_SB_PM_INGRESS(1, 0, 0),
MLXSW_SP_SB_PM_INGRESS(2, 0, 0),
MLXSW_SP_SB_PM_INGRESS(3, 0, 0),
MLXSW_SP_SB_PM_EGRESS(0, 0, 7),
MLXSW_SP_SB_PM_EGRESS(1, 0, 0),
MLXSW_SP_SB_PM_EGRESS(2, 0, 0),
MLXSW_SP_SB_PM_EGRESS(3, 0, 0),
};
#define MLXSW_SP_SB_PMS_LEN ARRAY_SIZE(mlxsw_sp_sb_pms)
static int mlxsw_sp_port_sb_pms_init(struct mlxsw_sp_port *mlxsw_sp_port)
{
char sbpm_pl[MLXSW_REG_SBPM_LEN];
int i;
int err;
for (i = 0; i < MLXSW_SP_SB_PMS_LEN; i++) {
const struct mlxsw_sp_sb_pm *pm;
pm = &mlxsw_sp_sb_pms[i];
mlxsw_reg_sbpm_pack(sbpm_pl, mlxsw_sp_port->local_port,
pm->pool, pm->dir,
pm->min_buff, pm->max_buff);
err = mlxsw_reg_write(mlxsw_sp_port->mlxsw_sp->core,
MLXSW_REG(sbpm), sbpm_pl);
if (err)
return err;
}
return 0;
}
struct mlxsw_sp_sb_mm {
u8 prio;
u32 min_buff;
u32 max_buff;
u8 pool;
};
#define MLXSW_SP_SB_MM(_prio, _min_buff, _max_buff, _pool) \
{ \
.prio = _prio, \
.min_buff = _min_buff, \
.max_buff = _max_buff, \
.pool = _pool, \
}
static const struct mlxsw_sp_sb_mm mlxsw_sp_sb_mms[] = {
MLXSW_SP_SB_MM(0, 20000 / MLXSW_SP_SB_BYTES_PER_CELL, 0xff, 0),
MLXSW_SP_SB_MM(1, 20000 / MLXSW_SP_SB_BYTES_PER_CELL, 0xff, 0),
MLXSW_SP_SB_MM(2, 20000 / MLXSW_SP_SB_BYTES_PER_CELL, 0xff, 0),
MLXSW_SP_SB_MM(3, 20000 / MLXSW_SP_SB_BYTES_PER_CELL, 0xff, 0),
MLXSW_SP_SB_MM(4, 20000 / MLXSW_SP_SB_BYTES_PER_CELL, 0xff, 0),
MLXSW_SP_SB_MM(5, 20000 / MLXSW_SP_SB_BYTES_PER_CELL, 0xff, 0),
MLXSW_SP_SB_MM(6, 20000 / MLXSW_SP_SB_BYTES_PER_CELL, 0xff, 0),
MLXSW_SP_SB_MM(7, 20000 / MLXSW_SP_SB_BYTES_PER_CELL, 0xff, 0),
MLXSW_SP_SB_MM(8, 20000 / MLXSW_SP_SB_BYTES_PER_CELL, 0xff, 0),
MLXSW_SP_SB_MM(9, 20000 / MLXSW_SP_SB_BYTES_PER_CELL, 0xff, 0),
MLXSW_SP_SB_MM(10, 20000 / MLXSW_SP_SB_BYTES_PER_CELL, 0xff, 0),
MLXSW_SP_SB_MM(11, 20000 / MLXSW_SP_SB_BYTES_PER_CELL, 0xff, 0),
MLXSW_SP_SB_MM(12, 20000 / MLXSW_SP_SB_BYTES_PER_CELL, 0xff, 0),
MLXSW_SP_SB_MM(13, 20000 / MLXSW_SP_SB_BYTES_PER_CELL, 0xff, 0),
MLXSW_SP_SB_MM(14, 20000 / MLXSW_SP_SB_BYTES_PER_CELL, 0xff, 0),
};
#define MLXSW_SP_SB_MMS_LEN ARRAY_SIZE(mlxsw_sp_sb_mms)
static int mlxsw_sp_sb_mms_init(struct mlxsw_sp *mlxsw_sp)
{
char sbmm_pl[MLXSW_REG_SBMM_LEN];
int i;
int err;
for (i = 0; i < MLXSW_SP_SB_MMS_LEN; i++) {
const struct mlxsw_sp_sb_mm *mc;
mc = &mlxsw_sp_sb_mms[i];
mlxsw_reg_sbmm_pack(sbmm_pl, mc->prio, mc->min_buff,
mc->max_buff, mc->pool);
err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sbmm), sbmm_pl);
if (err)
return err;
}
return 0;
}
int mlxsw_sp_buffers_init(struct mlxsw_sp *mlxsw_sp)
{
int err;
err = mlxsw_sp_sb_pools_init(mlxsw_sp);
if (err)
return err;
err = mlxsw_sp_cpu_port_sb_cms_init(mlxsw_sp);
if (err)
return err;
err = mlxsw_sp_sb_mms_init(mlxsw_sp);
return err;
}
int mlxsw_sp_port_buffers_init(struct mlxsw_sp_port *mlxsw_sp_port)
{
int err;
err = mlxsw_sp_port_pb_init(mlxsw_sp_port);
if (err)
return err;
err = mlxsw_sp_port_sb_cms_init(mlxsw_sp_port);
if (err)
return err;
err = mlxsw_sp_port_sb_pms_init(mlxsw_sp_port);
return err;
}

863
drivers/net/ethernet/mellanox/mlxsw/spectrum_switchdev.c Normal file
View File

@ -0,0 +1,863 @@
/*
* drivers/net/ethernet/mellanox/mlxsw/spectrum_switchdev.c
* Copyright (c) 2015 Mellanox Technologies. All rights reserved.
* Copyright (c) 2015 Jiri Pirko <jiri@mellanox.com>
* Copyright (c) 2015 Ido Schimmel <idosch@mellanox.com>
* Copyright (c) 2015 Elad Raz <eladr@mellanox.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the names of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* Alternatively, this software may be distributed under the terms of the
* GNU General Public License ("GPL") version 2 as published by the Free
* Software Foundation.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <linux/slab.h>
#include <linux/device.h>
#include <linux/skbuff.h>
#include <linux/if_vlan.h>
#include <linux/if_bridge.h>
#include <linux/workqueue.h>
#include <linux/jiffies.h>
#include <net/switchdev.h>
#include "spectrum.h"
#include "core.h"
#include "reg.h"
static int mlxsw_sp_port_attr_get(struct net_device *dev,
struct switchdev_attr *attr)
{
struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
switch (attr->id) {
case SWITCHDEV_ATTR_ID_PORT_PARENT_ID:
attr->u.ppid.id_len = sizeof(mlxsw_sp->base_mac);
memcpy(&attr->u.ppid.id, &mlxsw_sp->base_mac,
attr->u.ppid.id_len);
break;
case SWITCHDEV_ATTR_ID_PORT_BRIDGE_FLAGS:
attr->u.brport_flags =
(mlxsw_sp_port->learning ? BR_LEARNING : 0) |
(mlxsw_sp_port->learning_sync ? BR_LEARNING_SYNC : 0);
break;
default:
return -EOPNOTSUPP;
}
return 0;
}
static int mlxsw_sp_port_stp_state_set(struct mlxsw_sp_port *mlxsw_sp_port,
u8 state)
{
struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
enum mlxsw_reg_spms_state spms_state;
char *spms_pl;
u16 vid;
int err;
switch (state) {
case BR_STATE_DISABLED: /* fall-through */
case BR_STATE_FORWARDING:
spms_state = MLXSW_REG_SPMS_STATE_FORWARDING;
break;
case BR_STATE_LISTENING: /* fall-through */
case BR_STATE_LEARNING:
spms_state = MLXSW_REG_SPMS_STATE_LEARNING;
break;
case BR_STATE_BLOCKING:
spms_state = MLXSW_REG_SPMS_STATE_DISCARDING;
break;
default:
BUG();
}
spms_pl = kmalloc(MLXSW_REG_SPMS_LEN, GFP_KERNEL);
if (!spms_pl)
return -ENOMEM;
mlxsw_reg_spms_pack(spms_pl, mlxsw_sp_port->local_port);
for_each_set_bit(vid, mlxsw_sp_port->active_vlans, VLAN_N_VID)
mlxsw_reg_spms_vid_pack(spms_pl, vid, spms_state);
err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spms), spms_pl);
kfree(spms_pl);
return err;
}
static int mlxsw_sp_port_attr_stp_state_set(struct mlxsw_sp_port *mlxsw_sp_port,
struct switchdev_trans *trans,
u8 state)
{
if (switchdev_trans_ph_prepare(trans))
return 0;
mlxsw_sp_port->stp_state = state;
return mlxsw_sp_port_stp_state_set(mlxsw_sp_port, state);
}
static int mlxsw_sp_port_attr_br_flags_set(struct mlxsw_sp_port *mlxsw_sp_port,
struct switchdev_trans *trans,
unsigned long brport_flags)
{
if (switchdev_trans_ph_prepare(trans))
return 0;
mlxsw_sp_port->learning = brport_flags & BR_LEARNING ? 1 : 0;
mlxsw_sp_port->learning_sync = brport_flags & BR_LEARNING_SYNC ? 1 : 0;
return 0;
}
static int mlxsw_sp_ageing_set(struct mlxsw_sp *mlxsw_sp, u32 ageing_time)
{
char sfdat_pl[MLXSW_REG_SFDAT_LEN];
int err;
mlxsw_reg_sfdat_pack(sfdat_pl, ageing_time);
err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sfdat), sfdat_pl);
if (err)
return err;
mlxsw_sp->ageing_time = ageing_time;
return 0;
}
static int mlxsw_sp_port_attr_br_ageing_set(struct mlxsw_sp_port *mlxsw_sp_port,
struct switchdev_trans *trans,
unsigned long ageing_jiffies)
{
struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
u32 ageing_time = jiffies_to_msecs(ageing_jiffies) / 1000;
if (switchdev_trans_ph_prepare(trans))
return 0;
return mlxsw_sp_ageing_set(mlxsw_sp, ageing_time);
}
static int mlxsw_sp_port_attr_set(struct net_device *dev,
const struct switchdev_attr *attr,
struct switchdev_trans *trans)
{
struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
int err = 0;
switch (attr->id) {
case SWITCHDEV_ATTR_ID_PORT_STP_STATE:
err = mlxsw_sp_port_attr_stp_state_set(mlxsw_sp_port, trans,
attr->u.stp_state);
break;
case SWITCHDEV_ATTR_ID_PORT_BRIDGE_FLAGS:
err = mlxsw_sp_port_attr_br_flags_set(mlxsw_sp_port, trans,
attr->u.brport_flags);
break;
case SWITCHDEV_ATTR_ID_BRIDGE_AGEING_TIME:
err = mlxsw_sp_port_attr_br_ageing_set(mlxsw_sp_port, trans,
attr->u.ageing_time);
break;
default:
err = -EOPNOTSUPP;
break;
}
return err;
}
static int mlxsw_sp_port_pvid_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
{
struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
char spvid_pl[MLXSW_REG_SPVID_LEN];
mlxsw_reg_spvid_pack(spvid_pl, mlxsw_sp_port->local_port, vid);
return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvid), spvid_pl);
}
static int mlxsw_sp_fid_create(struct mlxsw_sp *mlxsw_sp, u16 fid)
{
char sfmr_pl[MLXSW_REG_SFMR_LEN];
int err;
mlxsw_reg_sfmr_pack(sfmr_pl, MLXSW_REG_SFMR_OP_CREATE_FID, fid, fid);
err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sfmr), sfmr_pl);
if (err)
return err;
set_bit(fid, mlxsw_sp->active_fids);
return 0;
}
static void mlxsw_sp_fid_destroy(struct mlxsw_sp *mlxsw_sp, u16 fid)
{
char sfmr_pl[MLXSW_REG_SFMR_LEN];
clear_bit(fid, mlxsw_sp->active_fids);
mlxsw_reg_sfmr_pack(sfmr_pl, MLXSW_REG_SFMR_OP_DESTROY_FID,
fid, fid);
mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sfmr), sfmr_pl);
}
static int mlxsw_sp_port_fid_map(struct mlxsw_sp_port *mlxsw_sp_port, u16 fid)
{
enum mlxsw_reg_svfa_mt mt;
if (mlxsw_sp_port->nr_vfids)
mt = MLXSW_REG_SVFA_MT_PORT_VID_TO_FID;
else
mt = MLXSW_REG_SVFA_MT_VID_TO_FID;
return mlxsw_sp_port_vid_to_fid_set(mlxsw_sp_port, mt, true, fid, fid);
}
static int mlxsw_sp_port_fid_unmap(struct mlxsw_sp_port *mlxsw_sp_port, u16 fid)
{
enum mlxsw_reg_svfa_mt mt;
if (!mlxsw_sp_port->nr_vfids)
return 0;
mt = MLXSW_REG_SVFA_MT_PORT_VID_TO_FID;
return mlxsw_sp_port_vid_to_fid_set(mlxsw_sp_port, mt, false, fid, fid);
}
static int __mlxsw_sp_port_flood_set(struct mlxsw_sp_port *mlxsw_sp_port,
u16 fid, bool set, bool only_uc)
{
struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
char *sftr_pl;
int err;
sftr_pl = kmalloc(MLXSW_REG_SFTR_LEN, GFP_KERNEL);
if (!sftr_pl)
return -ENOMEM;
mlxsw_reg_sftr_pack(sftr_pl, MLXSW_SP_FLOOD_TABLE_UC, fid,
MLXSW_REG_SFGC_TABLE_TYPE_FID_OFFEST, 0,
mlxsw_sp_port->local_port, set);
err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sftr), sftr_pl);
if (err)
goto buffer_out;
/* Flooding control allows one to decide whether a given port will
* flood unicast traffic for which there is no FDB entry.
*/
if (only_uc)
goto buffer_out;
mlxsw_reg_sftr_pack(sftr_pl, MLXSW_SP_FLOOD_TABLE_BM, fid,
MLXSW_REG_SFGC_TABLE_TYPE_FID_OFFEST, 0,
mlxsw_sp_port->local_port, set);
err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sftr), sftr_pl);
buffer_out:
kfree(sftr_pl);
return err;
}
static int mlxsw_sp_port_add_vids(struct net_device *dev, u16 vid_begin,
u16 vid_end)
{
u16 vid;
int err;
for (vid = vid_begin; vid <= vid_end; vid++) {
err = mlxsw_sp_port_add_vid(dev, 0, vid);
if (err)
goto err_port_add_vid;
}
return 0;
err_port_add_vid:
for (vid--; vid >= vid_begin; vid--)
mlxsw_sp_port_kill_vid(dev, 0, vid);
return err;
}
static int __mlxsw_sp_port_vlans_add(struct mlxsw_sp_port *mlxsw_sp_port,
u16 vid_begin, u16 vid_end,
bool flag_untagged, bool flag_pvid)
{
struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
struct net_device *dev = mlxsw_sp_port->dev;
enum mlxsw_reg_svfa_mt mt;
u16 vid, vid_e;
int err;
/* In case this is invoked with BRIDGE_FLAGS_SELF and port is
* not bridged, then packets ingressing through the port with
* the specified VIDs will be directed to CPU.
*/
if (!mlxsw_sp_port->bridged)
return mlxsw_sp_port_add_vids(dev, vid_begin, vid_end);
for (vid = vid_begin; vid <= vid_end; vid++) {
if (!test_bit(vid, mlxsw_sp->active_fids)) {
err = mlxsw_sp_fid_create(mlxsw_sp, vid);
if (err) {
netdev_err(dev, "Failed to create FID=%d\n",
vid);
return err;
}
/* When creating a FID, we set a VID to FID mapping
* regardless of the port's mode.
*/
mt = MLXSW_REG_SVFA_MT_VID_TO_FID;
err = mlxsw_sp_port_vid_to_fid_set(mlxsw_sp_port, mt,
true, vid, vid);
if (err) {
netdev_err(dev, "Failed to create FID=VID=%d mapping\n",
vid);
return err;
}
}
/* Set FID mapping according to port's mode */
err = mlxsw_sp_port_fid_map(mlxsw_sp_port, vid);
if (err) {
netdev_err(dev, "Failed to map FID=%d", vid);
return err;
}
err = __mlxsw_sp_port_flood_set(mlxsw_sp_port, vid, true,
false);
if (err) {
netdev_err(dev, "Failed to set flooding for FID=%d",
vid);
return err;
}
}
for (vid = vid_begin; vid <= vid_end;
vid += MLXSW_REG_SPVM_REC_MAX_COUNT) {
vid_e = min((u16) (vid + MLXSW_REG_SPVM_REC_MAX_COUNT - 1),
vid_end);
err = mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid_e, true,
flag_untagged);
if (err) {
netdev_err(mlxsw_sp_port->dev, "Unable to add VIDs %d-%d\n",
vid, vid_e);
return err;
}
}
vid = vid_begin;
if (flag_pvid && mlxsw_sp_port->pvid != vid) {
err = mlxsw_sp_port_pvid_set(mlxsw_sp_port, vid);
if (err) {
netdev_err(mlxsw_sp_port->dev, "Unable to add PVID %d\n",
vid);
return err;
}
mlxsw_sp_port->pvid = vid;
}
/* Changing activity bits only if HW operation succeded */
for (vid = vid_begin; vid <= vid_end; vid++)
set_bit(vid, mlxsw_sp_port->active_vlans);
return mlxsw_sp_port_stp_state_set(mlxsw_sp_port,
mlxsw_sp_port->stp_state);
}
static int mlxsw_sp_port_vlans_add(struct mlxsw_sp_port *mlxsw_sp_port,
const struct switchdev_obj_port_vlan *vlan,
struct switchdev_trans *trans)
{
bool untagged_flag = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
bool pvid_flag = vlan->flags & BRIDGE_VLAN_INFO_PVID;
if (switchdev_trans_ph_prepare(trans))
return 0;
return __mlxsw_sp_port_vlans_add(mlxsw_sp_port,
vlan->vid_begin, vlan->vid_end,
untagged_flag, pvid_flag);
}
static int mlxsw_sp_port_fdb_op(struct mlxsw_sp_port *mlxsw_sp_port,
const char *mac, u16 vid, bool adding,
bool dynamic)
{
enum mlxsw_reg_sfd_rec_policy policy;
enum mlxsw_reg_sfd_op op;
char *sfd_pl;
int err;
if (!vid)
vid = mlxsw_sp_port->pvid;
sfd_pl = kmalloc(MLXSW_REG_SFD_LEN, GFP_KERNEL);
if (!sfd_pl)
return -ENOMEM;
policy = dynamic ? MLXSW_REG_SFD_REC_POLICY_DYNAMIC_ENTRY_INGRESS :
MLXSW_REG_SFD_REC_POLICY_STATIC_ENTRY;
op = adding ? MLXSW_REG_SFD_OP_WRITE_EDIT :
MLXSW_REG_SFD_OP_WRITE_REMOVE;
mlxsw_reg_sfd_pack(sfd_pl, op, 0);
mlxsw_reg_sfd_uc_pack(sfd_pl, 0, policy,
mac, vid, MLXSW_REG_SFD_REC_ACTION_NOP,
mlxsw_sp_port->local_port);
err = mlxsw_reg_write(mlxsw_sp_port->mlxsw_sp->core, MLXSW_REG(sfd),
sfd_pl);
kfree(sfd_pl);
return err;
}
static int
mlxsw_sp_port_fdb_static_add(struct mlxsw_sp_port *mlxsw_sp_port,
const struct switchdev_obj_port_fdb *fdb,
struct switchdev_trans *trans)
{
if (switchdev_trans_ph_prepare(trans))
return 0;
return mlxsw_sp_port_fdb_op(mlxsw_sp_port, fdb->addr, fdb->vid,
true, false);
}
static int mlxsw_sp_port_obj_add(struct net_device *dev,
const struct switchdev_obj *obj,
struct switchdev_trans *trans)
{
struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
int err = 0;
switch (obj->id) {
case SWITCHDEV_OBJ_ID_PORT_VLAN:
err = mlxsw_sp_port_vlans_add(mlxsw_sp_port,
SWITCHDEV_OBJ_PORT_VLAN(obj),
trans);
break;
case SWITCHDEV_OBJ_ID_PORT_FDB:
err = mlxsw_sp_port_fdb_static_add(mlxsw_sp_port,
SWITCHDEV_OBJ_PORT_FDB(obj),
trans);
break;
default:
err = -EOPNOTSUPP;
break;
}
return err;
}
static int mlxsw_sp_port_kill_vids(struct net_device *dev, u16 vid_begin,
u16 vid_end)
{
u16 vid;
int err;
for (vid = vid_begin; vid <= vid_end; vid++) {
err = mlxsw_sp_port_kill_vid(dev, 0, vid);
if (err)
return err;
}
return 0;
}
static int __mlxsw_sp_port_vlans_del(struct mlxsw_sp_port *mlxsw_sp_port,
u16 vid_begin, u16 vid_end, bool init)
{
struct net_device *dev = mlxsw_sp_port->dev;
u16 vid, vid_e;
int err;
/* In case this is invoked with BRIDGE_FLAGS_SELF and port is
* not bridged, then prevent packets ingressing through the
* port with the specified VIDs from being trapped to CPU.
*/
if (!init && !mlxsw_sp_port->bridged)
return mlxsw_sp_port_kill_vids(dev, vid_begin, vid_end);
for (vid = vid_begin; vid <= vid_end;
vid += MLXSW_REG_SPVM_REC_MAX_COUNT) {
vid_e = min((u16) (vid + MLXSW_REG_SPVM_REC_MAX_COUNT - 1),
vid_end);
err = mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid_e, false,
false);
if (err) {
netdev_err(mlxsw_sp_port->dev, "Unable to del VIDs %d-%d\n",
vid, vid_e);
return err;
}
}
if ((mlxsw_sp_port->pvid >= vid_begin) &&
(mlxsw_sp_port->pvid <= vid_end)) {
/* Default VLAN is always 1 */
mlxsw_sp_port->pvid = 1;
err = mlxsw_sp_port_pvid_set(mlxsw_sp_port,
mlxsw_sp_port->pvid);
if (err) {
netdev_err(mlxsw_sp_port->dev, "Unable to del PVID %d\n",
vid);
return err;
}
}
if (init)
goto out;
for (vid = vid_begin; vid <= vid_end; vid++) {
err = __mlxsw_sp_port_flood_set(mlxsw_sp_port, vid, false,
false);
if (err) {
netdev_err(dev, "Failed to clear flooding for FID=%d",
vid);
return err;
}
/* Remove FID mapping in case of Virtual mode */
err = mlxsw_sp_port_fid_unmap(mlxsw_sp_port, vid);
if (err) {
netdev_err(dev, "Failed to unmap FID=%d", vid);
return err;
}
}
out:
/* Changing activity bits only if HW operation succeded */
for (vid = vid_begin; vid <= vid_end; vid++)
clear_bit(vid, mlxsw_sp_port->active_vlans);
return 0;
}
static int mlxsw_sp_port_vlans_del(struct mlxsw_sp_port *mlxsw_sp_port,
const struct switchdev_obj_port_vlan *vlan)
{
return __mlxsw_sp_port_vlans_del(mlxsw_sp_port,
vlan->vid_begin, vlan->vid_end, false);
}
static int
mlxsw_sp_port_fdb_static_del(struct mlxsw_sp_port *mlxsw_sp_port,
const struct switchdev_obj_port_fdb *fdb)
{
return mlxsw_sp_port_fdb_op(mlxsw_sp_port, fdb->addr, fdb->vid,
false, false);
}
static int mlxsw_sp_port_obj_del(struct net_device *dev,
const struct switchdev_obj *obj)
{
struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
int err = 0;
switch (obj->id) {
case SWITCHDEV_OBJ_ID_PORT_VLAN:
err = mlxsw_sp_port_vlans_del(mlxsw_sp_port,
SWITCHDEV_OBJ_PORT_VLAN(obj));
break;
case SWITCHDEV_OBJ_ID_PORT_FDB:
err = mlxsw_sp_port_fdb_static_del(mlxsw_sp_port,
SWITCHDEV_OBJ_PORT_FDB(obj));
break;
default:
err = -EOPNOTSUPP;
break;
}
return err;
}
static int mlxsw_sp_port_fdb_dump(struct mlxsw_sp_port *mlxsw_sp_port,
struct switchdev_obj_port_fdb *fdb,
switchdev_obj_dump_cb_t *cb)
{
char *sfd_pl;
char mac[ETH_ALEN];
u16 vid;
u8 local_port;
u8 num_rec;
int stored_err = 0;
int i;
int err;
sfd_pl = kmalloc(MLXSW_REG_SFD_LEN, GFP_KERNEL);
if (!sfd_pl)
return -ENOMEM;
mlxsw_reg_sfd_pack(sfd_pl, MLXSW_REG_SFD_OP_QUERY_DUMP, 0);
do {
mlxsw_reg_sfd_num_rec_set(sfd_pl, MLXSW_REG_SFD_REC_MAX_COUNT);
err = mlxsw_reg_query(mlxsw_sp_port->mlxsw_sp->core,
MLXSW_REG(sfd), sfd_pl);
if (err)
goto out;
num_rec = mlxsw_reg_sfd_num_rec_get(sfd_pl);
/* Even in case of error, we have to run the dump to the end
* so the session in firmware is finished.
*/
if (stored_err)
continue;
for (i = 0; i < num_rec; i++) {
switch (mlxsw_reg_sfd_rec_type_get(sfd_pl, i)) {
case MLXSW_REG_SFD_REC_TYPE_UNICAST:
mlxsw_reg_sfd_uc_unpack(sfd_pl, i, mac, &vid,
&local_port);
if (local_port == mlxsw_sp_port->local_port) {
ether_addr_copy(fdb->addr, mac);
fdb->ndm_state = NUD_REACHABLE;
fdb->vid = vid;
err = cb(&fdb->obj);
if (err)
stored_err = err;
}
}
}
} while (num_rec == MLXSW_REG_SFD_REC_MAX_COUNT);
out:
kfree(sfd_pl);
return stored_err ? stored_err : err;
}
static int mlxsw_sp_port_vlan_dump(struct mlxsw_sp_port *mlxsw_sp_port,
struct switchdev_obj_port_vlan *vlan,
switchdev_obj_dump_cb_t *cb)
{
u16 vid;
int err = 0;
for_each_set_bit(vid, mlxsw_sp_port->active_vlans, VLAN_N_VID) {
vlan->flags = 0;
if (vid == mlxsw_sp_port->pvid)
vlan->flags |= BRIDGE_VLAN_INFO_PVID;
vlan->vid_begin = vid;
vlan->vid_end = vid;
err = cb(&vlan->obj);
if (err)
break;
}
return err;
}
static int mlxsw_sp_port_obj_dump(struct net_device *dev,
struct switchdev_obj *obj,
switchdev_obj_dump_cb_t *cb)
{
struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
int err = 0;
switch (obj->id) {
case SWITCHDEV_OBJ_ID_PORT_VLAN:
err = mlxsw_sp_port_vlan_dump(mlxsw_sp_port,
SWITCHDEV_OBJ_PORT_VLAN(obj), cb);
break;
case SWITCHDEV_OBJ_ID_PORT_FDB:
err = mlxsw_sp_port_fdb_dump(mlxsw_sp_port,
SWITCHDEV_OBJ_PORT_FDB(obj), cb);
break;
default:
err = -EOPNOTSUPP;
break;
}
return err;
}
const struct switchdev_ops mlxsw_sp_port_switchdev_ops = {
.switchdev_port_attr_get = mlxsw_sp_port_attr_get,
.switchdev_port_attr_set = mlxsw_sp_port_attr_set,
.switchdev_port_obj_add = mlxsw_sp_port_obj_add,
.switchdev_port_obj_del = mlxsw_sp_port_obj_del,
.switchdev_port_obj_dump = mlxsw_sp_port_obj_dump,
};
static void mlxsw_sp_fdb_notify_mac_process(struct mlxsw_sp *mlxsw_sp,
char *sfn_pl, int rec_index,
bool adding)
{
struct mlxsw_sp_port *mlxsw_sp_port;
char mac[ETH_ALEN];
u8 local_port;
u16 vid;
int err;
mlxsw_reg_sfn_mac_unpack(sfn_pl, rec_index, mac, &vid, &local_port);
mlxsw_sp_port = mlxsw_sp->ports[local_port];
if (!mlxsw_sp_port) {
dev_err_ratelimited(mlxsw_sp->bus_info->dev, "Incorrect local port in FDB notification\n");
return;
}
err = mlxsw_sp_port_fdb_op(mlxsw_sp_port, mac, vid,
adding && mlxsw_sp_port->learning, true);
if (err) {
if (net_ratelimit())
netdev_err(mlxsw_sp_port->dev, "Failed to set FDB entry\n");
return;
}
if (mlxsw_sp_port->learning && mlxsw_sp_port->learning_sync) {
struct switchdev_notifier_fdb_info info;
unsigned long notifier_type;
info.addr = mac;
info.vid = vid;
notifier_type = adding ? SWITCHDEV_FDB_ADD : SWITCHDEV_FDB_DEL;
call_switchdev_notifiers(notifier_type, mlxsw_sp_port->dev,
&info.info);
}
}
static void mlxsw_sp_fdb_notify_rec_process(struct mlxsw_sp *mlxsw_sp,
char *sfn_pl, int rec_index)
{
switch (mlxsw_reg_sfn_rec_type_get(sfn_pl, rec_index)) {
case MLXSW_REG_SFN_REC_TYPE_LEARNED_MAC:
mlxsw_sp_fdb_notify_mac_process(mlxsw_sp, sfn_pl,
rec_index, true);
break;
case MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC:
mlxsw_sp_fdb_notify_mac_process(mlxsw_sp, sfn_pl,
rec_index, false);
break;
}
}
static void mlxsw_sp_fdb_notify_work_schedule(struct mlxsw_sp *mlxsw_sp)
{
schedule_delayed_work(&mlxsw_sp->fdb_notify.dw,
msecs_to_jiffies(mlxsw_sp->fdb_notify.interval));
}
static void mlxsw_sp_fdb_notify_work(struct work_struct *work)
{
struct mlxsw_sp *mlxsw_sp;
char *sfn_pl;
u8 num_rec;
int i;
int err;
sfn_pl = kmalloc(MLXSW_REG_SFN_LEN, GFP_KERNEL);
if (!sfn_pl)
return;
mlxsw_sp = container_of(work, struct mlxsw_sp, fdb_notify.dw.work);
do {
mlxsw_reg_sfn_pack(sfn_pl);
err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(sfn), sfn_pl);
if (err) {
dev_err_ratelimited(mlxsw_sp->bus_info->dev, "Failed to get FDB notifications\n");
break;
}
num_rec = mlxsw_reg_sfn_num_rec_get(sfn_pl);
for (i = 0; i < num_rec; i++)
mlxsw_sp_fdb_notify_rec_process(mlxsw_sp, sfn_pl, i);
} while (num_rec);
kfree(sfn_pl);
mlxsw_sp_fdb_notify_work_schedule(mlxsw_sp);
}
static int mlxsw_sp_fdb_init(struct mlxsw_sp *mlxsw_sp)
{
int err;
err = mlxsw_sp_ageing_set(mlxsw_sp, MLXSW_SP_DEFAULT_AGEING_TIME);
if (err) {
dev_err(mlxsw_sp->bus_info->dev, "Failed to set default ageing time\n");
return err;
}
INIT_DELAYED_WORK(&mlxsw_sp->fdb_notify.dw, mlxsw_sp_fdb_notify_work);
mlxsw_sp->fdb_notify.interval = MLXSW_SP_DEFAULT_LEARNING_INTERVAL;
mlxsw_sp_fdb_notify_work_schedule(mlxsw_sp);
return 0;
}
static void mlxsw_sp_fdb_fini(struct mlxsw_sp *mlxsw_sp)
{
cancel_delayed_work_sync(&mlxsw_sp->fdb_notify.dw);
}
static void mlxsw_sp_fids_fini(struct mlxsw_sp *mlxsw_sp)
{
u16 fid;
for_each_set_bit(fid, mlxsw_sp->active_fids, VLAN_N_VID)
mlxsw_sp_fid_destroy(mlxsw_sp, fid);
}
int mlxsw_sp_switchdev_init(struct mlxsw_sp *mlxsw_sp)
{
return mlxsw_sp_fdb_init(mlxsw_sp);
}
void mlxsw_sp_switchdev_fini(struct mlxsw_sp *mlxsw_sp)
{
mlxsw_sp_fdb_fini(mlxsw_sp);
mlxsw_sp_fids_fini(mlxsw_sp);
}
int mlxsw_sp_port_vlan_init(struct mlxsw_sp_port *mlxsw_sp_port)
{
struct net_device *dev = mlxsw_sp_port->dev;
int err;
/* Allow only untagged packets to ingress and tag them internally
* with VID 1.
*/
mlxsw_sp_port->pvid = 1;
err = __mlxsw_sp_port_vlans_del(mlxsw_sp_port, 0, VLAN_N_VID, true);
if (err) {
netdev_err(dev, "Unable to init VLANs\n");
return err;
}
/* Add implicit VLAN interface in the device, so that untagged
* packets will be classified to the default vFID.
*/
err = mlxsw_sp_port_add_vid(dev, 0, 1);
if (err)
netdev_err(dev, "Failed to configure default vFID\n");
return err;
}
void mlxsw_sp_port_switchdev_init(struct mlxsw_sp_port *mlxsw_sp_port)
{
mlxsw_sp_port->dev->switchdev_ops = &mlxsw_sp_port_switchdev_ops;
}
void mlxsw_sp_port_switchdev_fini(struct mlxsw_sp_port *mlxsw_sp_port)
{
}

1
drivers/net/ethernet/mellanox/mlxsw/txheader.h
View File

@ -38,6 +38,7 @@
#define MLXSW_TXHDR_LEN 0x10
#define MLXSW_TXHDR_VERSION_0 0
#define MLXSW_TXHDR_VERSION_1 1
enum {
MLXSW_TXHDR_ETH_CTL,