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arm64: dts: freescale: Add support for i.MX8QXP AI_ML board
Add support for i.MX8QXP AI_ML board from Einfochips. This board is one of the Consumer Edition boards of the 96Boards family based on i.MX8QXP SoC from NXP/Freescale. The initial support includes following peripherals which are tested and known to be working: 1. Debug serial via UART2 2. uSD 3. WiFi 4. Ethernet More information about this board can be found in Arrow website: https://www.arrow.com/en/products/imx8-ai-ml/arrow-development-tools Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This commit is contained in:
Manivannan Sadhasivam
Shawn Guo
parent
b5547e22be
commit
56838644f9
@ -26,4 +26,5 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mq-librem5-devkit.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mq-zii-ultra-rmb3.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mq-zii-ultra-zest.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8qxp-ai_ml.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8qxp-mek.dtb
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249
arch/arm64/boot/dts/freescale/imx8qxp-ai_ml.dts
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249
arch/arm64/boot/dts/freescale/imx8qxp-ai_ml.dts
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@ -0,0 +1,249 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2018 Einfochips
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* Copyright 2019 Linaro Ltd.
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*/
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/dts-v1/;
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#include "imx8qxp.dtsi"
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/ {
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model = "Einfochips i.MX8QXP AI_ML";
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compatible = "einfochips,imx8qxp-ai_ml", "fsl,imx8qxp";
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aliases {
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serial1 = &adma_lpuart1;
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serial2 = &adma_lpuart2;
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serial3 = &adma_lpuart3;
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};
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chosen {
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stdout-path = &adma_lpuart2;
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};
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memory@80000000 {
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device_type = "memory";
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reg = <0x00000000 0x80000000 0 0x80000000>;
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};
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leds {
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compatible = "gpio-leds";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_leds>;
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user-led1 {
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label = "green:user1";
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gpios = <&lsio_gpio4 16 GPIO_ACTIVE_HIGH>;
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linux,default-trigger = "heartbeat";
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};
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user-led2 {
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label = "green:user2";
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gpios = <&lsio_gpio0 6 GPIO_ACTIVE_HIGH>;
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linux,default-trigger = "none";
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};
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user-led3 {
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label = "green:user3";
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gpios = <&lsio_gpio0 7 GPIO_ACTIVE_HIGH>;
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linux,default-trigger = "mmc1";
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default-state = "off";
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};
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user-led4 {
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label = "green:user4";
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gpios = <&lsio_gpio4 21 GPIO_ACTIVE_HIGH>;
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panic-indicator;
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linux,default-trigger = "none";
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};
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wlan-active-led {
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label = "yellow:wlan";
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gpios = <&lsio_gpio4 17 GPIO_ACTIVE_HIGH>;
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linux,default-trigger = "phy0tx";
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default-state = "off";
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};
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bt-active-led {
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label = "blue:bt";
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gpios = <&lsio_gpio4 18 GPIO_ACTIVE_HIGH>;
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linux,default-trigger = "hci0-power";
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default-state = "off";
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};
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};
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sdio_pwrseq: sdio-pwrseq {
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compatible = "mmc-pwrseq-simple";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_wifi_reg_on>;
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reset-gpios = <&lsio_gpio3 24 GPIO_ACTIVE_LOW>;
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};
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};
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/* BT */
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&adma_lpuart0 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_lpuart0>;
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uart-has-rtscts;
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status = "okay";
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};
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/* LS-UART0 */
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&adma_lpuart1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_lpuart1>;
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status = "okay";
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};
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/* Debug */
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&adma_lpuart2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_lpuart2>;
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status = "okay";
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};
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/* PCI-E UART */
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&adma_lpuart3 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_lpuart3>;
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status = "okay";
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};
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&fec1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_fec1>;
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phy-mode = "rgmii-id";
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phy-handle = <ðphy0>;
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fsl,magic-packet;
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status = "okay";
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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ethphy0: ethernet-phy@0 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <0>;
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};
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};
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};
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/* WiFi */
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&usdhc1 {
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#address-cells = <1>;
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#size-cells = <0>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usdhc1>;
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bus-width = <4>;
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no-sd;
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non-removable;
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mmc-pwrseq = <&sdio_pwrseq>;
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status = "okay";
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brcmf: wifi@1 {
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reg = <1>;
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compatible = "brcm,bcm4329-fmac";
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};
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};
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/* SD */
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&usdhc2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usdhc2>;
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bus-width = <4>;
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cd-gpios = <&lsio_gpio4 22 GPIO_ACTIVE_LOW>;
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status = "okay";
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};
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&iomuxc {
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pinctrl_fec1: fec1grp {
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fsl,pins = <
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IMX8QXP_ENET0_MDC_CONN_ENET0_MDC 0x06000020
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IMX8QXP_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020
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IMX8QXP_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x06000020
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IMX8QXP_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x06000020
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IMX8QXP_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x06000020
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IMX8QXP_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x06000020
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IMX8QXP_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x06000020
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IMX8QXP_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x06000020
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IMX8QXP_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x06000020
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IMX8QXP_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x06000020
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IMX8QXP_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x06000020
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IMX8QXP_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x06000020
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IMX8QXP_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x06000020
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IMX8QXP_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x06000020
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>;
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};
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pinctrl_leds: ledsgrp{
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fsl,pins = <
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IMX8QXP_ESAI0_TX2_RX3_LSIO_GPIO0_IO06 0x00000021
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IMX8QXP_ESAI0_TX3_RX2_LSIO_GPIO0_IO07 0x00000021
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IMX8QXP_EMMC0_DATA7_LSIO_GPIO4_IO16 0x00000021
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IMX8QXP_USDHC1_WP_LSIO_GPIO4_IO21 0x00000021
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IMX8QXP_EMMC0_STROBE_LSIO_GPIO4_IO17 0x00000021
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IMX8QXP_EMMC0_RESET_B_LSIO_GPIO4_IO18 0x00000021
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>;
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};
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pinctrl_lpuart0: lpuart0grp {
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fsl,pins = <
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IMX8QXP_UART0_RX_ADMA_UART0_RX 0X06000020
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IMX8QXP_UART0_TX_ADMA_UART0_TX 0X06000020
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IMX8QXP_FLEXCAN0_TX_ADMA_UART0_CTS_B 0x06000020
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IMX8QXP_FLEXCAN0_RX_ADMA_UART0_RTS_B 0x06000020
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>;
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};
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pinctrl_lpuart1: lpuart1grp {
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fsl,pins = <
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IMX8QXP_UART1_RX_ADMA_UART1_RX 0X06000020
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IMX8QXP_UART1_TX_ADMA_UART1_TX 0X06000020
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>;
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};
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pinctrl_lpuart2: lpuart2grp {
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fsl,pins = <
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IMX8QXP_UART2_RX_ADMA_UART2_RX 0X06000020
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IMX8QXP_UART2_TX_ADMA_UART2_TX 0X06000020
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>;
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};
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pinctrl_lpuart3: lpuart3grp {
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fsl,pins = <
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IMX8QXP_FLEXCAN2_RX_ADMA_UART3_RX 0X06000020
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IMX8QXP_FLEXCAN2_TX_ADMA_UART3_TX 0X06000020
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>;
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};
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pinctrl_usdhc1: usdhc1grp {
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fsl,pins = <
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IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041
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IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021
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IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021
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IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021
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IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021
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IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021
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>;
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};
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pinctrl_usdhc2: usdhc2grp {
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fsl,pins = <
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IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041
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IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021
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IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021
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IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021
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IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021
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IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021
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IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021
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IMX8QXP_USDHC1_CD_B_LSIO_GPIO4_IO22 0x00000021
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>;
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};
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pinctrl_wifi_reg_on: wifiregongrp {
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fsl,pins = <
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IMX8QXP_QSPI0B_SS1_B_LSIO_GPIO3_IO24 0x00000021
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>;
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};
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};
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