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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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mtd: spi-nor: Prepend spi_nor_ to all Reg Ops methods
All the core functions should begin with "spi_nor_". Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
This commit is contained in:
Tudor Ambarus
parent
a5c6603038
commit
567c2983ef
@ -393,7 +393,7 @@ static ssize_t spi_nor_write_data(struct spi_nor *nor, loff_t to, size_t len,
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* Return the status register value.
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* Returns negative if error occurred.
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*/
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static int read_sr(struct spi_nor *nor)
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static int spi_nor_read_sr(struct spi_nor *nor)
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{
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int ret;
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@ -423,7 +423,7 @@ static int read_sr(struct spi_nor *nor)
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* Return the status register value.
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* Returns negative if error occurred.
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*/
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static int read_fsr(struct spi_nor *nor)
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static int spi_nor_read_fsr(struct spi_nor *nor)
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{
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int ret;
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@ -453,7 +453,7 @@ static int read_fsr(struct spi_nor *nor)
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* location. Return the configuration register value.
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* Returns negative if error occurred.
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*/
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static int read_cr(struct spi_nor *nor)
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static int spi_nor_read_cr(struct spi_nor *nor)
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{
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int ret;
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@ -482,7 +482,7 @@ static int read_cr(struct spi_nor *nor)
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* Write status register 1 byte
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* Returns negative if error occurred.
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*/
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static int write_sr(struct spi_nor *nor, u8 val)
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static int spi_nor_write_sr(struct spi_nor *nor, u8 val)
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{
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nor->bouncebuf[0] = val;
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if (nor->spimem) {
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@ -503,7 +503,7 @@ static int write_sr(struct spi_nor *nor, u8 val)
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* Set write enable latch with Write Enable command.
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* Returns negative if error occurred.
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*/
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static int write_enable(struct spi_nor *nor)
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static int spi_nor_write_enable(struct spi_nor *nor)
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{
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if (nor->spimem) {
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struct spi_mem_op op =
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@ -521,7 +521,7 @@ static int write_enable(struct spi_nor *nor)
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/*
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* Send write disable instruction to the chip.
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*/
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static int write_disable(struct spi_nor *nor)
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static int spi_nor_write_disable(struct spi_nor *nor)
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{
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if (nor->spimem) {
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struct spi_mem_op op =
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@ -644,9 +644,9 @@ static int st_micron_set_4byte(struct spi_nor *nor, bool enable)
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{
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int ret;
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write_enable(nor);
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spi_nor_write_enable(nor);
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ret = macronix_set_4byte(nor, enable);
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write_disable(nor);
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spi_nor_write_disable(nor);
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return ret;
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}
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@ -700,9 +700,9 @@ static int winbond_set_4byte(struct spi_nor *nor, bool enable)
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* Register to be set to 1, so all 3-byte-address reads come from the
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* second 16M. We must clear the register to enable normal behavior.
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*/
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write_enable(nor);
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spi_nor_write_enable(nor);
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ret = spi_nor_write_ear(nor, 0);
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write_disable(nor);
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spi_nor_write_disable(nor);
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return ret;
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}
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@ -752,7 +752,7 @@ static int spi_nor_clear_sr(struct spi_nor *nor)
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static int spi_nor_sr_ready(struct spi_nor *nor)
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{
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int sr = read_sr(nor);
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int sr = spi_nor_read_sr(nor);
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if (sr < 0)
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return sr;
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@ -786,7 +786,7 @@ static int spi_nor_clear_fsr(struct spi_nor *nor)
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static int spi_nor_fsr_ready(struct spi_nor *nor)
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{
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int fsr = read_fsr(nor);
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int fsr = spi_nor_read_fsr(nor);
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if (fsr < 0)
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return fsr;
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@ -864,7 +864,7 @@ static int spi_nor_wait_till_ready(struct spi_nor *nor)
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*
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* Returns 0 if successful, non-zero otherwise.
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*/
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static int erase_chip(struct spi_nor *nor)
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static int spi_nor_erase_chip(struct spi_nor *nor)
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{
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dev_dbg(nor->dev, " %lldKiB\n", (long long)(nor->mtd.size >> 10));
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@ -1215,7 +1215,7 @@ static int spi_nor_erase_multi_sectors(struct spi_nor *nor, u64 addr, u32 len)
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list_for_each_entry_safe(cmd, next, &erase_list, list) {
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nor->erase_opcode = cmd->opcode;
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while (cmd->count) {
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write_enable(nor);
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spi_nor_write_enable(nor);
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ret = spi_nor_erase_sector(nor, addr);
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if (ret)
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@ -1270,9 +1270,9 @@ static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr)
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if (len == mtd->size && !(nor->flags & SNOR_F_NO_OP_CHIP_ERASE)) {
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unsigned long timeout;
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write_enable(nor);
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spi_nor_write_enable(nor);
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if (erase_chip(nor)) {
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if (spi_nor_erase_chip(nor)) {
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ret = -EIO;
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goto erase_err;
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}
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@ -1298,7 +1298,7 @@ static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr)
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/* "sector"-at-a-time erase */
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} else if (spi_nor_has_uniform_erase(nor)) {
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while (len) {
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write_enable(nor);
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spi_nor_write_enable(nor);
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ret = spi_nor_erase_sector(nor, addr);
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if (ret)
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@ -1319,7 +1319,7 @@ static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr)
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goto erase_err;
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}
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write_disable(nor);
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spi_nor_write_disable(nor);
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erase_err:
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spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_ERASE);
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@ -1328,12 +1328,13 @@ static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr)
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}
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/* Write status register and ensure bits in mask match written values */
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static int write_sr_and_check(struct spi_nor *nor, u8 status_new, u8 mask)
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static int spi_nor_write_sr_and_check(struct spi_nor *nor, u8 status_new,
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u8 mask)
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{
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int ret;
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write_enable(nor);
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ret = write_sr(nor, status_new);
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spi_nor_write_enable(nor);
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ret = spi_nor_write_sr(nor, status_new);
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if (ret)
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return ret;
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@ -1341,7 +1342,7 @@ static int write_sr_and_check(struct spi_nor *nor, u8 status_new, u8 mask)
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if (ret)
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return ret;
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ret = read_sr(nor);
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ret = spi_nor_read_sr(nor);
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if (ret < 0)
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return ret;
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@ -1447,7 +1448,7 @@ static int stm_lock(struct spi_nor *nor, loff_t ofs, uint64_t len)
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bool can_be_top = true, can_be_bottom = nor->flags & SNOR_F_HAS_SR_TB;
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bool use_top;
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status_old = read_sr(nor);
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status_old = spi_nor_read_sr(nor);
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if (status_old < 0)
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return status_old;
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@ -1509,7 +1510,7 @@ static int stm_lock(struct spi_nor *nor, loff_t ofs, uint64_t len)
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if ((status_new & mask) < (status_old & mask))
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return -EINVAL;
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return write_sr_and_check(nor, status_new, mask);
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return spi_nor_write_sr_and_check(nor, status_new, mask);
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}
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/*
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@ -1527,7 +1528,7 @@ static int stm_unlock(struct spi_nor *nor, loff_t ofs, uint64_t len)
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bool can_be_top = true, can_be_bottom = nor->flags & SNOR_F_HAS_SR_TB;
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bool use_top;
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status_old = read_sr(nor);
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status_old = spi_nor_read_sr(nor);
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if (status_old < 0)
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return status_old;
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@ -1592,7 +1593,7 @@ static int stm_unlock(struct spi_nor *nor, loff_t ofs, uint64_t len)
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if ((status_new & mask) > (status_old & mask))
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return -EINVAL;
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return write_sr_and_check(nor, status_new, mask);
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return spi_nor_write_sr_and_check(nor, status_new, mask);
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}
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/*
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@ -1606,7 +1607,7 @@ static int stm_is_locked(struct spi_nor *nor, loff_t ofs, uint64_t len)
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{
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int status;
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status = read_sr(nor);
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status = spi_nor_read_sr(nor);
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if (status < 0)
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return status;
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@ -1670,11 +1671,11 @@ static int spi_nor_is_locked(struct mtd_info *mtd, loff_t ofs, uint64_t len)
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* second byte will be written to the configuration register.
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* Return negative if error occurred.
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*/
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static int write_sr_cr(struct spi_nor *nor, u8 *sr_cr)
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static int spi_nor_write_sr_cr(struct spi_nor *nor, u8 *sr_cr)
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{
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int ret;
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write_enable(nor);
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spi_nor_write_enable(nor);
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if (nor->spimem) {
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struct spi_mem_op op =
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@ -1719,21 +1720,21 @@ static int macronix_quad_enable(struct spi_nor *nor)
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{
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int ret, val;
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val = read_sr(nor);
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val = spi_nor_read_sr(nor);
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if (val < 0)
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return val;
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if (val & SR_QUAD_EN_MX)
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return 0;
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write_enable(nor);
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spi_nor_write_enable(nor);
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write_sr(nor, val | SR_QUAD_EN_MX);
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spi_nor_write_sr(nor, val | SR_QUAD_EN_MX);
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ret = spi_nor_wait_till_ready(nor);
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if (ret)
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return ret;
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ret = read_sr(nor);
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ret = spi_nor_read_sr(nor);
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if (!(ret > 0 && (ret & SR_QUAD_EN_MX))) {
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dev_err(nor->dev, "Macronix Quad bit not set\n");
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return -EINVAL;
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@ -1758,7 +1759,8 @@ static int macronix_quad_enable(struct spi_nor *nor)
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* some very old and few memories don't support this instruction. If a pull-up
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* resistor is present on the MISO/IO1 line, we might still be able to pass the
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* "read back" test because the QSPI memory doesn't recognize the command,
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* so leaves the MISO/IO1 line state unchanged, hence read_cr() returns 0xFF.
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* so leaves the MISO/IO1 line state unchanged, hence spi_nor_read_cr() returns
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* 0xFF.
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*
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* bit 1 of the Configuration Register is the QE bit for Spansion like QSPI
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* memories.
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@ -1772,12 +1774,12 @@ static int spansion_quad_enable(struct spi_nor *nor)
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sr_cr[0] = 0;
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sr_cr[1] = CR_QUAD_EN_SPAN;
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ret = write_sr_cr(nor, sr_cr);
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ret = spi_nor_write_sr_cr(nor, sr_cr);
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if (ret)
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return ret;
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/* read back and check it */
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ret = read_cr(nor);
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ret = spi_nor_read_cr(nor);
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if (!(ret > 0 && (ret & CR_QUAD_EN_SPAN))) {
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dev_err(nor->dev, "Spansion Quad bit not set\n");
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return -EINVAL;
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@ -1805,7 +1807,7 @@ static int spansion_no_read_cr_quad_enable(struct spi_nor *nor)
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int ret;
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/* Keep the current value of the Status Register. */
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ret = read_sr(nor);
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ret = spi_nor_read_sr(nor);
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if (ret < 0) {
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dev_err(nor->dev, "error while reading status register\n");
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return -EINVAL;
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@ -1813,7 +1815,7 @@ static int spansion_no_read_cr_quad_enable(struct spi_nor *nor)
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sr_cr[0] = ret;
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sr_cr[1] = CR_QUAD_EN_SPAN;
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return write_sr_cr(nor, sr_cr);
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return spi_nor_write_sr_cr(nor, sr_cr);
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}
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/**
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@ -1836,7 +1838,7 @@ static int spansion_read_cr_quad_enable(struct spi_nor *nor)
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int ret;
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/* Check current Quad Enable bit value. */
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ret = read_cr(nor);
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ret = spi_nor_read_cr(nor);
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if (ret < 0) {
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dev_err(dev, "error while reading configuration register\n");
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return -EINVAL;
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@ -1848,19 +1850,19 @@ static int spansion_read_cr_quad_enable(struct spi_nor *nor)
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sr_cr[1] = ret | CR_QUAD_EN_SPAN;
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/* Keep the current value of the Status Register. */
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ret = read_sr(nor);
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ret = spi_nor_read_sr(nor);
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if (ret < 0) {
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dev_err(dev, "error while reading status register\n");
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return -EINVAL;
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}
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sr_cr[0] = ret;
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ret = write_sr_cr(nor, sr_cr);
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ret = spi_nor_write_sr_cr(nor, sr_cr);
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if (ret)
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return ret;
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/* Read back and check it. */
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ret = read_cr(nor);
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ret = spi_nor_read_cr(nor);
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if (!(ret > 0 && (ret & CR_QUAD_EN_SPAN))) {
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dev_err(nor->dev, "Spansion Quad bit not set\n");
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return -EINVAL;
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@ -1926,7 +1928,7 @@ static int sr2_bit7_quad_enable(struct spi_nor *nor)
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/* Update the Quad Enable bit. */
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*sr2 |= SR2_QUAD_EN_BIT7;
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write_enable(nor);
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spi_nor_write_enable(nor);
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ret = spi_nor_write_sr2(nor, sr2);
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if (ret < 0) {
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@ -1964,15 +1966,15 @@ static int spi_nor_clear_sr_bp(struct spi_nor *nor)
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int ret;
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u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
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ret = read_sr(nor);
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ret = spi_nor_read_sr(nor);
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if (ret < 0) {
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dev_err(nor->dev, "error while reading status register\n");
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return ret;
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}
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write_enable(nor);
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spi_nor_write_enable(nor);
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ret = write_sr(nor, ret & ~mask);
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ret = spi_nor_write_sr(nor, ret & ~mask);
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if (ret) {
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dev_err(nor->dev, "write to status register failed\n");
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return ret;
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@ -2004,7 +2006,7 @@ static int spi_nor_spansion_clear_sr_bp(struct spi_nor *nor)
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u8 *sr_cr = nor->bouncebuf;
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/* Check current Quad Enable bit value. */
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ret = read_cr(nor);
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ret = spi_nor_read_cr(nor);
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if (ret < 0) {
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dev_err(nor->dev,
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"error while reading configuration register\n");
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@ -2018,7 +2020,7 @@ static int spi_nor_spansion_clear_sr_bp(struct spi_nor *nor)
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if (ret & CR_QUAD_EN_SPAN) {
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sr_cr[1] = ret;
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ret = read_sr(nor);
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ret = spi_nor_read_sr(nor);
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if (ret < 0) {
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dev_err(nor->dev,
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"error while reading status register\n");
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@ -2026,7 +2028,7 @@ static int spi_nor_spansion_clear_sr_bp(struct spi_nor *nor)
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}
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sr_cr[0] = ret & ~mask;
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ret = write_sr_cr(nor, sr_cr);
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ret = spi_nor_write_sr_cr(nor, sr_cr);
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if (ret)
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dev_err(nor->dev, "16-bit write register failed\n");
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return ret;
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@ -2602,7 +2604,7 @@ static int sst_write(struct mtd_info *mtd, loff_t to, size_t len,
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if (ret)
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return ret;
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write_enable(nor);
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spi_nor_write_enable(nor);
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nor->sst_write_second = false;
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@ -2641,14 +2643,14 @@ static int sst_write(struct mtd_info *mtd, loff_t to, size_t len,
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}
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nor->sst_write_second = false;
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write_disable(nor);
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spi_nor_write_disable(nor);
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ret = spi_nor_wait_till_ready(nor);
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if (ret)
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goto sst_write_err;
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/* Write out trailing byte if it exists. */
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if (actual != len) {
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write_enable(nor);
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spi_nor_write_enable(nor);
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nor->program_opcode = SPINOR_OP_BP;
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ret = spi_nor_write_data(nor, to, 1, buf + actual);
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@ -2659,7 +2661,7 @@ static int sst_write(struct mtd_info *mtd, loff_t to, size_t len,
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ret = spi_nor_wait_till_ready(nor);
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if (ret)
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goto sst_write_err;
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write_disable(nor);
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spi_nor_write_disable(nor);
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actual += 1;
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}
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sst_write_err:
|
||||
@ -2711,7 +2713,7 @@ static int spi_nor_write(struct mtd_info *mtd, loff_t to, size_t len,
|
||||
|
||||
addr = spi_nor_convert_addr(nor, addr);
|
||||
|
||||
write_enable(nor);
|
||||
spi_nor_write_enable(nor);
|
||||
ret = spi_nor_write_data(nor, addr, page_remain, buf + i);
|
||||
if (ret < 0)
|
||||
goto write_err;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user