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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-28 11:18:45 +07:00
amdgpu/dc: fix a bunch of misc whitespace.
This just aligns a few things with kernel style. Signed-off-by: Dave Airlie <airlied@redhat.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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parent
2016b641f4
commit
5667ff5c11
drivers/gpu/drm/amd/display
@ -1473,10 +1473,10 @@ void decide_link_settings(struct dc_stream_state *stream,
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return;
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}
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/* search for the minimum link setting that:
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* 1. is supported according to the link training result
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* 2. could support the b/w requested by the timing
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*/
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/* search for the minimum link setting that:
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* 1. is supported according to the link training result
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* 2. could support the b/w requested by the timing
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*/
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while (current_link_setting.link_rate <=
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link->verified_link_cap.link_rate) {
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link_bw = bandwidth_in_kbps_from_link_settings(
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@ -429,14 +429,14 @@ union audio_sample_rates {
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};
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struct audio_speaker_flags {
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uint32_t FL_FR:1;
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uint32_t LFE:1;
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uint32_t FC:1;
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uint32_t RL_RR:1;
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uint32_t RC:1;
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uint32_t FLC_FRC:1;
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uint32_t RLC_RRC:1;
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uint32_t SUPPORT_AI:1;
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uint32_t FL_FR:1;
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uint32_t LFE:1;
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uint32_t FC:1;
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uint32_t RL_RR:1;
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uint32_t RC:1;
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uint32_t FLC_FRC:1;
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uint32_t RLC_RRC:1;
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uint32_t SUPPORT_AI:1;
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};
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struct audio_speaker_info {
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@ -1238,8 +1238,8 @@ void dce110_timing_generator_setup_global_swap_lock(
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DCP_GSL_CONTROL,
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DCP_GSL_HSYNC_FLIP_FORCE_DELAY);
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/* Keep signal low (pending high) during 6 lines.
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* Also defines minimum interval before re-checking signal. */
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/* Keep signal low (pending high) during 6 lines.
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* Also defines minimum interval before re-checking signal. */
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set_reg_field_value(value,
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HFLIP_CHECK_DELAY,
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DCP_GSL_CONTROL,
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@ -2396,14 +2396,14 @@ static void program_all_pipe_in_tree(
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dcn10_power_on_fe(dc, pipe_ctx, context);
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/* temporary dcn1 wa:
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* watermark update requires toggle after a/b/c/d sets are programmed
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* if hubp is pg then wm value doesn't get properaged to hubp
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* need to toggle after ungate to ensure wm gets to hubp.
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*
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* final solution: we need to get SMU to do the toggle as
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* DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST is owned by SMU we should have
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* both driver and fw accessing same register
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*/
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* watermark update requires toggle after a/b/c/d sets are programmed
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* if hubp is pg then wm value doesn't get properaged to hubp
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* need to toggle after ungate to ensure wm gets to hubp.
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*
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* final solution: we need to get SMU to do the toggle as
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* DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST is owned by SMU we should have
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* both driver and fw accessing same register
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*/
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toggle_watermark_change_req(dc->hwseq);
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update_dchubp_dpp(dc, pipe_ctx, context);
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@ -697,37 +697,37 @@ static void min10_set_vm_context0_settings(struct mem_input *mem_input,
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}
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static void min_set_viewport(
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struct mem_input *mem_input,
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const struct rect *viewport,
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const struct rect *viewport_c)
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struct mem_input *mem_input,
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const struct rect *viewport,
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const struct rect *viewport_c)
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{
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struct dcn10_mem_input *mi = TO_DCN10_MEM_INPUT(mem_input);
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REG_SET_2(DCSURF_PRI_VIEWPORT_DIMENSION, 0,
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PRI_VIEWPORT_WIDTH, viewport->width,
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PRI_VIEWPORT_HEIGHT, viewport->height);
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REG_SET_2(DCSURF_PRI_VIEWPORT_DIMENSION, 0,
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PRI_VIEWPORT_WIDTH, viewport->width,
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PRI_VIEWPORT_HEIGHT, viewport->height);
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REG_SET_2(DCSURF_PRI_VIEWPORT_START, 0,
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PRI_VIEWPORT_X_START, viewport->x,
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PRI_VIEWPORT_Y_START, viewport->y);
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REG_SET_2(DCSURF_PRI_VIEWPORT_START, 0,
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PRI_VIEWPORT_X_START, viewport->x,
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PRI_VIEWPORT_Y_START, viewport->y);
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/*for stereo*/
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REG_SET_2(DCSURF_SEC_VIEWPORT_DIMENSION, 0,
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SEC_VIEWPORT_WIDTH, viewport->width,
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SEC_VIEWPORT_HEIGHT, viewport->height);
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/*for stereo*/
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REG_SET_2(DCSURF_SEC_VIEWPORT_DIMENSION, 0,
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SEC_VIEWPORT_WIDTH, viewport->width,
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SEC_VIEWPORT_HEIGHT, viewport->height);
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REG_SET_2(DCSURF_SEC_VIEWPORT_START, 0,
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SEC_VIEWPORT_X_START, viewport->x,
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SEC_VIEWPORT_Y_START, viewport->y);
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REG_SET_2(DCSURF_SEC_VIEWPORT_START, 0,
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SEC_VIEWPORT_X_START, viewport->x,
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SEC_VIEWPORT_Y_START, viewport->y);
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/* DC supports NV12 only at the moment */
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REG_SET_2(DCSURF_PRI_VIEWPORT_DIMENSION_C, 0,
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PRI_VIEWPORT_WIDTH_C, viewport_c->width,
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PRI_VIEWPORT_HEIGHT_C, viewport_c->height);
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/* DC supports NV12 only at the moment */
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REG_SET_2(DCSURF_PRI_VIEWPORT_DIMENSION_C, 0,
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PRI_VIEWPORT_WIDTH_C, viewport_c->width,
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PRI_VIEWPORT_HEIGHT_C, viewport_c->height);
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REG_SET_2(DCSURF_PRI_VIEWPORT_START_C, 0,
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PRI_VIEWPORT_X_START_C, viewport_c->x,
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PRI_VIEWPORT_Y_START_C, viewport_c->y);
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REG_SET_2(DCSURF_PRI_VIEWPORT_START_C, 0,
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PRI_VIEWPORT_X_START_C, viewport_c->x,
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PRI_VIEWPORT_Y_START_C, viewport_c->y);
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}
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void dcn10_mem_input_read_state(struct dcn10_mem_input *mi,
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@ -183,9 +183,9 @@ struct dc_firmware_info {
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};
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struct step_and_delay_info {
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uint32_t step;
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uint32_t delay;
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uint32_t recommended_ref_div;
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uint32_t step;
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uint32_t delay;
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uint32_t recommended_ref_div;
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};
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struct spread_spectrum_info {
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@ -266,16 +266,16 @@ struct transmitter_configuration {
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#define NUMBER_OF_AVAILABLE_SCLK 5
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struct i2c_reg_info {
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unsigned char i2c_reg_index;
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unsigned char i2c_reg_val;
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unsigned char i2c_reg_index;
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unsigned char i2c_reg_val;
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};
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struct ext_hdmi_settings {
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unsigned char slv_addr;
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unsigned char reg_num;
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struct i2c_reg_info reg_settings[9];
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unsigned char reg_num_6g;
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struct i2c_reg_info reg_settings_6g[3];
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unsigned char slv_addr;
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unsigned char reg_num;
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struct i2c_reg_info reg_settings[9];
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unsigned char reg_num_6g;
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struct i2c_reg_info reg_settings_6g[3];
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};
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