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clk: qcom: add video clock controller driver for SM8150

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Add support for the video clock controller found on SM8150 based devices.

Derived from the downstream driver.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Link: https://lore.kernel.org/r/20200923160635.28370-5-jonathan@marek.ca
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This commit is contained in:
Jonathan Marek 2020-09-23 12:06:30 -04:00 committed by Stephen Boyd
parent dafb992a95
commit 5658e8cf1a
3 changed files with 286 additions and 0 deletions
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9
drivers/clk/qcom/Kconfig
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@ -444,6 +444,15 @@ config SM_GPUCC_8250
Say Y if you want to support graphics controller devices and
functionality such as 3D graphics.
config SM_VIDEOCC_8150
tristate "SM8150 Video Clock Controller"
select SDM_GCC_8150
select QCOM_GDSC
help
Support for the video clock controller on SM8150 devices.
Say Y if you want to support video devices and functionality such as
video encode and decode.
config SPMI_PMIC_CLKDIV
tristate "SPMI PMIC clkdiv Support"
depends on SPMI || COMPILE_TEST

1
drivers/clk/qcom/Makefile
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@ -68,6 +68,7 @@ obj-$(CONFIG_SM_GCC_8150) += gcc-sm8150.o
obj-$(CONFIG_SM_GCC_8250) += gcc-sm8250.o
obj-$(CONFIG_SM_GPUCC_8150) += gpucc-sm8150.o
obj-$(CONFIG_SM_GPUCC_8250) += gpucc-sm8250.o
obj-$(CONFIG_SM_VIDEOCC_8150) += videocc-sm8150.o
obj-$(CONFIG_SPMI_PMIC_CLKDIV) += clk-spmi-pmic-div.o
obj-$(CONFIG_KPSS_XCC) += kpss-xcc.o
obj-$(CONFIG_QCOM_HFPLL) += hfpll.o

276
drivers/clk/qcom/videocc-sm8150.c Normal file
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@ -0,0 +1,276 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.
*/
#include <linux/clk-provider.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <dt-bindings/clock/qcom,videocc-sm8150.h>
#include "common.h"
#include "clk-alpha-pll.h"
#include "clk-branch.h"
#include "clk-rcg.h"
#include "clk-regmap.h"
#include "reset.h"
#include "gdsc.h"
enum {
P_BI_TCXO,
P_CHIP_SLEEP_CLK,
P_CORE_BI_PLL_TEST_SE,
P_VIDEO_PLL0_OUT_EVEN,
P_VIDEO_PLL0_OUT_MAIN,
P_VIDEO_PLL0_OUT_ODD,
};
static struct pll_vco trion_vco[] = {
{ 249600000, 2000000000, 0 },
};
static struct alpha_pll_config video_pll0_config = {
.l = 0x14,
.alpha = 0xD555,
.config_ctl_val = 0x20485699,
.config_ctl_hi_val = 0x00002267,
.config_ctl_hi1_val = 0x00000024,
.user_ctl_val = 0x00000000,
.user_ctl_hi_val = 0x00000805,
.user_ctl_hi1_val = 0x000000D0,
};
static struct clk_alpha_pll video_pll0 = {
.offset = 0x42c,
.vco_table = trion_vco,
.num_vco = ARRAY_SIZE(trion_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION],
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "video_pll0",
.parent_data = &(const struct clk_parent_data){
.fw_name = "bi_tcxo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_trion_ops,
},
},
};
static const struct parent_map video_cc_parent_map_0[] = {
{ P_BI_TCXO, 0 },
{ P_VIDEO_PLL0_OUT_MAIN, 1 },
};
static const struct clk_parent_data video_cc_parent_data_0[] = {
{ .fw_name = "bi_tcxo" },
{ .hw = &video_pll0.clkr.hw },
};
static const struct freq_tbl ftbl_video_cc_iris_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(200000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0),
F(240000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0),
F(338000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0),
F(365000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0),
F(444000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0),
F(533000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0),
{ }
};
static struct clk_rcg2 video_cc_iris_clk_src = {
.cmd_rcgr = 0x7f0,
.mnd_width = 0,
.hid_width = 5,
.parent_map = video_cc_parent_map_0,
.freq_tbl = ftbl_video_cc_iris_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "video_cc_iris_clk_src",
.parent_data = video_cc_parent_data_0,
.num_parents = ARRAY_SIZE(video_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_branch video_cc_iris_ahb_clk = {
.halt_reg = 0x8f4,
.halt_check = BRANCH_VOTED,
.clkr = {
.enable_reg = 0x8f4,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "video_cc_iris_ahb_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &video_cc_iris_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch video_cc_mvs0_core_clk = {
.halt_reg = 0x890,
.halt_check = BRANCH_VOTED,
.clkr = {
.enable_reg = 0x890,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "video_cc_mvs0_core_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &video_cc_iris_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch video_cc_mvs1_core_clk = {
.halt_reg = 0x8d0,
.halt_check = BRANCH_VOTED,
.clkr = {
.enable_reg = 0x8d0,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "video_cc_mvs1_core_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &video_cc_iris_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch video_cc_mvsc_core_clk = {
.halt_reg = 0x850,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x850,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "video_cc_mvsc_core_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &video_cc_iris_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct gdsc venus_gdsc = {
.gdscr = 0x814,
.pd = {
.name = "venus_gdsc",
},
.flags = 0,
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc vcodec0_gdsc = {
.gdscr = 0x874,
.pd = {
.name = "vcodec0_gdsc",
},
.flags = HW_CTRL,
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc vcodec1_gdsc = {
.gdscr = 0x8b4,
.pd = {
.name = "vcodec1_gdsc",
},
.flags = HW_CTRL,
.pwrsts = PWRSTS_OFF_ON,
};
static struct clk_regmap *video_cc_sm8150_clocks[] = {
[VIDEO_CC_IRIS_AHB_CLK] = &video_cc_iris_ahb_clk.clkr,
[VIDEO_CC_IRIS_CLK_SRC] = &video_cc_iris_clk_src.clkr,
[VIDEO_CC_MVS0_CORE_CLK] = &video_cc_mvs0_core_clk.clkr,
[VIDEO_CC_MVS1_CORE_CLK] = &video_cc_mvs1_core_clk.clkr,
[VIDEO_CC_MVSC_CORE_CLK] = &video_cc_mvsc_core_clk.clkr,
[VIDEO_CC_PLL0] = &video_pll0.clkr,
};
static struct gdsc *video_cc_sm8150_gdscs[] = {
[VENUS_GDSC] = &venus_gdsc,
[VCODEC0_GDSC] = &vcodec0_gdsc,
[VCODEC1_GDSC] = &vcodec1_gdsc,
};
static const struct regmap_config video_cc_sm8150_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0xb94,
.fast_io = true,
};
static const struct qcom_reset_map video_cc_sm8150_resets[] = {
[VIDEO_CC_MVSC_CORE_CLK_BCR] = { 0x850, 2 },
};
static const struct qcom_cc_desc video_cc_sm8150_desc = {
.config = &video_cc_sm8150_regmap_config,
.clks = video_cc_sm8150_clocks,
.num_clks = ARRAY_SIZE(video_cc_sm8150_clocks),
.resets = video_cc_sm8150_resets,
.num_resets = ARRAY_SIZE(video_cc_sm8150_resets),
.gdscs = video_cc_sm8150_gdscs,
.num_gdscs = ARRAY_SIZE(video_cc_sm8150_gdscs),
};
static const struct of_device_id video_cc_sm8150_match_table[] = {
{ .compatible = "qcom,sm8150-videocc" },
{ }
};
MODULE_DEVICE_TABLE(of, video_cc_sm8150_match_table);
static int video_cc_sm8150_probe(struct platform_device *pdev)
{
struct regmap *regmap;
regmap = qcom_cc_map(pdev, &video_cc_sm8150_desc);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
clk_trion_pll_configure(&video_pll0, regmap, &video_pll0_config);
/* Keep VIDEO_CC_XO_CLK ALWAYS-ON */
regmap_update_bits(regmap, 0x984, 0x1, 0x1);
return qcom_cc_really_probe(pdev, &video_cc_sm8150_desc, regmap);
}
static struct platform_driver video_cc_sm8150_driver = {
.probe = video_cc_sm8150_probe,
.driver = {
.name = "video_cc-sm8150",
.of_match_table = video_cc_sm8150_match_table,
},
};
static int __init video_cc_sm8150_init(void)
{
return platform_driver_register(&video_cc_sm8150_driver);
}
subsys_initcall(video_cc_sm8150_init);
static void __exit video_cc_sm8150_exit(void)
{
platform_driver_unregister(&video_cc_sm8150_driver);
}
module_exit(video_cc_sm8150_exit);
MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("QTI VIDEOCC SM8150 Driver");