mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-11-25 22:10:49 +07:00
ARM: EXYNOS: Remove unused static uart resource information
All supported EXYNOS5 platforms are device tree enabled and hence the unused static uart resource information is removed. Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> [kgene.kim@samsung.com: changed to exynos4_init_uarts() clearly] Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This commit is contained in:
parent
fe267b8781
commit
55b6ef7a7d
@ -62,7 +62,7 @@ static void exynos4_map_io(void);
|
||||
static void exynos5_map_io(void);
|
||||
static void exynos4_init_clocks(int xtal);
|
||||
static void exynos5_init_clocks(int xtal);
|
||||
static void exynos_init_uarts(struct s3c2410_uartcfg *cfg, int no);
|
||||
static void exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no);
|
||||
static int exynos_init(void);
|
||||
|
||||
static struct cpu_table cpu_ids[] __initdata = {
|
||||
@ -71,7 +71,7 @@ static struct cpu_table cpu_ids[] __initdata = {
|
||||
.idmask = EXYNOS4_CPU_MASK,
|
||||
.map_io = exynos4_map_io,
|
||||
.init_clocks = exynos4_init_clocks,
|
||||
.init_uarts = exynos_init_uarts,
|
||||
.init_uarts = exynos4_init_uarts,
|
||||
.init = exynos_init,
|
||||
.name = name_exynos4210,
|
||||
}, {
|
||||
@ -79,7 +79,7 @@ static struct cpu_table cpu_ids[] __initdata = {
|
||||
.idmask = EXYNOS4_CPU_MASK,
|
||||
.map_io = exynos4_map_io,
|
||||
.init_clocks = exynos4_init_clocks,
|
||||
.init_uarts = exynos_init_uarts,
|
||||
.init_uarts = exynos4_init_uarts,
|
||||
.init = exynos_init,
|
||||
.name = name_exynos4212,
|
||||
}, {
|
||||
@ -87,7 +87,7 @@ static struct cpu_table cpu_ids[] __initdata = {
|
||||
.idmask = EXYNOS4_CPU_MASK,
|
||||
.map_io = exynos4_map_io,
|
||||
.init_clocks = exynos4_init_clocks,
|
||||
.init_uarts = exynos_init_uarts,
|
||||
.init_uarts = exynos4_init_uarts,
|
||||
.init = exynos_init,
|
||||
.name = name_exynos4412,
|
||||
}, {
|
||||
@ -95,7 +95,6 @@ static struct cpu_table cpu_ids[] __initdata = {
|
||||
.idmask = EXYNOS5_SOC_MASK,
|
||||
.map_io = exynos5_map_io,
|
||||
.init_clocks = exynos5_init_clocks,
|
||||
.init_uarts = exynos_init_uarts,
|
||||
.init = exynos_init,
|
||||
.name = name_exynos5250,
|
||||
},
|
||||
@ -707,7 +706,7 @@ static int __init exynos_init(void)
|
||||
|
||||
/* uart registration process */
|
||||
|
||||
static void __init exynos_init_uarts(struct s3c2410_uartcfg *cfg, int no)
|
||||
static void __init exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no)
|
||||
{
|
||||
struct s3c2410_uartcfg *tcfg = cfg;
|
||||
u32 ucnt;
|
||||
@ -715,10 +714,7 @@ static void __init exynos_init_uarts(struct s3c2410_uartcfg *cfg, int no)
|
||||
for (ucnt = 0; ucnt < no; ucnt++, tcfg++)
|
||||
tcfg->has_fracval = 1;
|
||||
|
||||
if (soc_is_exynos5250())
|
||||
s3c24xx_init_uartdevs("exynos4210-uart", exynos5_uart_resources, cfg, no);
|
||||
else
|
||||
s3c24xx_init_uartdevs("exynos4210-uart", exynos4_uart_resources, cfg, no);
|
||||
s3c24xx_init_uartdevs("exynos4210-uart", exynos4_uart_resources, cfg, no);
|
||||
}
|
||||
|
||||
static void __iomem *exynos_eint_base;
|
||||
|
@ -52,27 +52,3 @@ struct s3c24xx_uart_resources exynos4_uart_resources[] __initdata = {
|
||||
.nr_resources = ARRAY_SIZE(exynos4_uart3_resource),
|
||||
},
|
||||
};
|
||||
|
||||
EXYNOS_UART_RESOURCE(5, 0)
|
||||
EXYNOS_UART_RESOURCE(5, 1)
|
||||
EXYNOS_UART_RESOURCE(5, 2)
|
||||
EXYNOS_UART_RESOURCE(5, 3)
|
||||
|
||||
struct s3c24xx_uart_resources exynos5_uart_resources[] __initdata = {
|
||||
[0] = {
|
||||
.resources = exynos5_uart0_resource,
|
||||
.nr_resources = ARRAY_SIZE(exynos5_uart0_resource),
|
||||
},
|
||||
[1] = {
|
||||
.resources = exynos5_uart1_resource,
|
||||
.nr_resources = ARRAY_SIZE(exynos5_uart0_resource),
|
||||
},
|
||||
[2] = {
|
||||
.resources = exynos5_uart2_resource,
|
||||
.nr_resources = ARRAY_SIZE(exynos5_uart2_resource),
|
||||
},
|
||||
[3] = {
|
||||
.resources = exynos5_uart3_resource,
|
||||
.nr_resources = ARRAY_SIZE(exynos5_uart3_resource),
|
||||
},
|
||||
};
|
||||
|
@ -259,11 +259,6 @@
|
||||
#define EXYNOS5_IRQ_IEM_IEC IRQ_SPI(48)
|
||||
#define EXYNOS5_IRQ_IEM_APC IRQ_SPI(49)
|
||||
#define EXYNOS5_IRQ_GPIO_C2C IRQ_SPI(50)
|
||||
#define EXYNOS5_IRQ_UART0 IRQ_SPI(51)
|
||||
#define EXYNOS5_IRQ_UART1 IRQ_SPI(52)
|
||||
#define EXYNOS5_IRQ_UART2 IRQ_SPI(53)
|
||||
#define EXYNOS5_IRQ_UART3 IRQ_SPI(54)
|
||||
#define EXYNOS5_IRQ_UART4 IRQ_SPI(55)
|
||||
#define EXYNOS5_IRQ_IIC IRQ_SPI(56)
|
||||
#define EXYNOS5_IRQ_IIC1 IRQ_SPI(57)
|
||||
#define EXYNOS5_IRQ_IIC2 IRQ_SPI(58)
|
||||
|
@ -271,7 +271,6 @@
|
||||
#define EXYNOS5_PA_UART1 0x12C10000
|
||||
#define EXYNOS5_PA_UART2 0x12C20000
|
||||
#define EXYNOS5_PA_UART3 0x12C30000
|
||||
#define EXYNOS5_SZ_UART SZ_256
|
||||
|
||||
#define S3C_VA_UARTx(x) (S3C_VA_UART + ((x) * S3C_UART_OFFSET))
|
||||
|
||||
|
Loading…
Reference in New Issue
Block a user