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arm64: dts: Add PWM and SDHCI DT nodes for Stingray SOC

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The Stingray SoC has two instances of SDHCI controller
and one instance of iProc PWM.

Let's enable above mentioned devices in Stingray DT.

Signed-off-by: Srinath Mannam <srinath.mannam@broadcom.com>
Signed-off-by: Anup Patel <anup.patel@broadcom.com>
Reviewed-by: Ray Jui <ray.jui@broadcom.com>
Reviewed-by: Scott Branden <scott.branden@broadcom.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
This commit is contained in:
Srinath Mannam 2017-06-02 12:04:35 +05:30 committed by Florian Fainelli
parent 0dc454ee89
commit 552df26309
2 changed files with 67 additions and 0 deletions
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39
arch/arm64/boot/dts/broadcom/stingray/bcm958742-base.dtsi
View File

@ -43,6 +43,28 @@ aliases {
serial2 = &uart2;
serial3 = &uart3;
};
sdio0_vddo_ctrl_reg: sdio0_vddo_ctrl {
compatible = "regulator-gpio";
regulator-name = "sdio0_vddo_ctrl_reg";
regulator-type = "voltage";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
gpios = <&pca9505 18 0>;
states = <3300000 0x0
1800000 0x1>;
};
sdio1_vddo_ctrl_reg: sdio1_vddo_ctrl {
compatible = "regulator-gpio";
regulator-name = "sdio1_vddo_ctrl_reg";
regulator-type = "voltage";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
gpios = <&pca9505 19 0>;
states = <3300000 0x0
1800000 0x1>;
};
};
&memory { /* Default DRAM banks */
@ -54,6 +76,10 @@ &uart1 {
status = "okay";
};
&pwm {
status = "okay";
};
&i2c0 {
status = "okay";
@ -90,3 +116,16 @@ nandcs@0 {
#size-cells = <1>;
};
};
&sdio0 {
vqmmc-supply = <&sdio0_vddo_ctrl_reg>;
non-removable;
full-pwr-cycle;
status = "okay";
};
&sdio1 {
vqmmc-supply = <&sdio1_vddo_ctrl_reg>;
full-pwr-cycle;
status = "okay";
};

28
arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi
View File

@ -269,6 +269,14 @@ hsls {
#include "stingray-pinctrl.dtsi"
pwm: pwm@00010000 {
compatible = "brcm,iproc-pwm";
reg = <0x00010000 0x1000>;
clocks = <&crmu_ref25m>;
#pwm-cells = <3>;
status = "disabled";
};
i2c0: i2c@000b0000 {
compatible = "brcm,iproc-i2c";
reg = <0x000b0000 0x100>;
@ -428,5 +436,25 @@ nand: nand@00360000 {
brcm,nand-has-wp;
status = "disabled";
};
sdio0: sdhci@003f1000 {
compatible = "brcm,sdhci-iproc";
reg = <0x003f1000 0x100>;
interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
bus-width = <8>;
clocks = <&sdio0_clk>;
iommus = <&smmu 0x6002 0x0000>;
status = "disabled";
};
sdio1: sdhci@003f2000 {
compatible = "brcm,sdhci-iproc";
reg = <0x003f2000 0x100>;
interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
bus-width = <8>;
clocks = <&sdio1_clk>;
iommus = <&smmu 0x6003 0x0000>;
status = "disabled";
};
};
};