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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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cxgb4: add support to flash boot image
Update set_flash to flash boot image to flash region Signed-off-by: Vishal Kulkarni <vishal@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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4ee339e1e9
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@ -142,6 +142,52 @@ enum cc_fec {
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enum {
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CXGB4_ETHTOOL_FLASH_FW = 1,
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CXGB4_ETHTOOL_FLASH_PHY = 2,
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CXGB4_ETHTOOL_FLASH_BOOT = 3,
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};
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struct cxgb4_pcir_data {
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__le32 signature; /* Signature. The string "PCIR" */
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__le16 vendor_id; /* Vendor Identification */
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__le16 device_id; /* Device Identification */
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__u8 vital_product[2]; /* Pointer to Vital Product Data */
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__u8 length[2]; /* PCIR Data Structure Length */
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__u8 revision; /* PCIR Data Structure Revision */
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__u8 class_code[3]; /* Class Code */
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__u8 image_length[2]; /* Image Length. Multiple of 512B */
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__u8 code_revision[2]; /* Revision Level of Code/Data */
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__u8 code_type;
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__u8 indicator;
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__u8 reserved[2];
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};
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/* BIOS boot headers */
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struct cxgb4_pci_exp_rom_header {
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__le16 signature; /* ROM Signature. Should be 0xaa55 */
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__u8 reserved[22]; /* Reserved per processor Architecture data */
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__le16 pcir_offset; /* Offset to PCI Data Structure */
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};
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/* Legacy PCI Expansion ROM Header */
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struct legacy_pci_rom_hdr {
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__u8 signature[2]; /* ROM Signature. Should be 0xaa55 */
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__u8 size512; /* Current Image Size in units of 512 bytes */
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__u8 initentry_point[4];
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__u8 cksum; /* Checksum computed on the entire Image */
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__u8 reserved[16]; /* Reserved */
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__le16 pcir_offset; /* Offset to PCI Data Struture */
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};
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#define CXGB4_HDR_CODE1 0x00
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#define CXGB4_HDR_CODE2 0x03
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#define CXGB4_HDR_INDI 0x80
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/* BOOT constants */
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enum {
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BOOT_SIZE_INC = 512,
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BOOT_SIGNATURE = 0xaa55,
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BOOT_MIN_SIZE = sizeof(struct cxgb4_pci_exp_rom_header),
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BOOT_MAX_SIZE = 1024 * BOOT_SIZE_INC,
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PCIR_SIGNATURE = 0x52494350
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};
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struct port_stats {
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@ -1998,6 +2044,8 @@ void t4_register_netevent_notifier(void);
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int t4_i2c_rd(struct adapter *adap, unsigned int mbox, int port,
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unsigned int devid, unsigned int offset,
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unsigned int len, u8 *buf);
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int t4_load_boot(struct adapter *adap, u8 *boot_data,
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unsigned int boot_addr, unsigned int size);
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void free_rspq_fl(struct adapter *adap, struct sge_rspq *rq, struct sge_fl *fl);
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void free_tx_desc(struct adapter *adap, struct sge_txq *q,
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unsigned int n, bool unmap);
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@ -27,6 +27,7 @@ static const char * const flash_region_strings[] = {
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"All",
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"Firmware",
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"PHY Firmware",
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"Boot",
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};
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static const char stats_strings[][ETH_GSTRING_LEN] = {
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@ -1241,6 +1242,28 @@ static int set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
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return err;
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}
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static int cxgb4_ethtool_flash_boot(struct net_device *netdev,
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const u8 *bdata, u32 size)
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{
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struct adapter *adap = netdev2adap(netdev);
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unsigned int offset;
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u8 *data;
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int ret;
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data = kmemdup(bdata, size, GFP_KERNEL);
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if (!data)
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return -ENOMEM;
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offset = OFFSET_G(t4_read_reg(adap, PF_REG(0, PCIE_PF_EXPROM_OFST_A)));
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ret = t4_load_boot(adap, data, offset, size);
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if (ret)
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dev_err(adap->pdev_dev, "Failed to load boot image\n");
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kfree(data);
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return ret;
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}
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#define CXGB4_PHY_SIG 0x130000ea
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static int cxgb4_validate_phy_image(const u8 *data, u32 *size)
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@ -1310,6 +1333,9 @@ static int cxgb4_ethtool_flash_region(struct net_device *netdev,
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case CXGB4_ETHTOOL_FLASH_PHY:
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ret = cxgb4_ethtool_flash_phy(netdev, data, size);
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break;
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case CXGB4_ETHTOOL_FLASH_BOOT:
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ret = cxgb4_ethtool_flash_boot(netdev, data, size);
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break;
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default:
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ret = -EOPNOTSUPP;
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break;
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@ -1339,10 +1365,40 @@ static int cxgb4_validate_fw_image(const u8 *data, u32 *size)
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return 0;
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}
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static int cxgb4_validate_boot_image(const u8 *data, u32 *size)
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{
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struct cxgb4_pci_exp_rom_header *exp_header;
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struct cxgb4_pcir_data *pcir_header;
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struct legacy_pci_rom_hdr *header;
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const u8 *cur_header = data;
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u16 pcir_offset;
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exp_header = (struct cxgb4_pci_exp_rom_header *)data;
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if (le16_to_cpu(exp_header->signature) != BOOT_SIGNATURE)
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return -EINVAL;
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if (size) {
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do {
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header = (struct legacy_pci_rom_hdr *)cur_header;
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pcir_offset = le16_to_cpu(header->pcir_offset);
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pcir_header = (struct cxgb4_pcir_data *)(cur_header +
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pcir_offset);
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*size += header->size512 * 512;
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cur_header += header->size512 * 512;
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} while (!(pcir_header->indicator & CXGB4_HDR_INDI));
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}
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return 0;
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}
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static int cxgb4_ethtool_get_flash_region(const u8 *data, u32 *size)
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{
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if (!cxgb4_validate_fw_image(data, size))
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return CXGB4_ETHTOOL_FLASH_FW;
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if (!cxgb4_validate_boot_image(data, size))
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return CXGB4_ETHTOOL_FLASH_BOOT;
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if (!cxgb4_validate_phy_image(data, size))
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return CXGB4_ETHTOOL_FLASH_PHY;
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@ -10481,3 +10481,190 @@ int t4_set_vlan_acl(struct adapter *adap, unsigned int mbox, unsigned int vf,
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return t4_wr_mbox(adap, adap->mbox, &vlan_cmd, sizeof(vlan_cmd), NULL);
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}
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/**
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* modify_device_id - Modifies the device ID of the Boot BIOS image
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* @device_id: the device ID to write.
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* @boot_data: the boot image to modify.
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*
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* Write the supplied device ID to the boot BIOS image.
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*/
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static void modify_device_id(int device_id, u8 *boot_data)
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{
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struct cxgb4_pcir_data *pcir_header;
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struct legacy_pci_rom_hdr *header;
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u8 *cur_header = boot_data;
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u16 pcir_offset;
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/* Loop through all chained images and change the device ID's */
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do {
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header = (struct legacy_pci_rom_hdr *)cur_header;
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pcir_offset = le16_to_cpu(header->pcir_offset);
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pcir_header = (struct cxgb4_pcir_data *)(cur_header +
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pcir_offset);
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/**
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* Only modify the Device ID if code type is Legacy or HP.
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* 0x00: Okay to modify
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* 0x01: FCODE. Do not modify
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* 0x03: Okay to modify
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* 0x04-0xFF: Do not modify
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*/
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if (pcir_header->code_type == CXGB4_HDR_CODE1) {
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u8 csum = 0;
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int i;
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/**
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* Modify Device ID to match current adatper
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*/
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pcir_header->device_id = cpu_to_le16(device_id);
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/**
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* Set checksum temporarily to 0.
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* We will recalculate it later.
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*/
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header->cksum = 0x0;
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/**
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* Calculate and update checksum
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*/
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for (i = 0; i < (header->size512 * 512); i++)
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csum += cur_header[i];
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/**
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* Invert summed value to create the checksum
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* Writing new checksum value directly to the boot data
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*/
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cur_header[7] = -csum;
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} else if (pcir_header->code_type == CXGB4_HDR_CODE2) {
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/**
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* Modify Device ID to match current adatper
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*/
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pcir_header->device_id = cpu_to_le16(device_id);
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}
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/**
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* Move header pointer up to the next image in the ROM.
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*/
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cur_header += header->size512 * 512;
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} while (!(pcir_header->indicator & CXGB4_HDR_INDI));
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}
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/**
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* t4_load_boot - download boot flash
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* @adap: the adapter
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* @boot_data: the boot image to write
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* @boot_addr: offset in flash to write boot_data
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* @size: image size
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*
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* Write the supplied boot image to the card's serial flash.
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* The boot image has the following sections: a 28-byte header and the
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* boot image.
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*/
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int t4_load_boot(struct adapter *adap, u8 *boot_data,
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unsigned int boot_addr, unsigned int size)
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{
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unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec;
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unsigned int boot_sector = (boot_addr * 1024);
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struct cxgb4_pci_exp_rom_header *header;
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struct cxgb4_pcir_data *pcir_header;
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int pcir_offset;
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unsigned int i;
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u16 device_id;
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int ret, addr;
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/**
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* Make sure the boot image does not encroach on the firmware region
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*/
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if ((boot_sector + size) >> 16 > FLASH_FW_START_SEC) {
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dev_err(adap->pdev_dev, "boot image encroaching on firmware region\n");
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return -EFBIG;
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}
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/* Get boot header */
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header = (struct cxgb4_pci_exp_rom_header *)boot_data;
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pcir_offset = le16_to_cpu(header->pcir_offset);
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/* PCIR Data Structure */
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pcir_header = (struct cxgb4_pcir_data *)&boot_data[pcir_offset];
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/**
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* Perform some primitive sanity testing to avoid accidentally
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* writing garbage over the boot sectors. We ought to check for
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* more but it's not worth it for now ...
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*/
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if (size < BOOT_MIN_SIZE || size > BOOT_MAX_SIZE) {
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dev_err(adap->pdev_dev, "boot image too small/large\n");
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return -EFBIG;
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}
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if (le16_to_cpu(header->signature) != BOOT_SIGNATURE) {
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dev_err(adap->pdev_dev, "Boot image missing signature\n");
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return -EINVAL;
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}
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/* Check PCI header signature */
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if (le32_to_cpu(pcir_header->signature) != PCIR_SIGNATURE) {
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dev_err(adap->pdev_dev, "PCI header missing signature\n");
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return -EINVAL;
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}
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/* Check Vendor ID matches Chelsio ID*/
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if (le16_to_cpu(pcir_header->vendor_id) != PCI_VENDOR_ID_CHELSIO) {
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dev_err(adap->pdev_dev, "Vendor ID missing signature\n");
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return -EINVAL;
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}
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/**
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* The boot sector is comprised of the Expansion-ROM boot, iSCSI boot,
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* and Boot configuration data sections. These 3 boot sections span
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* sectors 0 to 7 in flash and live right before the FW image location.
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*/
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i = DIV_ROUND_UP(size ? size : FLASH_FW_START, sf_sec_size);
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ret = t4_flash_erase_sectors(adap, boot_sector >> 16,
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(boot_sector >> 16) + i - 1);
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/**
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* If size == 0 then we're simply erasing the FLASH sectors associated
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* with the on-adapter option ROM file
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*/
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if (ret || size == 0)
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goto out;
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/* Retrieve adapter's device ID */
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pci_read_config_word(adap->pdev, PCI_DEVICE_ID, &device_id);
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/* Want to deal with PF 0 so I strip off PF 4 indicator */
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device_id = device_id & 0xf0ff;
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/* Check PCIE Device ID */
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if (le16_to_cpu(pcir_header->device_id) != device_id) {
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/**
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* Change the device ID in the Boot BIOS image to match
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* the Device ID of the current adapter.
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*/
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modify_device_id(device_id, boot_data);
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}
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/**
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* Skip over the first SF_PAGE_SIZE worth of data and write it after
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* we finish copying the rest of the boot image. This will ensure
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* that the BIOS boot header will only be written if the boot image
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* was written in full.
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*/
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addr = boot_sector;
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for (size -= SF_PAGE_SIZE; size; size -= SF_PAGE_SIZE) {
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addr += SF_PAGE_SIZE;
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boot_data += SF_PAGE_SIZE;
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ret = t4_write_flash(adap, addr, SF_PAGE_SIZE, boot_data);
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if (ret)
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goto out;
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}
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ret = t4_write_flash(adap, boot_sector, SF_PAGE_SIZE,
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(const u8 *)header);
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out:
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if (ret)
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dev_err(adap->pdev_dev, "boot image load failed, error %d\n",
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ret);
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return ret;
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}
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@ -563,6 +563,12 @@
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#define AIVEC_V(x) ((x) << AIVEC_S)
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#define PCIE_PF_CLI_A 0x44
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#define PCIE_PF_EXPROM_OFST_A 0x4c
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#define OFFSET_S 10
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#define OFFSET_M 0x3fffU
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#define OFFSET_G(x) (((x) >> OFFSET_S) & OFFSET_M)
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#define PCIE_INT_CAUSE_A 0x3004
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#define UNXSPLCPLERR_S 29
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