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drm/amdgpu: create mqd for gfx queues on navi10

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mqd is the memory queue descriptor for gfx and compute.

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Jack Xiao <jack.xiao@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Hawking Zhang 2018-08-14 20:54:35 +08:00 committed by Alex Deucher
parent 5bfca06928
commit 54fc447279
1 changed files with 34 additions and 1 deletions
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35
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
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@ -389,6 +389,27 @@ int amdgpu_gfx_mqd_sw_init(struct amdgpu_device *adev,
dev_warn(adev->dev, "no memory to create MQD backup for ring %s\n", ring->name); dev_warn(adev->dev, "no memory to create MQD backup for ring %s\n", ring->name);
} }
if (adev->asic_type == CHIP_NAVI10 && amdgpu_async_gfx_ring) {
/* create MQD for each KGQ */
for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
ring = &adev->gfx.gfx_ring[i];
if (!ring->mqd_obj) {
r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE,
AMDGPU_GEM_DOMAIN_GTT, &ring->mqd_obj,
&ring->mqd_gpu_addr, &ring->mqd_ptr);
if (r) {
dev_warn(adev->dev, "failed to create ring mqd bo (%d)", r);
return r;
}
/* prepare MQD backup */
adev->gfx.me.mqd_backup[i] = kmalloc(mqd_size, GFP_KERNEL);
if (!adev->gfx.me.mqd_backup[i])
dev_warn(adev->dev, "no memory to create MQD backup for ring %s\n", ring->name);
}
}
}
/* create MQD for each KCQ */ /* create MQD for each KCQ */
for (i = 0; i < adev->gfx.num_compute_rings; i++) { for (i = 0; i < adev->gfx.num_compute_rings; i++) {
ring = &adev->gfx.compute_ring[i]; ring = &adev->gfx.compute_ring[i];
@ -397,7 +418,7 @@ int amdgpu_gfx_mqd_sw_init(struct amdgpu_device *adev,
AMDGPU_GEM_DOMAIN_GTT, &ring->mqd_obj, AMDGPU_GEM_DOMAIN_GTT, &ring->mqd_obj,
&ring->mqd_gpu_addr, &ring->mqd_ptr); &ring->mqd_gpu_addr, &ring->mqd_ptr);
if (r) { if (r) {
dev_warn(adev->dev, "failed to create ring mqd ob (%d)", r); dev_warn(adev->dev, "failed to create ring mqd bo (%d)", r);
return r; return r;
} }
@ -416,6 +437,16 @@ void amdgpu_gfx_mqd_sw_fini(struct amdgpu_device *adev)
struct amdgpu_ring *ring = NULL; struct amdgpu_ring *ring = NULL;
int i; int i;
if (adev->asic_type == CHIP_NAVI10 && amdgpu_async_gfx_ring) {
for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
ring = &adev->gfx.gfx_ring[i];
kfree(adev->gfx.me.mqd_backup[i]);
amdgpu_bo_free_kernel(&ring->mqd_obj,
&ring->mqd_gpu_addr,
&ring->mqd_ptr);
}
}
for (i = 0; i < adev->gfx.num_compute_rings; i++) { for (i = 0; i < adev->gfx.num_compute_rings; i++) {
ring = &adev->gfx.compute_ring[i]; ring = &adev->gfx.compute_ring[i];
kfree(adev->gfx.mec.mqd_backup[i]); kfree(adev->gfx.mec.mqd_backup[i]);
@ -425,6 +456,8 @@ void amdgpu_gfx_mqd_sw_fini(struct amdgpu_device *adev)
} }
ring = &adev->gfx.kiq.ring; ring = &adev->gfx.kiq.ring;
if (adev->asic_type == CHIP_NAVI10 && amdgpu_async_gfx_ring)
kfree(adev->gfx.me.mqd_backup[AMDGPU_MAX_GFX_RINGS]);
kfree(adev->gfx.mec.mqd_backup[AMDGPU_MAX_COMPUTE_RINGS]); kfree(adev->gfx.mec.mqd_backup[AMDGPU_MAX_COMPUTE_RINGS]);
amdgpu_bo_free_kernel(&ring->mqd_obj, amdgpu_bo_free_kernel(&ring->mqd_obj,
&ring->mqd_gpu_addr, &ring->mqd_gpu_addr,