mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-18 09:46:50 +07:00
octeontx2-af: Reset all RVU blocks
Go through all BLKADDRs and check which ones are implemented on this silicon and do a HW reset of each implemented block. Also added all RVU AF and PF register offsets. Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Sunil Goutham
David S. Miller
parent
54494aa5d1
commit
54d557815e
@ -16,6 +16,7 @@
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#include <linux/sysfs.h>
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#include "rvu.h"
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#include "rvu_reg.h"
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#define DRV_NAME "octeontx2-af"
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#define DRV_STRING "Marvell OcteonTX2 RVU Admin Function Driver"
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@ -33,6 +34,69 @@ MODULE_LICENSE("GPL v2");
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MODULE_VERSION(DRV_VERSION);
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MODULE_DEVICE_TABLE(pci, rvu_id_table);
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/* Poll a RVU block's register 'offset', for a 'zero'
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* or 'nonzero' at bits specified by 'mask'
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*/
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int rvu_poll_reg(struct rvu *rvu, u64 block, u64 offset, u64 mask, bool zero)
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{
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void __iomem *reg;
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int timeout = 100;
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u64 reg_val;
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reg = rvu->afreg_base + ((block << 28) | offset);
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while (timeout) {
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reg_val = readq(reg);
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if (zero && !(reg_val & mask))
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return 0;
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if (!zero && (reg_val & mask))
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return 0;
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usleep_range(1, 2);
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timeout--;
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}
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return -EBUSY;
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}
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static void rvu_check_block_implemented(struct rvu *rvu)
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{
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struct rvu_hwinfo *hw = rvu->hw;
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struct rvu_block *block;
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int blkid;
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u64 cfg;
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/* For each block check if 'implemented' bit is set */
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for (blkid = 0; blkid < BLK_COUNT; blkid++) {
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block = &hw->block[blkid];
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cfg = rvupf_read64(rvu, RVU_PF_BLOCK_ADDRX_DISC(blkid));
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if (cfg & BIT_ULL(11))
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block->implemented = true;
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}
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}
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static void rvu_block_reset(struct rvu *rvu, int blkaddr, u64 rst_reg)
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{
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struct rvu_block *block = &rvu->hw->block[blkaddr];
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if (!block->implemented)
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return;
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rvu_write64(rvu, blkaddr, rst_reg, BIT_ULL(0));
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rvu_poll_reg(rvu, blkaddr, rst_reg, BIT_ULL(63), true);
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}
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static void rvu_reset_all_blocks(struct rvu *rvu)
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{
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/* Do a HW reset of all RVU blocks */
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rvu_block_reset(rvu, BLKADDR_NPA, NPA_AF_BLK_RST);
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rvu_block_reset(rvu, BLKADDR_NIX0, NIX_AF_BLK_RST);
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rvu_block_reset(rvu, BLKADDR_NPC, NPC_AF_BLK_RST);
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rvu_block_reset(rvu, BLKADDR_SSO, SSO_AF_BLK_RST);
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rvu_block_reset(rvu, BLKADDR_TIM, TIM_AF_BLK_RST);
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rvu_block_reset(rvu, BLKADDR_CPT0, CPT_AF_BLK_RST);
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rvu_block_reset(rvu, BLKADDR_NDC0, NDC_AF_BLK_RST);
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rvu_block_reset(rvu, BLKADDR_NDC1, NDC_AF_BLK_RST);
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rvu_block_reset(rvu, BLKADDR_NDC2, NDC_AF_BLK_RST);
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}
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static int rvu_probe(struct pci_dev *pdev, const struct pci_device_id *id)
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{
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struct device *dev = &pdev->dev;
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@ -43,6 +107,12 @@ static int rvu_probe(struct pci_dev *pdev, const struct pci_device_id *id)
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if (!rvu)
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return -ENOMEM;
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rvu->hw = devm_kzalloc(dev, sizeof(struct rvu_hwinfo), GFP_KERNEL);
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if (!rvu->hw) {
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devm_kfree(dev, rvu);
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return -ENOMEM;
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}
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pci_set_drvdata(pdev, rvu);
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rvu->pdev = pdev;
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rvu->dev = &pdev->dev;
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@ -80,6 +150,11 @@ static int rvu_probe(struct pci_dev *pdev, const struct pci_device_id *id)
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goto err_release_regions;
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}
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/* Check which blocks the HW supports */
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rvu_check_block_implemented(rvu);
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rvu_reset_all_blocks(rvu);
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return 0;
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err_release_regions:
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@ -88,6 +163,7 @@ static int rvu_probe(struct pci_dev *pdev, const struct pci_device_id *id)
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pci_disable_device(pdev);
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err_freemem:
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pci_set_drvdata(pdev, NULL);
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devm_kfree(&pdev->dev, rvu->hw);
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devm_kfree(dev, rvu);
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return err;
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}
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@ -100,6 +176,7 @@ static void rvu_remove(struct pci_dev *pdev)
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pci_disable_device(pdev);
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pci_set_drvdata(pdev, NULL);
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devm_kfree(&pdev->dev, rvu->hw);
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devm_kfree(&pdev->dev, rvu);
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}
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@ -11,6 +11,8 @@
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#ifndef RVU_H
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#define RVU_H
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#include "rvu_struct.h"
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/* PCI device IDs */
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#define PCI_DEVID_OCTEONTX2_RVU_AF 0xA065
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@ -21,11 +23,46 @@
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#define NAME_SIZE 32
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struct rvu_block {
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bool implemented;
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};
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struct rvu_hwinfo {
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struct rvu_block block[BLK_COUNT]; /* Block info */
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};
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struct rvu {
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void __iomem *afreg_base;
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void __iomem *pfreg_base;
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struct pci_dev *pdev;
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struct device *dev;
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struct rvu_hwinfo *hw;
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};
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static inline void rvu_write64(struct rvu *rvu, u64 block, u64 offset, u64 val)
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{
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writeq(val, rvu->afreg_base + ((block << 28) | offset));
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}
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static inline u64 rvu_read64(struct rvu *rvu, u64 block, u64 offset)
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{
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return readq(rvu->afreg_base + ((block << 28) | offset));
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}
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static inline void rvupf_write64(struct rvu *rvu, u64 offset, u64 val)
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{
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writeq(val, rvu->pfreg_base + offset);
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}
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static inline u64 rvupf_read64(struct rvu *rvu, u64 offset)
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{
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return readq(rvu->pfreg_base + offset);
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}
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/* Function Prototypes
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* RVU
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*/
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int rvu_poll_reg(struct rvu *rvu, u64 block, u64 offset, u64 mask, bool zero);
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#endif /* RVU_H */
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112
drivers/net/ethernet/marvell/octeontx2/af/rvu_reg.h
Normal file
112
drivers/net/ethernet/marvell/octeontx2/af/rvu_reg.h
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@ -0,0 +1,112 @@
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/* SPDX-License-Identifier: GPL-2.0
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* Marvell OcteonTx2 RVU Admin Function driver
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*
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* Copyright (C) 2018 Marvell International Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef RVU_REG_H
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#define RVU_REG_H
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/* Admin function registers */
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#define RVU_AF_MSIXTR_BASE (0x10)
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#define RVU_AF_ECO (0x20)
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#define RVU_AF_BLK_RST (0x30)
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#define RVU_AF_PF_BAR4_ADDR (0x40)
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#define RVU_AF_RAS (0x100)
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#define RVU_AF_RAS_W1S (0x108)
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#define RVU_AF_RAS_ENA_W1S (0x110)
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#define RVU_AF_RAS_ENA_W1C (0x118)
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#define RVU_AF_GEN_INT (0x120)
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#define RVU_AF_GEN_INT_W1S (0x128)
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#define RVU_AF_GEN_INT_ENA_W1S (0x130)
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#define RVU_AF_GEN_INT_ENA_W1C (0x138)
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#define RVU_AF_AFPF_MBOX0 (0x02000)
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#define RVU_AF_AFPF_MBOX1 (0x02008)
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#define RVU_AF_AFPFX_MBOXX(a, b) (0x2000 | (a) << 4 | (b) << 3)
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#define RVU_AF_PFME_STATUS (0x2800)
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#define RVU_AF_PFTRPEND (0x2810)
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#define RVU_AF_PFTRPEND_W1S (0x2820)
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#define RVU_AF_PF_RST (0x2840)
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#define RVU_AF_HWVF_RST (0x2850)
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#define RVU_AF_PFAF_MBOX_INT (0x2880)
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#define RVU_AF_PFAF_MBOX_INT_W1S (0x2888)
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#define RVU_AF_PFAF_MBOX_INT_ENA_W1S (0x2890)
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#define RVU_AF_PFAF_MBOX_INT_ENA_W1C (0x2898)
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#define RVU_AF_PFFLR_INT (0x28a0)
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#define RVU_AF_PFFLR_INT_W1S (0x28a8)
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#define RVU_AF_PFFLR_INT_ENA_W1S (0x28b0)
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#define RVU_AF_PFFLR_INT_ENA_W1C (0x28b8)
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#define RVU_AF_PFME_INT (0x28c0)
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#define RVU_AF_PFME_INT_W1S (0x28c8)
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#define RVU_AF_PFME_INT_ENA_W1S (0x28d0)
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#define RVU_AF_PFME_INT_ENA_W1C (0x28d8)
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/* Admin function's privileged PF/VF registers */
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#define RVU_PRIV_CONST (0x8000000)
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#define RVU_PRIV_GEN_CFG (0x8000010)
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#define RVU_PRIV_CLK_CFG (0x8000020)
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#define RVU_PRIV_ACTIVE_PC (0x8000030)
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#define RVU_PRIV_PFX_CFG(a) (0x8000100 | (a) << 16)
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#define RVU_PRIV_PFX_MSIX_CFG(a) (0x8000110 | (a) << 16)
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#define RVU_PRIV_PFX_ID_CFG(a) (0x8000120 | (a) << 16)
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#define RVU_PRIV_PFX_INT_CFG(a) (0x8000200 | (a) << 16)
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#define RVU_PRIV_PFX_NIX_CFG (0x8000300)
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#define RVU_PRIV_PFX_NPA_CFG (0x8000310)
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#define RVU_PRIV_PFX_SSO_CFG (0x8000320)
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#define RVU_PRIV_PFX_SSOW_CFG (0x8000330)
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#define RVU_PRIV_PFX_TIM_CFG (0x8000340)
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#define RVU_PRIV_PFX_CPT_CFG (0x8000350)
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#define RVU_PRIV_BLOCK_TYPEX_REV(a) (0x8000400 | (a) << 3)
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#define RVU_PRIV_HWVFX_INT_CFG(a) (0x8001280 | (a) << 16)
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#define RVU_PRIV_HWVFX_NIX_CFG (0x8001300)
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#define RVU_PRIV_HWVFX_NPA_CFG (0x8001310)
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#define RVU_PRIV_HWVFX_SSO_CFG (0x8001320)
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#define RVU_PRIV_HWVFX_SSOW_CFG (0x8001330)
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#define RVU_PRIV_HWVFX_TIM_CFG (0x8001340)
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#define RVU_PRIV_HWVFX_CPT_CFG (0x8001350)
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/* RVU PF registers */
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#define RVU_PF_VFX_PFVF_MBOX0 (0x00000)
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#define RVU_PF_VFX_PFVF_MBOX1 (0x00008)
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#define RVU_PF_VFX_PFVF_MBOXX(a, b) (0x0 | (a) << 12 | (b) << 3)
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#define RVU_PF_VF_BAR4_ADDR (0x10)
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#define RVU_PF_BLOCK_ADDRX_DISC(a) (0x200 | (a) << 3)
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#define RVU_PF_VFME_STATUSX(a) (0x800 | (a) << 3)
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#define RVU_PF_VFTRPENDX(a) (0x820 | (a) << 3)
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#define RVU_PF_VFTRPEND_W1SX(a) (0x840 | (a) << 3)
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#define RVU_PF_VFPF_MBOX_INTX(a) (0x880 | (a) << 3)
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#define RVU_PF_VFPF_MBOX_INT_W1SX(a) (0x8A0 | (a) << 3)
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#define RVU_PF_VFPF_MBOX_INT_ENA_W1SX(a) (0x8C0 | (a) << 3)
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#define RVU_PF_VFPF_MBOX_INT_ENA_W1CX(a) (0x8E0 | (a) << 3)
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#define RVU_PF_VFFLR_INTX(a) (0x900 | (a) << 3)
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#define RVU_PF_VFFLR_INT_W1SX(a) (0x920 | (a) << 3)
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#define RVU_PF_VFFLR_INT_ENA_W1SX(a) (0x940 | (a) << 3)
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#define RVU_PF_VFFLR_INT_ENA_W1CX(a) (0x960 | (a) << 3)
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#define RVU_PF_VFME_INTX(a) (0x980 | (a) << 3)
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#define RVU_PF_VFME_INT_W1SX(a) (0x9A0 | (a) << 3)
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#define RVU_PF_VFME_INT_ENA_W1SX(a) (0x9C0 | (a) << 3)
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#define RVU_PF_VFME_INT_ENA_W1CX(a) (0x9E0 | (a) << 3)
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#define RVU_PF_PFAF_MBOX0 (0xC00)
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#define RVU_PF_PFAF_MBOX1 (0xC08)
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#define RVU_PF_PFAF_MBOXX(a) (0xC00 | (a) << 3)
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#define RVU_PF_INT (0xc20)
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#define RVU_PF_INT_W1S (0xc28)
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#define RVU_PF_INT_ENA_W1S (0xc30)
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#define RVU_PF_INT_ENA_W1C (0xc38)
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#define RVU_PF_MSIX_VECX_ADDR(a) (0x000 | (a) << 4)
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#define RVU_PF_MSIX_VECX_CTL(a) (0x008 | (a) << 4)
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#define RVU_PF_MSIX_PBAX(a) (0xF0000 | (a) << 3)
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#define NPA_AF_BLK_RST (0x0000)
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#define NIX_AF_BLK_RST (0x00B0)
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#define SSO_AF_BLK_RST (0x10f8)
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#define TIM_AF_BLK_RST (0x10)
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#define CPT_AF_BLK_RST (0x46000)
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#define NDC_AF_BLK_RST (0x002F0)
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#define NPC_AF_BLK_RST (0x00040)
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#endif /* RVU_REG_H */
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34
drivers/net/ethernet/marvell/octeontx2/af/rvu_struct.h
Normal file
34
drivers/net/ethernet/marvell/octeontx2/af/rvu_struct.h
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@ -0,0 +1,34 @@
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/* SPDX-License-Identifier: GPL-2.0
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* Marvell OcteonTx2 RVU Admin Function driver
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*
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* Copyright (C) 2018 Marvell International Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef RVU_STRUCT_H
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#define RVU_STRUCT_H
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/* RVU Block Address Enumeration */
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enum rvu_block_addr_e {
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BLKADDR_RVUM = 0x0ULL,
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BLKADDR_LMT = 0x1ULL,
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BLKADDR_MSIX = 0x2ULL,
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BLKADDR_NPA = 0x3ULL,
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BLKADDR_NIX0 = 0x4ULL,
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BLKADDR_NIX1 = 0x5ULL,
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BLKADDR_NPC = 0x6ULL,
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BLKADDR_SSO = 0x7ULL,
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BLKADDR_SSOW = 0x8ULL,
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BLKADDR_TIM = 0x9ULL,
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BLKADDR_CPT0 = 0xaULL,
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BLKADDR_CPT1 = 0xbULL,
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BLKADDR_NDC0 = 0xcULL,
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BLKADDR_NDC1 = 0xdULL,
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BLKADDR_NDC2 = 0xeULL,
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BLK_COUNT = 0xfULL,
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};
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#endif /* RVU_STRUCT_H */
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