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MIPS: Octeon: Update PCI Latency timer and enable more error reporting.

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Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/2987/
Patchwork: https://patchwork.linux-mips.org/patch/3161/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
David Daney 2011-12-08 12:26:28 +00:00 committed by Ralf Baechle
parent 714c1f5c1a
commit 53efc98ec6
1 changed files with 6 additions and 10 deletions
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16
arch/mips/pci/pci-octeon.c
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@ -99,7 +99,7 @@ int pcibios_plat_dev_init(struct pci_dev *dev)
*/ */
pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 64 / 4); pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 64 / 4);
/* Set latency timers for all devices */ /* Set latency timers for all devices */
pci_write_config_byte(dev, PCI_LATENCY_TIMER, 48); pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64);
/* Enable reporting System errors and parity errors on all devices */ /* Enable reporting System errors and parity errors on all devices */
/* Enable parity checking and error reporting */ /* Enable parity checking and error reporting */
@ -109,7 +109,7 @@ int pcibios_plat_dev_init(struct pci_dev *dev)
if (dev->subordinate) { if (dev->subordinate) {
/* Set latency timers on sub bridges */ /* Set latency timers on sub bridges */
pci_write_config_byte(dev, PCI_SEC_LATENCY_TIMER, 48); pci_write_config_byte(dev, PCI_SEC_LATENCY_TIMER, 64);
/* More bridge error detection */ /* More bridge error detection */
pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &config); pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &config);
config |= PCI_BRIDGE_CTL_PARITY | PCI_BRIDGE_CTL_SERR; config |= PCI_BRIDGE_CTL_PARITY | PCI_BRIDGE_CTL_SERR;
@ -121,14 +121,10 @@ int pcibios_plat_dev_init(struct pci_dev *dev)
if (pos) { if (pos) {
/* Update Device Control */ /* Update Device Control */
pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &config); pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &config);
/* Correctable Error Reporting */ config |= PCI_EXP_DEVCTL_CERE; /* Correctable Error Reporting */
config |= PCI_EXP_DEVCTL_CERE; config |= PCI_EXP_DEVCTL_NFERE; /* Non-Fatal Error Reporting */
/* Non-Fatal Error Reporting */ config |= PCI_EXP_DEVCTL_FERE; /* Fatal Error Reporting */
config |= PCI_EXP_DEVCTL_NFERE; config |= PCI_EXP_DEVCTL_URRE; /* Unsupported Request */
/* Fatal Error Reporting */
config |= PCI_EXP_DEVCTL_FERE;
/* Unsupported Request */
config |= PCI_EXP_DEVCTL_URRE;
pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, config); pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, config);
} }