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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2025-01-18 16:56:09 +07:00
dmaengine: at_hdmac: add cyclic DMA operation support
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
This commit is contained in:
Nicolas Ferre
Vinod Koul
parent
9b3aa589ea
commit
53830cc759
@ -164,6 +164,29 @@ static void atc_desc_put(struct at_dma_chan *atchan, struct at_desc *desc)
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}
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}
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/**
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* atc_desc_chain - build chain adding a descripor
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* @first: address of first descripor of the chain
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* @prev: address of previous descripor of the chain
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* @desc: descriptor to queue
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*
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* Called from prep_* functions
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*/
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static void atc_desc_chain(struct at_desc **first, struct at_desc **prev,
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struct at_desc *desc)
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{
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if (!(*first)) {
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*first = desc;
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} else {
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/* inform the HW lli about chaining */
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(*prev)->lli.dscr = desc->txd.phys;
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/* insert the link descriptor to the LD ring */
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list_add_tail(&desc->desc_node,
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&(*first)->tx_list);
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}
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*prev = desc;
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}
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/**
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* atc_assign_cookie - compute and assign new cookie
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* @atchan: channel we work on
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@ -237,16 +260,12 @@ static void atc_dostart(struct at_dma_chan *atchan, struct at_desc *first)
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static void
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atc_chain_complete(struct at_dma_chan *atchan, struct at_desc *desc)
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{
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dma_async_tx_callback callback;
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void *param;
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struct dma_async_tx_descriptor *txd = &desc->txd;
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dev_vdbg(chan2dev(&atchan->chan_common),
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"descriptor %u complete\n", txd->cookie);
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atchan->completed_cookie = txd->cookie;
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callback = txd->callback;
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param = txd->callback_param;
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/* move children to free_list */
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list_splice_init(&desc->tx_list, &atchan->free_list);
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@ -278,12 +297,19 @@ atc_chain_complete(struct at_dma_chan *atchan, struct at_desc *desc)
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}
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}
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/*
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* The API requires that no submissions are done from a
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* callback, so we don't need to drop the lock here
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*/
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if (callback)
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callback(param);
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/* for cyclic transfers,
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* no need to replay callback function while stopping */
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if (!test_bit(ATC_IS_CYCLIC, &atchan->status)) {
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dma_async_tx_callback callback = txd->callback;
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void *param = txd->callback_param;
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/*
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* The API requires that no submissions are done from a
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* callback, so we don't need to drop the lock here
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*/
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if (callback)
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callback(param);
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}
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dma_run_dependencies(txd);
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}
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@ -419,6 +445,26 @@ static void atc_handle_error(struct at_dma_chan *atchan)
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atc_chain_complete(atchan, bad_desc);
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}
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/**
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* atc_handle_cyclic - at the end of a period, run callback function
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* @atchan: channel used for cyclic operations
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*
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* Called with atchan->lock held and bh disabled
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*/
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static void atc_handle_cyclic(struct at_dma_chan *atchan)
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{
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struct at_desc *first = atc_first_active(atchan);
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struct dma_async_tx_descriptor *txd = &first->txd;
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dma_async_tx_callback callback = txd->callback;
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void *param = txd->callback_param;
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dev_vdbg(chan2dev(&atchan->chan_common),
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"new cyclic period llp 0x%08x\n",
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channel_readl(atchan, DSCR));
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if (callback)
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callback(param);
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}
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/*-- IRQ & Tasklet ---------------------------------------------------*/
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@ -434,8 +480,10 @@ static void atc_tasklet(unsigned long data)
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}
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spin_lock(&atchan->lock);
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if (test_and_clear_bit(0, &atchan->error_status))
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if (test_and_clear_bit(ATC_IS_ERROR, &atchan->status))
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atc_handle_error(atchan);
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else if (test_bit(ATC_IS_CYCLIC, &atchan->status))
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atc_handle_cyclic(atchan);
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else
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atc_advance_work(atchan);
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@ -469,7 +517,7 @@ static irqreturn_t at_dma_interrupt(int irq, void *dev_id)
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/* Disable channel on AHB error */
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dma_writel(atdma, CHDR, atchan->mask);
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/* Give information to tasklet */
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set_bit(0, &atchan->error_status);
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set_bit(ATC_IS_ERROR, &atchan->status);
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}
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tasklet_schedule(&atchan->tasklet);
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ret = IRQ_HANDLED;
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@ -759,6 +807,148 @@ atc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
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return NULL;
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}
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/**
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* atc_dma_cyclic_check_values
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* Check for too big/unaligned periods and unaligned DMA buffer
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*/
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static int
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atc_dma_cyclic_check_values(unsigned int reg_width, dma_addr_t buf_addr,
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size_t period_len, enum dma_data_direction direction)
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{
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if (period_len > (ATC_BTSIZE_MAX << reg_width))
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goto err_out;
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if (unlikely(period_len & ((1 << reg_width) - 1)))
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goto err_out;
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if (unlikely(buf_addr & ((1 << reg_width) - 1)))
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goto err_out;
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if (unlikely(!(direction & (DMA_TO_DEVICE | DMA_FROM_DEVICE))))
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goto err_out;
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return 0;
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err_out:
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return -EINVAL;
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}
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/**
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* atc_dma_cyclic_fill_desc - Fill one period decriptor
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*/
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static int
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atc_dma_cyclic_fill_desc(struct at_dma_slave *atslave, struct at_desc *desc,
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unsigned int period_index, dma_addr_t buf_addr,
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size_t period_len, enum dma_data_direction direction)
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{
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u32 ctrla;
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unsigned int reg_width = atslave->reg_width;
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/* prepare common CRTLA value */
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ctrla = ATC_DEFAULT_CTRLA | atslave->ctrla
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| ATC_DST_WIDTH(reg_width)
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| ATC_SRC_WIDTH(reg_width)
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| period_len >> reg_width;
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switch (direction) {
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case DMA_TO_DEVICE:
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desc->lli.saddr = buf_addr + (period_len * period_index);
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desc->lli.daddr = atslave->tx_reg;
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desc->lli.ctrla = ctrla;
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desc->lli.ctrlb = ATC_DEFAULT_CTRLB
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| ATC_DST_ADDR_MODE_FIXED
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| ATC_SRC_ADDR_MODE_INCR
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| ATC_FC_MEM2PER;
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break;
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case DMA_FROM_DEVICE:
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desc->lli.saddr = atslave->rx_reg;
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desc->lli.daddr = buf_addr + (period_len * period_index);
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desc->lli.ctrla = ctrla;
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desc->lli.ctrlb = ATC_DEFAULT_CTRLB
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| ATC_DST_ADDR_MODE_INCR
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| ATC_SRC_ADDR_MODE_FIXED
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| ATC_FC_PER2MEM;
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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/**
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* atc_prep_dma_cyclic - prepare the cyclic DMA transfer
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* @chan: the DMA channel to prepare
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* @buf_addr: physical DMA address where the buffer starts
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* @buf_len: total number of bytes for the entire buffer
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* @period_len: number of bytes for each period
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* @direction: transfer direction, to or from device
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*/
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static struct dma_async_tx_descriptor *
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atc_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
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size_t period_len, enum dma_data_direction direction)
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{
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struct at_dma_chan *atchan = to_at_dma_chan(chan);
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struct at_dma_slave *atslave = chan->private;
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struct at_desc *first = NULL;
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struct at_desc *prev = NULL;
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unsigned long was_cyclic;
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unsigned int periods = buf_len / period_len;
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unsigned int i;
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dev_vdbg(chan2dev(chan), "prep_dma_cyclic: %s buf@0x%08x - %d (%d/%d)\n",
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direction == DMA_TO_DEVICE ? "TO DEVICE" : "FROM DEVICE",
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buf_addr,
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periods, buf_len, period_len);
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if (unlikely(!atslave || !buf_len || !period_len)) {
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dev_dbg(chan2dev(chan), "prep_dma_cyclic: length is zero!\n");
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return NULL;
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}
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was_cyclic = test_and_set_bit(ATC_IS_CYCLIC, &atchan->status);
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if (was_cyclic) {
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dev_dbg(chan2dev(chan), "prep_dma_cyclic: channel in use!\n");
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return NULL;
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}
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/* Check for too big/unaligned periods and unaligned DMA buffer */
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if (atc_dma_cyclic_check_values(atslave->reg_width, buf_addr,
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period_len, direction))
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goto err_out;
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/* build cyclic linked list */
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for (i = 0; i < periods; i++) {
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struct at_desc *desc;
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desc = atc_desc_get(atchan);
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if (!desc)
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goto err_desc_get;
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if (atc_dma_cyclic_fill_desc(atslave, desc, i, buf_addr,
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period_len, direction))
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goto err_desc_get;
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atc_desc_chain(&first, &prev, desc);
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}
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/* lets make a cyclic list */
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prev->lli.dscr = first->txd.phys;
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/* First descriptor of the chain embedds additional information */
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first->txd.cookie = -EBUSY;
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first->len = buf_len;
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return &first->txd;
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err_desc_get:
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dev_err(chan2dev(chan), "not enough descriptors available\n");
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atc_desc_put(atchan, first);
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err_out:
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clear_bit(ATC_IS_CYCLIC, &atchan->status);
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return NULL;
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}
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static int atc_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
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unsigned long arg)
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{
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@ -793,6 +983,9 @@ static int atc_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
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list_for_each_entry_safe(desc, _desc, &list, desc_node)
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atc_chain_complete(atchan, desc);
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/* if channel dedicated to cyclic operations, free it */
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clear_bit(ATC_IS_CYCLIC, &atchan->status);
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spin_unlock_bh(&atchan->lock);
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return 0;
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@ -853,6 +1046,10 @@ static void atc_issue_pending(struct dma_chan *chan)
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dev_vdbg(chan2dev(chan), "issue_pending\n");
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/* Not needed for cyclic transfers */
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if (test_bit(ATC_IS_CYCLIC, &atchan->status))
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return;
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spin_lock_bh(&atchan->lock);
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if (!atc_chan_is_enabled(atchan)) {
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atc_advance_work(atchan);
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@ -959,6 +1156,7 @@ static void atc_free_chan_resources(struct dma_chan *chan)
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}
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list_splice_init(&atchan->free_list, &list);
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atchan->descs_allocated = 0;
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atchan->status = 0;
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dev_vdbg(chan2dev(chan), "free_chan_resources: done\n");
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}
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@ -1092,10 +1290,15 @@ static int __init at_dma_probe(struct platform_device *pdev)
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if (dma_has_cap(DMA_MEMCPY, atdma->dma_common.cap_mask))
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atdma->dma_common.device_prep_dma_memcpy = atc_prep_dma_memcpy;
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if (dma_has_cap(DMA_SLAVE, atdma->dma_common.cap_mask)) {
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if (dma_has_cap(DMA_SLAVE, atdma->dma_common.cap_mask))
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atdma->dma_common.device_prep_slave_sg = atc_prep_slave_sg;
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if (dma_has_cap(DMA_CYCLIC, atdma->dma_common.cap_mask))
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atdma->dma_common.device_prep_dma_cyclic = atc_prep_dma_cyclic;
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if (dma_has_cap(DMA_SLAVE, atdma->dma_common.cap_mask) ||
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dma_has_cap(DMA_CYCLIC, atdma->dma_common.cap_mask))
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atdma->dma_common.device_control = atc_control;
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}
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dma_writel(atdma, EN, AT_DMA_ENABLE);
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@ -180,13 +180,23 @@ txd_to_at_desc(struct dma_async_tx_descriptor *txd)
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/*-- Channels --------------------------------------------------------*/
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/**
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* atc_status - information bits stored in channel status flag
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*
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* Manipulated with atomic operations.
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*/
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enum atc_status {
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ATC_IS_ERROR = 0,
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ATC_IS_CYCLIC = 24,
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};
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/**
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* struct at_dma_chan - internal representation of an Atmel HDMAC channel
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* @chan_common: common dmaengine channel object members
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* @device: parent device
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* @ch_regs: memory mapped register base
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* @mask: channel index in a mask
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* @error_status: transmit error status information from irq handler
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* @status: transmit status information from irq/prep* functions
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* to tasklet (use atomic operations)
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* @tasklet: bottom half to finish transaction work
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* @lock: serializes enqueue/dequeue operations to descriptors lists
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@ -201,7 +211,7 @@ struct at_dma_chan {
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struct at_dma *device;
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void __iomem *ch_regs;
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u8 mask;
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unsigned long error_status;
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unsigned long status;
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struct tasklet_struct tasklet;
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spinlock_t lock;
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