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ath9k_hw: Fix XPABIAS level configuration for AR9003
Improper configuration of 0x16288 and 0x16290 would affect transmission. Cc:stable@kernel.org Signed-off-by: Vasanthakumar Thiagarajan <vasanth@atheros.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
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@ -22,12 +22,14 @@
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#define COMP_CKSUM_LEN 2
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#define AR_CH0_TOP (0x00016288)
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#define AR_CH0_TOP_XPABIASLVL (0x3)
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#define AR_CH0_TOP_XPABIASLVL (0x300)
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#define AR_CH0_TOP_XPABIASLVL_S (8)
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#define AR_CH0_THERM (0x00016290)
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#define AR_CH0_THERM_SPARE (0x3f)
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#define AR_CH0_THERM_SPARE_S (0)
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#define AR_CH0_THERM_XPABIASLVL_MSB 0x3
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#define AR_CH0_THERM_XPABIASLVL_MSB_S 0
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#define AR_CH0_THERM_XPASHORT2GND 0x4
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#define AR_CH0_THERM_XPASHORT2GND_S 2
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#define AR_SWITCH_TABLE_COM_ALL (0xffff)
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#define AR_SWITCH_TABLE_COM_ALL_S (0)
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@ -3336,9 +3338,9 @@ static s32 ar9003_hw_xpa_bias_level_get(struct ath_hw *ah, bool is2ghz)
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static void ar9003_hw_xpa_bias_level_apply(struct ath_hw *ah, bool is2ghz)
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{
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int bias = ar9003_hw_xpa_bias_level_get(ah, is2ghz);
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REG_RMW_FIELD(ah, AR_CH0_TOP, AR_CH0_TOP_XPABIASLVL, (bias & 0x3));
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REG_RMW_FIELD(ah, AR_CH0_THERM, AR_CH0_THERM_SPARE,
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((bias >> 2) & 0x3));
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REG_RMW_FIELD(ah, AR_CH0_TOP, AR_CH0_TOP_XPABIASLVL, bias);
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REG_RMW_FIELD(ah, AR_CH0_THERM, AR_CH0_THERM_XPABIASLVL_MSB, bias >> 2);
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REG_RMW_FIELD(ah, AR_CH0_THERM, AR_CH0_THERM_XPASHORT2GND, 1);
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}
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static u32 ar9003_hw_ant_ctrl_common_get(struct ath_hw *ah, bool is2ghz)
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