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drm/nvc0: implement irq handler for whatever's at 0x14xxxx

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This is just barely enough to stop a never-ending IRQ storm that can
be triggered by our 3D driver.  We have no idea what this engine is..

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Ben Skeggs 2011-01-21 13:53:21 +10:00
parent 0f1cb203b4
commit 51f73d64b4
1 changed files with 19 additions and 0 deletions
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19
drivers/gpu/drm/nouveau/nvc0_graph.c
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@ -31,6 +31,7 @@
#include "nvc0_graph.h"
static void nvc0_graph_isr(struct drm_device *);
static void nvc0_runk140_isr(struct drm_device *);
static int nvc0_graph_unload_context_to(struct drm_device *dev, u64 chan);
void
@ -281,6 +282,7 @@ nvc0_graph_destroy(struct drm_device *dev)
return;
nouveau_irq_unregister(dev, 12);
nouveau_irq_unregister(dev, 25);
nouveau_gpuobj_ref(NULL, &priv->unk4188b8);
nouveau_gpuobj_ref(NULL, &priv->unk4188b4);
@ -390,6 +392,7 @@ nvc0_graph_create(struct drm_device *dev)
}
nouveau_irq_register(dev, 12, nvc0_graph_isr);
nouveau_irq_register(dev, 25, nvc0_runk140_isr);
NVOBJ_CLASS(dev, 0x902d, GR); /* 2D */
NVOBJ_CLASS(dev, 0x9039, GR); /* M2MF */
NVOBJ_CLASS(dev, 0x9097, GR); /* 3D */
@ -777,3 +780,19 @@ nvc0_graph_isr(struct drm_device *dev)
nv_wr32(dev, 0x400500, 0x00010001);
}
static void
nvc0_runk140_isr(struct drm_device *dev)
{
u32 units = nv_rd32(dev, 0x00017c) & 0x1f;
while (units) {
u32 unit = ffs(units) - 1;
u32 reg = 0x140000 + unit * 0x2000;
u32 st0 = nv_mask(dev, reg + 0x1020, 0, 0);
u32 st1 = nv_mask(dev, reg + 0x1420, 0, 0);
NV_INFO(dev, "PRUNK140: %d 0x%08x 0x%08x\n", unit, st0, st1);
units &= ~(1 << unit);
}
}