mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-22 09:48:07 +07:00
drm/i915: Add .get_hw_state() method for planes
Add a .get_hw_state() method for planes, returning true or false
depending on whether the plane is enabled. Use it to rewrite the
plane enabled/disabled asserts in platform agnostic fashion.
We do lose the pre-gen4 plane<->pipe mapping checks, but since we're
supposed sanitize that anyway it doesn't really matter.
v2: Reoder patches to not depend on enum old_plane_id
Just call assert_plane_disabled() from assert_planes_disabled()
v3: Deal with disabled power wells in .get_hw_state()
v4: Rebase due skl primary plane code removal
Cc: Thierry Reding <thierry.reding@gmail.com>
Cc: Alex Villacís Lasso <alexvillacislasso@hotmail.com>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> #v2
Tested-by: Thierry Reding <thierry.reding@gmail.com> #v2
Link: https://patchwork.freedesktop.org/patch/msgid/20171117191917.11506-2-ville.syrjala@linux.intel.com
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
This commit is contained in:
Ville Syrjälä
parent
36fe778a48
commit
51f5a09639
@ -1190,23 +1190,6 @@ void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe)
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pipe_name(pipe));
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}
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static void assert_cursor(struct drm_i915_private *dev_priv,
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enum pipe pipe, bool state)
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{
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bool cur_state;
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if (IS_I845G(dev_priv) || IS_I865G(dev_priv))
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cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
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else
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cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
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I915_STATE_WARN(cur_state != state,
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"cursor on pipe %c assertion failure (expected %s, current %s)\n",
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pipe_name(pipe), onoff(state), onoff(cur_state));
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}
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#define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
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#define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
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void assert_pipe(struct drm_i915_private *dev_priv,
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enum pipe pipe, bool state)
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{
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@ -1234,77 +1217,25 @@ void assert_pipe(struct drm_i915_private *dev_priv,
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pipe_name(pipe), onoff(state), onoff(cur_state));
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}
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static void assert_plane(struct drm_i915_private *dev_priv,
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enum plane plane, bool state)
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static void assert_plane(struct intel_plane *plane, bool state)
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{
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u32 val;
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bool cur_state;
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bool cur_state = plane->get_hw_state(plane);
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val = I915_READ(DSPCNTR(plane));
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cur_state = !!(val & DISPLAY_PLANE_ENABLE);
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I915_STATE_WARN(cur_state != state,
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"plane %c assertion failure (expected %s, current %s)\n",
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plane_name(plane), onoff(state), onoff(cur_state));
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"%s assertion failure (expected %s, current %s)\n",
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plane->base.name, onoff(state), onoff(cur_state));
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}
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#define assert_plane_enabled(d, p) assert_plane(d, p, true)
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#define assert_plane_disabled(d, p) assert_plane(d, p, false)
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#define assert_plane_enabled(p) assert_plane(p, true)
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#define assert_plane_disabled(p) assert_plane(p, false)
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static void assert_planes_disabled(struct drm_i915_private *dev_priv,
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enum pipe pipe)
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static void assert_planes_disabled(struct intel_crtc *crtc)
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{
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int i;
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struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
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struct intel_plane *plane;
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/* Primary planes are fixed to pipes on gen4+ */
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if (INTEL_GEN(dev_priv) >= 4) {
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u32 val = I915_READ(DSPCNTR(pipe));
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I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
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"plane %c assertion failure, should be disabled but not\n",
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plane_name(pipe));
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return;
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}
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/* Need to check both planes against the pipe */
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for_each_pipe(dev_priv, i) {
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u32 val = I915_READ(DSPCNTR(i));
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enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
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DISPPLANE_SEL_PIPE_SHIFT;
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I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
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"plane %c assertion failure, should be off on pipe %c but is still active\n",
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plane_name(i), pipe_name(pipe));
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}
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}
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static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
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enum pipe pipe)
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{
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int sprite;
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if (INTEL_GEN(dev_priv) >= 9) {
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for_each_sprite(dev_priv, pipe, sprite) {
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u32 val = I915_READ(PLANE_CTL(pipe, sprite));
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I915_STATE_WARN(val & PLANE_CTL_ENABLE,
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"plane %d assertion failure, should be off on pipe %c but is still active\n",
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sprite, pipe_name(pipe));
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}
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} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
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for_each_sprite(dev_priv, pipe, sprite) {
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u32 val = I915_READ(SPCNTR(pipe, PLANE_SPRITE0 + sprite));
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I915_STATE_WARN(val & SP_ENABLE,
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"sprite %c assertion failure, should be off on pipe %c but is still active\n",
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sprite_name(pipe, sprite), pipe_name(pipe));
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}
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} else if (INTEL_GEN(dev_priv) >= 7) {
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u32 val = I915_READ(SPRCTL(pipe));
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I915_STATE_WARN(val & SPRITE_ENABLE,
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"sprite %c assertion failure, should be off on pipe %c but is still active\n",
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plane_name(pipe), pipe_name(pipe));
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} else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) {
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u32 val = I915_READ(DVSCNTR(pipe));
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I915_STATE_WARN(val & DVS_ENABLE,
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"sprite %c assertion failure, should be off on pipe %c but is still active\n",
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plane_name(pipe), pipe_name(pipe));
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}
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for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane)
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assert_plane_disabled(plane);
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}
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static void assert_vblank_disabled(struct drm_crtc *crtc)
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@ -1896,9 +1827,7 @@ static void intel_enable_pipe(struct intel_crtc *crtc)
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DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
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assert_planes_disabled(dev_priv, pipe);
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assert_cursor_disabled(dev_priv, pipe);
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assert_sprites_disabled(dev_priv, pipe);
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assert_planes_disabled(crtc);
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/*
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* A pipe without a PLL won't actually be able to drive bits from
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@ -1968,9 +1897,7 @@ static void intel_disable_pipe(struct intel_crtc *crtc)
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* Make sure planes won't keep trying to pump pixels to us,
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* or we might hang the display.
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*/
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assert_planes_disabled(dev_priv, pipe);
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assert_cursor_disabled(dev_priv, pipe);
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assert_sprites_disabled(dev_priv, pipe);
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assert_planes_disabled(crtc);
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reg = PIPECONF(cpu_transcoder);
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val = I915_READ(reg);
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@ -3364,6 +3291,31 @@ static void i9xx_disable_primary_plane(struct intel_plane *primary,
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spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
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}
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static bool i9xx_plane_get_hw_state(struct intel_plane *primary)
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{
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struct drm_i915_private *dev_priv = to_i915(primary->base.dev);
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enum intel_display_power_domain power_domain;
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enum plane plane = primary->plane;
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enum pipe pipe = primary->pipe;
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bool ret;
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/*
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* Not 100% correct for planes that can move between pipes,
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* but that's only the case for gen2-4 which don't have any
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* display power wells.
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*/
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power_domain = POWER_DOMAIN_PIPE(pipe);
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if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
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return false;
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ret = I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE;
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intel_display_power_put(dev_priv, power_domain);
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return ret;
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}
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static u32
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intel_fb_stride_alignment(const struct drm_framebuffer *fb, int plane)
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{
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@ -4879,7 +4831,8 @@ void hsw_enable_ips(const struct intel_crtc_state *crtc_state)
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* a vblank wait.
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*/
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assert_plane_enabled(dev_priv, crtc->plane);
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assert_plane_enabled(to_intel_plane(crtc->base.primary));
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if (IS_BROADWELL(dev_priv)) {
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mutex_lock(&dev_priv->pcu_lock);
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WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL,
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@ -4913,7 +4866,8 @@ void hsw_disable_ips(const struct intel_crtc_state *crtc_state)
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if (!crtc_state->ips_enabled)
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return;
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assert_plane_enabled(dev_priv, crtc->plane);
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assert_plane_enabled(to_intel_plane(crtc->base.primary));
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if (IS_BROADWELL(dev_priv)) {
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mutex_lock(&dev_priv->pcu_lock);
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WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
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@ -9499,6 +9453,23 @@ static void i845_disable_cursor(struct intel_plane *plane,
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i845_update_cursor(plane, NULL, NULL);
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}
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static bool i845_cursor_get_hw_state(struct intel_plane *plane)
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{
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struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
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enum intel_display_power_domain power_domain;
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bool ret;
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power_domain = POWER_DOMAIN_PIPE(PIPE_A);
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if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
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return false;
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ret = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
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intel_display_power_put(dev_priv, power_domain);
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return ret;
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}
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static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state,
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const struct intel_plane_state *plane_state)
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{
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@ -9692,6 +9663,28 @@ static void i9xx_disable_cursor(struct intel_plane *plane,
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i9xx_update_cursor(plane, NULL, NULL);
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}
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static bool i9xx_cursor_get_hw_state(struct intel_plane *plane)
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{
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struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
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enum intel_display_power_domain power_domain;
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enum pipe pipe = plane->pipe;
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bool ret;
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/*
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* Not 100% correct for planes that can move between pipes,
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* but that's only the case for gen2-3 which don't have any
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* display power wells.
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*/
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power_domain = POWER_DOMAIN_PIPE(pipe);
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if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
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return false;
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ret = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
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intel_display_power_put(dev_priv, power_domain);
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return ret;
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}
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/* VESA 640x480x72Hz mode to set on the pipe */
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static const struct drm_display_mode load_detect_mode = {
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@ -13279,6 +13272,7 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
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primary->update_plane = skl_update_plane;
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primary->disable_plane = skl_disable_plane;
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primary->get_hw_state = skl_plane_get_hw_state;
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} else if (INTEL_GEN(dev_priv) >= 9) {
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intel_primary_formats = skl_primary_formats;
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num_formats = ARRAY_SIZE(skl_primary_formats);
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@ -13289,6 +13283,7 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
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primary->update_plane = skl_update_plane;
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primary->disable_plane = skl_disable_plane;
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primary->get_hw_state = skl_plane_get_hw_state;
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} else if (INTEL_GEN(dev_priv) >= 4) {
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intel_primary_formats = i965_primary_formats;
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num_formats = ARRAY_SIZE(i965_primary_formats);
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@ -13296,6 +13291,7 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
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primary->update_plane = i9xx_update_primary_plane;
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primary->disable_plane = i9xx_disable_primary_plane;
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primary->get_hw_state = i9xx_plane_get_hw_state;
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} else {
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intel_primary_formats = i8xx_primary_formats;
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num_formats = ARRAY_SIZE(i8xx_primary_formats);
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@ -13303,6 +13299,7 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
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primary->update_plane = i9xx_update_primary_plane;
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primary->disable_plane = i9xx_disable_primary_plane;
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primary->get_hw_state = i9xx_plane_get_hw_state;
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}
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if (INTEL_GEN(dev_priv) >= 9)
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@ -13392,10 +13389,12 @@ intel_cursor_plane_create(struct drm_i915_private *dev_priv,
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if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
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cursor->update_plane = i845_update_cursor;
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cursor->disable_plane = i845_disable_cursor;
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cursor->get_hw_state = i845_cursor_get_hw_state;
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cursor->check_plane = i845_check_cursor;
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} else {
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cursor->update_plane = i9xx_update_cursor;
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cursor->disable_plane = i9xx_disable_cursor;
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cursor->get_hw_state = i9xx_cursor_get_hw_state;
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cursor->check_plane = i9xx_check_cursor;
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}
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@ -14761,8 +14760,8 @@ void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
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DRM_DEBUG_KMS("disabling pipe %c due to force quirk\n",
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pipe_name(pipe));
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assert_plane_disabled(dev_priv, PLANE_A);
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assert_plane_disabled(dev_priv, PLANE_B);
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assert_planes_disabled(intel_get_crtc_for_pipe(dev_priv, PIPE_A));
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assert_planes_disabled(intel_get_crtc_for_pipe(dev_priv, PIPE_B));
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I915_WRITE(PIPECONF(pipe), 0);
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POSTING_READ(PIPECONF(pipe));
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@ -14976,20 +14975,13 @@ void i915_redisable_vga(struct drm_i915_private *dev_priv)
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intel_display_power_put(dev_priv, POWER_DOMAIN_VGA);
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}
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static bool primary_get_hw_state(struct intel_plane *plane)
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{
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struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
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return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;
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}
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/* FIXME read out full plane state for all planes */
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static void readout_plane_state(struct intel_crtc *crtc)
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{
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struct intel_plane *primary = to_intel_plane(crtc->base.primary);
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bool visible;
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visible = crtc->active && primary_get_hw_state(primary);
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visible = crtc->active && primary->get_hw_state(primary);
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intel_set_plane_visible(to_intel_crtc_state(crtc->base.state),
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to_intel_plane_state(primary->base.state),
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@ -866,6 +866,7 @@ struct intel_plane {
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const struct intel_plane_state *plane_state);
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void (*disable_plane)(struct intel_plane *plane,
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struct intel_crtc *crtc);
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bool (*get_hw_state)(struct intel_plane *plane);
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int (*check_plane)(struct intel_plane *plane,
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struct intel_crtc_state *crtc_state,
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struct intel_plane_state *state);
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@ -1934,6 +1935,7 @@ void skl_update_plane(struct intel_plane *plane,
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const struct intel_crtc_state *crtc_state,
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const struct intel_plane_state *plane_state);
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void skl_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc);
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bool skl_plane_get_hw_state(struct intel_plane *plane);
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/* intel_tv.c */
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void intel_tv_init(struct drm_i915_private *dev_priv);
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@ -325,6 +325,26 @@ skl_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc)
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spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
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}
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bool
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skl_plane_get_hw_state(struct intel_plane *plane)
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{
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struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
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enum intel_display_power_domain power_domain;
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enum plane_id plane_id = plane->id;
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enum pipe pipe = plane->pipe;
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bool ret;
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power_domain = POWER_DOMAIN_PIPE(pipe);
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if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
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return false;
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ret = I915_READ(PLANE_CTL(pipe, plane_id)) & PLANE_CTL_ENABLE;
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intel_display_power_put(dev_priv, power_domain);
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return ret;
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}
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static void
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chv_update_csc(struct intel_plane *plane, uint32_t format)
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{
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@ -502,6 +522,26 @@ vlv_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc)
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spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
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}
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static bool
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vlv_plane_get_hw_state(struct intel_plane *plane)
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{
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struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
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enum intel_display_power_domain power_domain;
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enum plane_id plane_id = plane->id;
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enum pipe pipe = plane->pipe;
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bool ret;
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power_domain = POWER_DOMAIN_PIPE(pipe);
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if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
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return false;
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ret = I915_READ(SPCNTR(pipe, plane_id)) & SP_ENABLE;
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intel_display_power_put(dev_priv, power_domain);
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return ret;
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}
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static u32 ivb_sprite_ctl(const struct intel_crtc_state *crtc_state,
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const struct intel_plane_state *plane_state)
|
||||
{
|
||||
@ -642,6 +682,25 @@ ivb_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc)
|
||||
spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
|
||||
}
|
||||
|
||||
static bool
|
||||
ivb_plane_get_hw_state(struct intel_plane *plane)
|
||||
{
|
||||
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
|
||||
enum intel_display_power_domain power_domain;
|
||||
enum pipe pipe = plane->pipe;
|
||||
bool ret;
|
||||
|
||||
power_domain = POWER_DOMAIN_PIPE(pipe);
|
||||
if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
|
||||
return false;
|
||||
|
||||
ret = I915_READ(SPRCTL(pipe)) & SPRITE_ENABLE;
|
||||
|
||||
intel_display_power_put(dev_priv, power_domain);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static u32 g4x_sprite_ctl(const struct intel_crtc_state *crtc_state,
|
||||
const struct intel_plane_state *plane_state)
|
||||
{
|
||||
@ -773,6 +832,25 @@ g4x_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc)
|
||||
spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
|
||||
}
|
||||
|
||||
static bool
|
||||
g4x_plane_get_hw_state(struct intel_plane *plane)
|
||||
{
|
||||
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
|
||||
enum intel_display_power_domain power_domain;
|
||||
enum pipe pipe = plane->pipe;
|
||||
bool ret;
|
||||
|
||||
power_domain = POWER_DOMAIN_PIPE(pipe);
|
||||
if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
|
||||
return false;
|
||||
|
||||
ret = I915_READ(DVSCNTR(pipe)) & DVS_ENABLE;
|
||||
|
||||
intel_display_power_put(dev_priv, power_domain);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int
|
||||
intel_check_sprite_plane(struct intel_plane *plane,
|
||||
struct intel_crtc_state *crtc_state,
|
||||
@ -1231,6 +1309,7 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv,
|
||||
|
||||
intel_plane->update_plane = skl_update_plane;
|
||||
intel_plane->disable_plane = skl_disable_plane;
|
||||
intel_plane->get_hw_state = skl_plane_get_hw_state;
|
||||
|
||||
plane_formats = skl_plane_formats;
|
||||
num_plane_formats = ARRAY_SIZE(skl_plane_formats);
|
||||
@ -1241,6 +1320,7 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv,
|
||||
|
||||
intel_plane->update_plane = skl_update_plane;
|
||||
intel_plane->disable_plane = skl_disable_plane;
|
||||
intel_plane->get_hw_state = skl_plane_get_hw_state;
|
||||
|
||||
plane_formats = skl_plane_formats;
|
||||
num_plane_formats = ARRAY_SIZE(skl_plane_formats);
|
||||
@ -1251,6 +1331,7 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv,
|
||||
|
||||
intel_plane->update_plane = vlv_update_plane;
|
||||
intel_plane->disable_plane = vlv_disable_plane;
|
||||
intel_plane->get_hw_state = vlv_plane_get_hw_state;
|
||||
|
||||
plane_formats = vlv_plane_formats;
|
||||
num_plane_formats = ARRAY_SIZE(vlv_plane_formats);
|
||||
@ -1266,6 +1347,7 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv,
|
||||
|
||||
intel_plane->update_plane = ivb_update_plane;
|
||||
intel_plane->disable_plane = ivb_disable_plane;
|
||||
intel_plane->get_hw_state = ivb_plane_get_hw_state;
|
||||
|
||||
plane_formats = snb_plane_formats;
|
||||
num_plane_formats = ARRAY_SIZE(snb_plane_formats);
|
||||
@ -1276,6 +1358,7 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv,
|
||||
|
||||
intel_plane->update_plane = g4x_update_plane;
|
||||
intel_plane->disable_plane = g4x_disable_plane;
|
||||
intel_plane->get_hw_state = g4x_plane_get_hw_state;
|
||||
|
||||
modifiers = i9xx_plane_format_modifiers;
|
||||
if (IS_GEN6(dev_priv)) {
|
||||
|
||||
Loading…
Reference in New Issue
Block a user