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drm/i915: Gen3 HWSTAM is actually 32 bits

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Bspec claims that HWSTAM is only 16 bits on gen3, but the other
interrupts registers are 32 bits and there are 18 valid interrupt
bits. Hence a 16 bit HWSTAM wouldn't be able to contain all the
bits, so it seems the spec is incorrect about the size of the
register. And indeed I can clear bits 16 and 17 just fine with
a 32 bit write. So let's adjust the code to treat the register
as 32 bits.

Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20170818183705.27850-14-ville.syrjala@linux.intel.com
This commit is contained in:
Ville Syrjälä 2017-08-18 21:37:02 +03:00
parent af722d280e
commit 5190707e7a
1 changed files with 2 additions and 2 deletions
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4
drivers/gpu/drm/i915/i915_irq.c
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@ -3755,7 +3755,7 @@ static void i915_irq_preinstall(struct drm_device * dev)
i9xx_pipestat_irq_reset(dev_priv);
I915_WRITE16(HWSTAM, 0xeffe);
I915_WRITE(HWSTAM, 0xffffeffe);
GEN3_IRQ_RESET();
}
@ -3862,7 +3862,7 @@ static void i915_irq_uninstall(struct drm_device * dev)
i9xx_pipestat_irq_reset(dev_priv);
I915_WRITE16(HWSTAM, 0xffff);
I915_WRITE(HWSTAM, 0xffffffff);
GEN3_IRQ_RESET();
}