drm/i915: Add 10bit LUT for ilk/snb

Plop in support for 10bit LUT on ilk/snb.

There is no split gamma mode on these platforms, so we have
to choose between degamma and gamma. That could be a runtime choice
but for now let's just advertize the gamma as having 1024 entries.
We'll also keep the ctm hidden for now.

v2: Don't use I915_WRITE_FW() yet
    Introduce bool has_ctm (Maarten)
    Call drm_crtc_enable_color_mgmt() uncoditionally (Maarten)

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190401200231.2333-5-ville.syrjala@linux.intel.com
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
This commit is contained in:
Ville Syrjälä 2019-04-01 23:02:28 +03:00
parent c21ce2effc
commit 514462caf7
3 changed files with 52 additions and 10 deletions

View File

@ -116,6 +116,8 @@
[PIPE_C] = IVB_CURSOR_C_OFFSET, \ [PIPE_C] = IVB_CURSOR_C_OFFSET, \
} }
#define ILK_COLORS \
.color = { .gamma_lut_size = 1024 }
#define IVB_COLORS \ #define IVB_COLORS \
.color = { .degamma_lut_size = 512, .gamma_lut_size = 512 } .color = { .degamma_lut_size = 512, .gamma_lut_size = 512 }
#define CHV_COLORS \ #define CHV_COLORS \
@ -332,6 +334,7 @@ static const struct intel_device_info intel_gm45_info = {
.has_rc6 = 0, \ .has_rc6 = 0, \
I9XX_PIPE_OFFSETS, \ I9XX_PIPE_OFFSETS, \
I9XX_CURSOR_OFFSETS, \ I9XX_CURSOR_OFFSETS, \
ILK_COLORS, \
GEN_DEFAULT_PAGE_SIZES GEN_DEFAULT_PAGE_SIZES
static const struct intel_device_info intel_ironlake_d_info = { static const struct intel_device_info intel_ironlake_d_info = {
@ -360,6 +363,7 @@ static const struct intel_device_info intel_ironlake_m_info = {
.ppgtt_size = 31, \ .ppgtt_size = 31, \
I9XX_PIPE_OFFSETS, \ I9XX_PIPE_OFFSETS, \
I9XX_CURSOR_OFFSETS, \ I9XX_CURSOR_OFFSETS, \
ILK_COLORS, \
GEN_DEFAULT_PAGE_SIZES GEN_DEFAULT_PAGE_SIZES
#define SNB_D_PLATFORM \ #define SNB_D_PLATFORM \

View File

@ -7209,6 +7209,15 @@ enum {
#define _LGC_PALETTE_B 0x4a800 #define _LGC_PALETTE_B 0x4a800
#define LGC_PALETTE(pipe, i) _MMIO(_PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B) + (i) * 4) #define LGC_PALETTE(pipe, i) _MMIO(_PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B) + (i) * 4)
/* ilk/snb precision palette */
#define _PREC_PALETTE_A 0x4b000
#define _PREC_PALETTE_B 0x4c000
#define PREC_PALETTE(pipe, i) _MMIO(_PIPE(pipe, _PREC_PALETTE_A, _PREC_PALETTE_B) + (i) * 4)
#define _PREC_PIPEAGCMAX 0x4d000
#define _PREC_PIPEBGCMAX 0x4d010
#define PREC_PIPEGCMAX(pipe, i) _MMIO(_PIPE(pipe, _PIPEAGCMAX, _PIPEBGCMAX) + (i) * 4)
#define _GAMMA_MODE_A 0x4a480 #define _GAMMA_MODE_A 0x4a480
#define _GAMMA_MODE_B 0x4ac80 #define _GAMMA_MODE_B 0x4ac80
#define GAMMA_MODE(pipe) _MMIO_PIPE(pipe, _GAMMA_MODE_A, _GAMMA_MODE_B) #define GAMMA_MODE(pipe) _MMIO_PIPE(pipe, _GAMMA_MODE_A, _GAMMA_MODE_B)

View File

@ -468,6 +468,29 @@ static void skl_color_commit(const struct intel_crtc_state *crtc_state)
ilk_load_csc_matrix(crtc_state); ilk_load_csc_matrix(crtc_state);
} }
static void ilk_load_lut_10(struct intel_crtc *crtc,
const struct drm_property_blob *blob)
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
const struct drm_color_lut *lut = blob->data;
int i, lut_size = drm_color_lut_size(blob);
enum pipe pipe = crtc->pipe;
for (i = 0; i < lut_size; i++)
I915_WRITE(PREC_PALETTE(pipe, i), ilk_lut_10(&lut[i]));
}
static void ilk_load_luts(const struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
const struct drm_property_blob *gamma_lut = crtc_state->base.gamma_lut;
if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
i9xx_load_luts(crtc_state);
else
ilk_load_lut_10(crtc, gamma_lut);
}
/* /*
* IVB/HSW Bspec / PAL_PREC_INDEX: * IVB/HSW Bspec / PAL_PREC_INDEX:
* "Restriction : Index auto increment mode is not * "Restriction : Index auto increment mode is not
@ -967,6 +990,15 @@ static int chv_color_check(struct intel_crtc_state *crtc_state)
return 0; return 0;
} }
static u32 ilk_gamma_mode(const struct intel_crtc_state *crtc_state)
{
if (!crtc_state->gamma_enable ||
crtc_state_is_legacy_gamma(crtc_state))
return GAMMA_MODE_MODE_8BIT;
else
return GAMMA_MODE_MODE_10BIT;
}
static int ilk_color_check(struct intel_crtc_state *crtc_state) static int ilk_color_check(struct intel_crtc_state *crtc_state)
{ {
int ret; int ret;
@ -986,8 +1018,7 @@ static int ilk_color_check(struct intel_crtc_state *crtc_state)
*/ */
crtc_state->csc_enable = false; crtc_state->csc_enable = false;
/* We don't expose fancy gamma modes on ilk/snb currently */ crtc_state->gamma_mode = ilk_gamma_mode(crtc_state);
crtc_state->gamma_mode = GAMMA_MODE_MODE_8BIT;
crtc_state->csc_mode = 0; crtc_state->csc_mode = 0;
@ -1145,6 +1176,7 @@ static int icl_color_check(struct intel_crtc_state *crtc_state)
void intel_color_init(struct intel_crtc *crtc) void intel_color_init(struct intel_crtc *crtc)
{ {
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
bool has_ctm = INTEL_INFO(dev_priv)->color.degamma_lut_size != 0;
drm_mode_crtc_set_gamma_size(&crtc->base, 256); drm_mode_crtc_set_gamma_size(&crtc->base, 256);
@ -1184,14 +1216,11 @@ void intel_color_init(struct intel_crtc *crtc)
else if (INTEL_GEN(dev_priv) >= 7) else if (INTEL_GEN(dev_priv) >= 7)
dev_priv->display.load_luts = ivb_load_luts; dev_priv->display.load_luts = ivb_load_luts;
else else
dev_priv->display.load_luts = i9xx_load_luts; dev_priv->display.load_luts = ilk_load_luts;
} }
/* Enable color management support when we have degamma & gamma LUTs. */ drm_crtc_enable_color_mgmt(&crtc->base,
if (INTEL_INFO(dev_priv)->color.degamma_lut_size != 0 && INTEL_INFO(dev_priv)->color.degamma_lut_size,
INTEL_INFO(dev_priv)->color.gamma_lut_size != 0) has_ctm,
drm_crtc_enable_color_mgmt(&crtc->base, INTEL_INFO(dev_priv)->color.gamma_lut_size);
INTEL_INFO(dev_priv)->color.degamma_lut_size,
true,
INTEL_INFO(dev_priv)->color.gamma_lut_size);
} }