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net: stmmac: simplify the common DMA init API
Use struct stmmac_dma_cfg *dma_cfg as an argument rather than using all the struct members as individual arguments. Signed-off-by: Niklas Cassel <niklas.cassel@axis.com> Acked-by: Alexandre Torgue <alexandre.torgue@st.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -412,8 +412,8 @@ extern const struct stmmac_desc_ops ndesc_ops;
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struct stmmac_dma_ops {
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/* DMA core initialization */
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int (*reset)(void __iomem *ioaddr);
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void (*init)(void __iomem *ioaddr, int pbl, int fb, int mb,
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int aal, u32 dma_tx, u32 dma_rx, int atds);
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void (*init)(void __iomem *ioaddr, struct stmmac_dma_cfg *dma_cfg,
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u32 dma_tx, u32 dma_rx, int atds);
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/* Configure the AXI Bus Mode Register */
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void (*axi)(void __iomem *ioaddr, struct stmmac_axi *axi);
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/* Dump DMA registers */
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@ -84,8 +84,9 @@ static void dwmac1000_dma_axi(void __iomem *ioaddr, struct stmmac_axi *axi)
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writel(value, ioaddr + DMA_AXI_BUS_MODE);
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}
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static void dwmac1000_dma_init(void __iomem *ioaddr, int pbl, int fb, int mb,
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int aal, u32 dma_tx, u32 dma_rx, int atds)
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static void dwmac1000_dma_init(void __iomem *ioaddr,
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struct stmmac_dma_cfg *dma_cfg,
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u32 dma_tx, u32 dma_rx, int atds)
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{
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u32 value = readl(ioaddr + DMA_BUS_MODE);
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@ -101,20 +102,20 @@ static void dwmac1000_dma_init(void __iomem *ioaddr, int pbl, int fb, int mb,
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*/
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value |= DMA_BUS_MODE_MAXPBL;
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value &= ~DMA_BUS_MODE_PBL_MASK;
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value |= (pbl << DMA_BUS_MODE_PBL_SHIFT);
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value |= (dma_cfg->pbl << DMA_BUS_MODE_PBL_SHIFT);
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/* Set the Fixed burst mode */
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if (fb)
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if (dma_cfg->fixed_burst)
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value |= DMA_BUS_MODE_FB;
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/* Mixed Burst has no effect when fb is set */
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if (mb)
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if (dma_cfg->mixed_burst)
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value |= DMA_BUS_MODE_MB;
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if (atds)
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value |= DMA_BUS_MODE_ATDS;
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if (aal)
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if (dma_cfg->aal)
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value |= DMA_BUS_MODE_AAL;
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writel(value, ioaddr + DMA_BUS_MODE);
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@ -32,11 +32,12 @@
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#include "dwmac100.h"
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#include "dwmac_dma.h"
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static void dwmac100_dma_init(void __iomem *ioaddr, int pbl, int fb, int mb,
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int aal, u32 dma_tx, u32 dma_rx, int atds)
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static void dwmac100_dma_init(void __iomem *ioaddr,
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struct stmmac_dma_cfg *dma_cfg,
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u32 dma_tx, u32 dma_rx, int atds)
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{
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/* Enable Application Access by writing to DMA CSR0 */
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writel(DMA_BUS_MODE_DEFAULT | (pbl << DMA_BUS_MODE_PBL_SHIFT),
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writel(DMA_BUS_MODE_DEFAULT | (dma_cfg->pbl << DMA_BUS_MODE_PBL_SHIFT),
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ioaddr + DMA_BUS_MODE);
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/* Mask interrupts by writing to CSR7 */
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@ -99,27 +99,29 @@ static void dwmac4_dma_init_channel(void __iomem *ioaddr, int pbl,
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writel(dma_rx_phy, ioaddr + DMA_CHAN_RX_BASE_ADDR(channel));
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}
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static void dwmac4_dma_init(void __iomem *ioaddr, int pbl, int fb, int mb,
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int aal, u32 dma_tx, u32 dma_rx, int atds)
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static void dwmac4_dma_init(void __iomem *ioaddr,
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struct stmmac_dma_cfg *dma_cfg,
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u32 dma_tx, u32 dma_rx, int atds)
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{
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u32 value = readl(ioaddr + DMA_SYS_BUS_MODE);
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int i;
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/* Set the Fixed burst mode */
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if (fb)
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if (dma_cfg->fixed_burst)
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value |= DMA_SYS_BUS_FB;
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/* Mixed Burst has no effect when fb is set */
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if (mb)
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if (dma_cfg->mixed_burst)
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value |= DMA_SYS_BUS_MB;
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if (aal)
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if (dma_cfg->aal)
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value |= DMA_SYS_BUS_AAL;
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writel(value, ioaddr + DMA_SYS_BUS_MODE);
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for (i = 0; i < DMA_CHANNEL_NB_MAX; i++)
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dwmac4_dma_init_channel(ioaddr, pbl, dma_tx, dma_rx, i);
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dwmac4_dma_init_channel(ioaddr, dma_cfg->pbl,
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dma_tx, dma_rx, i);
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}
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static void _dwmac4_dump_dma_regs(void __iomem *ioaddr, u32 channel)
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@ -1595,11 +1595,7 @@ static int stmmac_init_dma_engine(struct stmmac_priv *priv)
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return ret;
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}
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priv->hw->dma->init(priv->ioaddr,
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priv->plat->dma_cfg->pbl,
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priv->plat->dma_cfg->fixed_burst,
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priv->plat->dma_cfg->mixed_burst,
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priv->plat->dma_cfg->aal,
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priv->hw->dma->init(priv->ioaddr, priv->plat->dma_cfg,
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priv->dma_tx_phy, priv->dma_rx_phy, atds);
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if (priv->synopsys_id >= DWMAC_CORE_4_00) {
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